1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ 2; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ 4; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 5; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ 6; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 7; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ 8; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 9; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ 10; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 11; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ 12; RUN: -check-prefix=R6 -check-prefix=GP32 13; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ 14; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 15; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ 16; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 17; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ 18; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 19; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ 20; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 21; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ 22; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 23; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ 24; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 25; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ 26; RUN: -check-prefix=R6 -check-prefix=64R6 27 28define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) { 29entry: 30; ALL-LABEL: sdiv_i1: 31 32 ; NOT-R6: div $zero, $4, $5 33 ; NOT-R6: teq $5, $zero, 7 34 ; NOT-R6: mflo $[[T0:[0-9]+]] 35 ; FIXME: The sll/sra instructions are redundant since div is signed. 36 ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31 37 ; NOT-R6: sra $2, $[[T1]], 31 38 39 ; R6: div $[[T0:[0-9]+]], $4, $5 40 ; R6: teq $5, $zero, 7 41 ; FIXME: The sll/sra instructions are redundant since div is signed. 42 ; R6: sll $[[T1:[0-9]+]], $[[T0]], 31 43 ; R6: sra $2, $[[T1]], 31 44 45 %r = sdiv i1 %a, %b 46 ret i1 %r 47} 48 49define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) { 50entry: 51; ALL-LABEL: sdiv_i8: 52 53 ; NOT-R2-R6: div $zero, $4, $5 54 ; NOT-R2-R6: teq $5, $zero, 7 55 ; NOT-R2-R6: mflo $[[T0:[0-9]+]] 56 ; FIXME: The sll/sra instructions are redundant since div is signed. 57 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24 58 ; NOT-R2-R6: sra $2, $[[T1]], 24 59 60 ; R2-R5: div $zero, $4, $5 61 ; R2-R5: teq $5, $zero, 7 62 ; R2-R5: mflo $[[T0:[0-9]+]] 63 ; FIXME: This instruction is redundant. 64 ; R2-R5: seb $2, $[[T0]] 65 66 ; R6: div $[[T0:[0-9]+]], $4, $5 67 ; R6: teq $5, $zero, 7 68 ; FIXME: This instruction is redundant. 69 ; R6: seb $2, $[[T0]] 70 71 %r = sdiv i8 %a, %b 72 ret i8 %r 73} 74 75define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) { 76entry: 77; ALL-LABEL: sdiv_i16: 78 79 ; NOT-R2-R6: div $zero, $4, $5 80 ; NOT-R2-R6: teq $5, $zero, 7 81 ; NOT-R2-R6: mflo $[[T0:[0-9]+]] 82 ; FIXME: The sll/sra instructions are redundant since div is signed. 83 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16 84 ; NOT-R2-R6: sra $2, $[[T1]], 16 85 86 ; R2-R5: div $zero, $4, $5 87 ; R2-R5: teq $5, $zero, 7 88 ; R2-R5: mflo $[[T0:[0-9]+]] 89 ; FIXME: This is instruction is redundant since div is signed. 90 ; R2-R5: seh $2, $[[T0]] 91 92 ; R6: div $[[T0:[0-9]+]], $4, $5 93 ; R6: teq $5, $zero, 7 94 ; FIXME: This is instruction is redundant since div is signed. 95 ; R6: seh $2, $[[T0]] 96 97 %r = sdiv i16 %a, %b 98 ret i16 %r 99} 100 101define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) { 102entry: 103; ALL-LABEL: sdiv_i32: 104 105 ; NOT-R6: div $zero, $4, $5 106 ; NOT-R6: teq $5, $zero, 7 107 ; NOT-R6: mflo $2 108 109 ; R6: div $2, $4, $5 110 ; R6: teq $5, $zero, 7 111 112 %r = sdiv i32 %a, %b 113 ret i32 %r 114} 115 116define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) { 117entry: 118; ALL-LABEL: sdiv_i64: 119 120 ; GP32: lw $25, %call16(__divdi3)($gp) 121 122 ; GP64-NOT-R6: ddiv $zero, $4, $5 123 ; GP64-NOT-R6: teq $5, $zero, 7 124 ; GP64-NOT-R6: mflo $2 125 126 ; 64R6: ddiv $2, $4, $5 127 ; 64R6: teq $5, $zero, 7 128 129 %r = sdiv i64 %a, %b 130 ret i64 %r 131} 132 133define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) { 134entry: 135 ; ALL-LABEL: sdiv_i128: 136 137 ; GP32: lw $25, %call16(__divti3)($gp) 138 139 ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) 140 ; 64R6: ld $25, %call16(__divti3)($gp) 141 142 %r = sdiv i128 %a, %b 143 ret i128 %r 144} 145