1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ 2; RUN: -check-prefix=ALL -check-prefix=GP32 \ 3; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6 4; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ 5; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \ 6; RUN: -check-prefix=32R1-R5 7; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ 8; RUN: -check-prefix=ALL -check-prefix=GP32 \ 9; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 10; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ 11; RUN: -check-prefix=ALL -check-prefix=GP32 \ 12; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 13; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ 14; RUN: -check-prefix=ALL -check-prefix=GP32 \ 15; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 16; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ 17; RUN: -check-prefix=ALL -check-prefix=GP32 \ 18; RUN: -check-prefix=32R6 -check-prefix=R2-R6 19; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ 20; RUN: -check-prefix=ALL -check-prefix=GP64 \ 21; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6 22; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ 23; RUN: -check-prefix=ALL -check-prefix=GP64 \ 24; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 25; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ 26; RUN: -check-prefix=ALL -check-prefix=GP64 \ 27; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 28; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ 29; RUN: -check-prefix=ALL -check-prefix=GP64 \ 30; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 31; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ 32; RUN: -check-prefix=ALL -check-prefix=GP64 \ 33; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 34; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ 35; RUN: -check-prefix=ALL -check-prefix=GP64 \ 36; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 37; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ 38; RUN: -check-prefix=ALL -check-prefix=GP64 \ 39; RUN: -check-prefix=64R6 -check-prefix=R2-R6 40 41define signext i1 @shl_i1(i1 signext %a, i1 signext %b) { 42entry: 43; ALL-LABEL: shl_i1: 44 45 ; ALL: move $2, $4 46 47 %r = shl i1 %a, %b 48 ret i1 %r 49} 50 51define signext i8 @shl_i8(i8 signext %a, i8 signext %b) { 52entry: 53; ALL-LABEL: shl_i8: 54 55 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255 56 ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] 57 ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 24 58 ; NOT-R2-R6: sra $2, $[[T2]], 24 59 60 ; R2-R6: andi $[[T0:[0-9]+]], $5, 255 61 ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] 62 ; R2-R6: seb $2, $[[T1]] 63 64 %r = shl i8 %a, %b 65 ret i8 %r 66} 67 68define signext i16 @shl_i16(i16 signext %a, i16 signext %b) { 69entry: 70; ALL-LABEL: shl_i16: 71 72 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535 73 ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] 74 ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 16 75 ; NOT-R2-R6: sra $2, $[[T2]], 16 76 77 ; R2-R6: andi $[[T0:[0-9]+]], $5, 65535 78 ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] 79 ; R2-R6: seh $2, $[[T1]] 80 81 %r = shl i16 %a, %b 82 ret i16 %r 83} 84 85define signext i32 @shl_i32(i32 signext %a, i32 signext %b) { 86entry: 87; ALL-LABEL: shl_i32: 88 89 ; ALL: sllv $2, $4, $5 90 91 %r = shl i32 %a, %b 92 ret i32 %r 93} 94 95define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { 96entry: 97; ALL-LABEL: shl_i64: 98 99 ; M2: sllv $[[T0:[0-9]+]], $5, $7 100 ; M2: andi $[[T1:[0-9]+]], $7, 32 101 ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] 102 ; M2: move $2, $[[T0]] 103 ; M2: sllv $[[T2:[0-9]+]], $4, $7 104 ; M2: not $[[T3:[0-9]+]], $7 105 ; M2: srl $[[T4:[0-9]+]], $5, 1 106 ; M2: srlv $[[T5:[0-9]+]], $[[T4]], $[[T3]] 107 ; M2: or $2, $[[T2]], $[[T3]] 108 ; M2: $[[BB0]]: 109 ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] 110 ; M2: addiu $3, $zero, 0 111 ; M2: move $3, $[[T0]] 112 ; M2: $[[BB1]]: 113 ; M2: jr $ra 114 ; M2: nop 115 116 ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7 117 ; 32R1-R5: not $[[T1:[0-9]+]], $7 118 ; 32R1-R5: srl $[[T2:[0-9]+]], $5, 1 119 ; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] 120 ; 32R1-R5: or $2, $[[T0]], $[[T3]] 121 ; 32R1-R5: sllv $[[T4:[0-9]+]], $5, $7 122 ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 123 ; 32R1-R5: movn $2, $[[T4]], $[[T5]] 124 ; 32R1-R5: jr $ra 125 ; 32R1-R5: movn $3, $zero, $[[T5]] 126 127 ; 32R6: sllv $[[T0:[0-9]+]], $4, $7 128 ; 32R6: not $[[T1:[0-9]+]], $7 129 ; 32R6: srl $[[T2:[0-9]+]], $5, 1 130 ; 32R6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] 131 ; 32R6: or $[[T4:[0-9]+]], $[[T0]], $[[T3]] 132 ; 32R6: andi $[[T5:[0-9]+]], $7, 32 133 ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T2]] 134 ; 32R6: sllv $[[T7:[0-9]+]], $5, $7 135 ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] 136 ; 32R6: or $2, $[[T8]], $[[T6]] 137 ; 32R6: jr $ra 138 ; 32R6: seleqz $3, $[[T7]], $[[T5]] 139 140 ; GP64: sll $[[T0:[0-9]+]], $5, 0 141 ; GP64: dsllv $2, $4, $1 142 143 %r = shl i64 %a, %b 144 ret i64 %r 145} 146 147define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { 148entry: 149; ALL-LABEL: shl_i128: 150 151 ; GP32: lw $25, %call16(__ashlti3)($gp) 152 153 ; M3: sll $[[T0:[0-9]+]], $7, 0 154 ; M3: dsllv $[[T1:[0-9]+]], $5, $[[T0]] 155 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 156 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] 157 ; M3: move $2, $[[T1]] 158 ; M3: dsllv $[[T4:[0-9]+]], $4, $[[T0]] 159 ; M3: dsrl $[[T5:[0-9]+]], $5, 1 160 ; M3: not $[[T6:[0-9]+]], $[[T0]] 161 ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] 162 ; M3: or $2, $[[T4]], $[[T7]] 163 ; M3: $[[BB0]]: 164 ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] 165 ; M3: daddiu $3, $zero, 0 166 ; M3: move $3, $[[T1]] 167 ; M3: $[[BB1]]: 168 ; M3: jr $ra 169 ; M3: nop 170 171 ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 172 ; GP64-NOT-R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]] 173 ; GP64-NOT-R6: dsrl $[[T2:[0-9]+]], $5, 1 174 ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] 175 ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]] 176 ; GP64-NOT-R6: or $2, $[[T1]], $[[T4]] 177 ; GP64-NOT-R6: dsllv $3, $5, $[[T0]] 178 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 179 ; GP64-NOT-R6: movn $2, $3, $[[T5]] 180 ; GP64-NOT-R6: jr $ra 181 ; GP64-NOT-R6: movn $3, $zero, $1 182 183 ; 64R6: sll $[[T0:[0-9]+]], $7, 0 184 ; 64R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]] 185 ; 64R6: dsrl $[[T2:[0-9]+]], $5, 1 186 ; 64R6: not $[[T3:[0-9]+]], $[[T0]] 187 ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]] 188 ; 64R6: or $[[T5:[0-9]+]], $[[T1]], $[[T4]] 189 ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32 190 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 191 ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] 192 ; 64R6: dsllv $[[T9:[0-9]+]], $5, $[[T0]] 193 ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] 194 ; 64R6: or $2, $[[T10]], $[[T8]] 195 ; 64R6: jr $ra 196 ; 64R6: seleqz $3, $[[T0]], $[[T7]] 197 198 %r = shl i128 %a, %b 199 ret i128 %r 200} 201