1; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 4 5; FUNC-LABEL: {{^}}test2: 6; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 7; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 8 9; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 10; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 11 12define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { 13 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 14 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in 15 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr 16 %result = and <2 x i32> %a, %b 17 store <2 x i32> %result, <2 x i32> addrspace(1)* %out 18 ret void 19} 20 21; FUNC-LABEL: {{^}}test4: 22; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 23; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 24; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 25; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 26 27; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 28; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 29; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 30; SI: v_and_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 31 32define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { 33 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 34 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in 35 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr 36 %result = and <4 x i32> %a, %b 37 store <4 x i32> %result, <4 x i32> addrspace(1)* %out 38 ret void 39} 40 41; FUNC-LABEL: {{^}}s_and_i32: 42; SI: s_and_b32 43define void @s_and_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { 44 %and = and i32 %a, %b 45 store i32 %and, i32 addrspace(1)* %out, align 4 46 ret void 47} 48 49; FUNC-LABEL: {{^}}s_and_constant_i32: 50; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687 51define void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) { 52 %and = and i32 %a, 1234567 53 store i32 %and, i32 addrspace(1)* %out, align 4 54 ret void 55} 56 57; FUNC-LABEL: {{^}}v_and_i32: 58; SI: v_and_b32 59define void @v_and_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) { 60 %a = load i32, i32 addrspace(1)* %aptr, align 4 61 %b = load i32, i32 addrspace(1)* %bptr, align 4 62 %and = and i32 %a, %b 63 store i32 %and, i32 addrspace(1)* %out, align 4 64 ret void 65} 66 67; FUNC-LABEL: {{^}}v_and_constant_i32 68; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}} 69define void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) { 70 %a = load i32, i32 addrspace(1)* %aptr, align 4 71 %and = and i32 %a, 1234567 72 store i32 %and, i32 addrspace(1)* %out, align 4 73 ret void 74} 75 76; FUNC-LABEL: {{^}}v_and_inline_imm_64_i32 77; SI: v_and_b32_e32 v{{[0-9]+}}, 64, v{{[0-9]+}} 78define void @v_and_inline_imm_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) { 79 %a = load i32, i32 addrspace(1)* %aptr, align 4 80 %and = and i32 %a, 64 81 store i32 %and, i32 addrspace(1)* %out, align 4 82 ret void 83} 84 85; FUNC-LABEL: {{^}}v_and_inline_imm_neg_16_i32 86; SI: v_and_b32_e32 v{{[0-9]+}}, -16, v{{[0-9]+}} 87define void @v_and_inline_imm_neg_16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) { 88 %a = load i32, i32 addrspace(1)* %aptr, align 4 89 %and = and i32 %a, -16 90 store i32 %and, i32 addrspace(1)* %out, align 4 91 ret void 92} 93 94; FUNC-LABEL: {{^}}s_and_i64 95; SI: s_and_b64 96define void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { 97 %and = and i64 %a, %b 98 store i64 %and, i64 addrspace(1)* %out, align 8 99 ret void 100} 101 102; FIXME: Should use SGPRs 103; FUNC-LABEL: {{^}}s_and_i1: 104; SI: v_and_b32 105define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) { 106 %and = and i1 %a, %b 107 store i1 %and, i1 addrspace(1)* %out 108 ret void 109} 110 111; FUNC-LABEL: {{^}}s_and_constant_i64 112; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} 113define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) { 114 %and = and i64 %a, 281474976710655 115 store i64 %and, i64 addrspace(1)* %out, align 8 116 ret void 117} 118 119; FUNC-LABEL: {{^}}v_and_i64: 120; SI: v_and_b32 121; SI: v_and_b32 122define void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { 123 %a = load i64, i64 addrspace(1)* %aptr, align 8 124 %b = load i64, i64 addrspace(1)* %bptr, align 8 125 %and = and i64 %a, %b 126 store i64 %and, i64 addrspace(1)* %out, align 8 127 ret void 128} 129 130; FUNC-LABEL: {{^}}v_and_i64_br: 131; SI: v_and_b32 132; SI: v_and_b32 133define void @v_and_i64_br(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i32 %cond) { 134entry: 135 %tmp0 = icmp eq i32 %cond, 0 136 br i1 %tmp0, label %if, label %endif 137 138if: 139 %a = load i64, i64 addrspace(1)* %aptr, align 8 140 %b = load i64, i64 addrspace(1)* %bptr, align 8 141 %and = and i64 %a, %b 142 br label %endif 143 144endif: 145 %tmp1 = phi i64 [%and, %if], [0, %entry] 146 store i64 %tmp1, i64 addrspace(1)* %out, align 8 147 ret void 148} 149 150; FUNC-LABEL: {{^}}v_and_constant_i64: 151; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} 152; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} 153define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 154 %a = load i64, i64 addrspace(1)* %aptr, align 8 155 %and = and i64 %a, 1234567 156 store i64 %and, i64 addrspace(1)* %out, align 8 157 ret void 158} 159 160; FIXME: Replace and 0 with mov 0 161; FUNC-LABEL: {{^}}v_and_inline_imm_i64: 162; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}} 163; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}} 164define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { 165 %a = load i64, i64 addrspace(1)* %aptr, align 8 166 %and = and i64 %a, 64 167 store i64 %and, i64 addrspace(1)* %out, align 8 168 ret void 169} 170 171; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64 172; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 64 173define void @s_and_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 174 %and = and i64 %a, 64 175 store i64 %and, i64 addrspace(1)* %out, align 8 176 ret void 177} 178 179; FUNC-LABEL: {{^}}s_and_inline_imm_1_i64 180; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1 181define void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 182 %and = and i64 %a, 1 183 store i64 %and, i64 addrspace(1)* %out, align 8 184 ret void 185} 186 187; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64 188; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0 189define void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 190 %and = and i64 %a, 4607182418800017408 191 store i64 %and, i64 addrspace(1)* %out, align 8 192 ret void 193} 194 195; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64 196; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0 197define void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 198 %and = and i64 %a, 13830554455654793216 199 store i64 %and, i64 addrspace(1)* %out, align 8 200 ret void 201} 202 203; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64 204; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5 205define void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 206 %and = and i64 %a, 4602678819172646912 207 store i64 %and, i64 addrspace(1)* %out, align 8 208 ret void 209} 210 211; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64 212; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5 213define void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 214 %and = and i64 %a, 13826050856027422720 215 store i64 %and, i64 addrspace(1)* %out, align 8 216 ret void 217} 218 219; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64 220; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 2.0 221define void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 222 %and = and i64 %a, 4611686018427387904 223 store i64 %and, i64 addrspace(1)* %out, align 8 224 ret void 225} 226 227; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64 228; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -2.0 229define void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 230 %and = and i64 %a, 13835058055282163712 231 store i64 %and, i64 addrspace(1)* %out, align 8 232 ret void 233} 234 235; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64 236; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0 237define void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 238 %and = and i64 %a, 4616189618054758400 239 store i64 %and, i64 addrspace(1)* %out, align 8 240 ret void 241} 242 243; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64 244; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0 245define void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 246 %and = and i64 %a, 13839561654909534208 247 store i64 %and, i64 addrspace(1)* %out, align 8 248 ret void 249} 250 251 252; Test with the 64-bit integer bitpattern for a 32-bit float in the 253; low 32-bits, which is not a valid 64-bit inline immmediate. 254 255; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64 256; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0 257; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}} 258; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} 259define void @s_and_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 260 %and = and i64 %a, 1082130432 261 store i64 %and, i64 addrspace(1)* %out, align 8 262 ret void 263} 264 265; FIXME: Copy of -1 register 266; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64 267; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0 268; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}} 269; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]] 270; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}} 271define void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 272 %and = and i64 %a, -1065353216 273 store i64 %and, i64 addrspace(1)* %out, align 8 274 ret void 275} 276 277; Shift into upper 32-bits 278; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_4.0_i64 279; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0 280; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} 281; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} 282define void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 283 %and = and i64 %a, 4647714815446351872 284 store i64 %and, i64 addrspace(1)* %out, align 8 285 ret void 286} 287 288; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64 289; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0 290; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} 291; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} 292define void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { 293 %and = and i64 %a, 13871086852301127680 294 store i64 %and, i64 addrspace(1)* %out, align 8 295 ret void 296} 297