1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s 3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s 4 5; FUNC-LABEL: {{^}}test_udivrem: 6; EG: RECIP_UINT 7; EG-DAG: MULHI 8; EG-DAG: MULLO_INT 9; EG-DAG: SUB_INT 10; EG: CNDE_INT 11; EG: MULHI 12; EG-DAG: ADD_INT 13; EG-DAG: SUB_INT 14; EG: CNDE_INT 15; EG: MULHI 16; EG: MULLO_INT 17; EG: SUB_INT 18; EG-DAG: SETGE_UINT 19; EG-DAG: SETGE_UINT 20; EG: AND_INT 21; EG-DAG: ADD_INT 22; EG-DAG: SUB_INT 23; EG-DAG: CNDE_INT 24; EG-DAG: CNDE_INT 25; EG-DAG: ADD_INT 26; EG-DAG: SUB_INT 27; EG-DAG: CNDE_INT 28; EG-DAG: CNDE_INT 29 30; SI: v_rcp_iflag_f32_e32 [[RCP:v[0-9]+]] 31; SI-DAG: v_mul_hi_u32 [[RCP_HI:v[0-9]+]], [[RCP]] 32; SI-DAG: v_mul_lo_i32 [[RCP_LO:v[0-9]+]], [[RCP]] 33; SI-DAG: v_sub_i32_e32 [[NEG_RCP_LO:v[0-9]+]], 0, [[RCP_LO]] 34; SI: v_cndmask_b32_e64 35; SI: v_mul_hi_u32 [[E:v[0-9]+]], {{v[0-9]+}}, [[RCP]] 36; SI-DAG: v_add_i32_e32 [[RCP_A_E:v[0-9]+]], [[E]], [[RCP]] 37; SI-DAG: v_subrev_i32_e32 [[RCP_S_E:v[0-9]+]], [[E]], [[RCP]] 38; SI: v_cndmask_b32_e64 39; SI: v_mul_hi_u32 [[Quotient:v[0-9]+]] 40; SI: v_mul_lo_i32 [[Num_S_Remainder:v[0-9]+]] 41; SI-DAG: v_sub_i32_e32 [[Remainder:v[0-9]+]], {{[vs][0-9]+}}, [[Num_S_Remainder]] 42; SI-DAG: v_cndmask_b32_e64 43; SI-DAG: v_cndmask_b32_e64 44; SI: v_and_b32_e32 [[Tmp1:v[0-9]+]] 45; SI-DAG: v_add_i32_e32 [[Quotient_A_One:v[0-9]+]], 1, [[Quotient]] 46; SI-DAG: v_subrev_i32_e32 [[Quotient_S_One:v[0-9]+]], 47; SI-DAG: v_cndmask_b32_e64 48; SI-DAG: v_cndmask_b32_e64 49; SI-DAG: v_add_i32_e32 [[Remainder_A_Den:v[0-9]+]], 50; SI-DAG: v_subrev_i32_e32 [[Remainder_S_Den:v[0-9]+]], 51; SI-DAG: v_cndmask_b32_e64 52; SI-DAG: v_cndmask_b32_e64 53; SI: s_endpgm 54define void @test_udivrem(i32 addrspace(1)* %out, i32 %x, i32 %y) { 55 %result0 = udiv i32 %x, %y 56 store i32 %result0, i32 addrspace(1)* %out 57 %result1 = urem i32 %x, %y 58 store i32 %result1, i32 addrspace(1)* %out 59 ret void 60} 61 62; FUNC-LABEL: {{^}}test_udivrem_v2: 63; EG-DAG: RECIP_UINT 64; EG-DAG: MULHI 65; EG-DAG: MULLO_INT 66; EG-DAG: SUB_INT 67; EG-DAG: CNDE_INT 68; EG-DAG: MULHI 69; EG-DAG: ADD_INT 70; EG-DAG: SUB_INT 71; EG-DAG: CNDE_INT 72; EG-DAG: MULHI 73; EG-DAG: MULLO_INT 74; EG-DAG: SUB_INT 75; EG-DAG: SETGE_UINT 76; EG-DAG: SETGE_UINT 77; EG-DAG: AND_INT 78; EG-DAG: ADD_INT 79; EG-DAG: SUB_INT 80; EG-DAG: CNDE_INT 81; EG-DAG: CNDE_INT 82; EG-DAG: ADD_INT 83; EG-DAG: SUB_INT 84; EG-DAG: CNDE_INT 85; EG-DAG: CNDE_INT 86; EG-DAG: RECIP_UINT 87; EG-DAG: MULHI 88; EG-DAG: MULLO_INT 89; EG-DAG: SUB_INT 90; EG-DAG: CNDE_INT 91; EG-DAG: MULHI 92; EG-DAG: ADD_INT 93; EG-DAG: SUB_INT 94; EG-DAG: CNDE_INT 95; EG-DAG: MULHI 96; EG-DAG: MULLO_INT 97; EG-DAG: SUB_INT 98; EG-DAG: SETGE_UINT 99; EG-DAG: SETGE_UINT 100; EG-DAG: AND_INT 101; EG-DAG: ADD_INT 102; EG-DAG: SUB_INT 103; EG-DAG: CNDE_INT 104; EG-DAG: CNDE_INT 105; EG-DAG: ADD_INT 106; EG-DAG: SUB_INT 107; EG-DAG: CNDE_INT 108; EG-DAG: CNDE_INT 109 110; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]] 111; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]] 112; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]] 113; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], 0, [[FIRST_RCP_LO]] 114; SI-DAG: v_cndmask_b32_e64 115; SI-DAG: v_mul_hi_u32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]] 116; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] 117; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] 118; SI-DAG: v_cndmask_b32_e64 119; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]] 120; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]] 121; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder:v[0-9]+]], [[FIRST_Num_S_Remainder]], v{{[0-9]+}} 122; SI-DAG: v_cndmask_b32_e64 123; SI-DAG: v_cndmask_b32_e64 124; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]] 125; SI-DAG: v_add_i32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]] 126; SI-DAG: v_subrev_i32_e32 [[FIRST_Quotient_S_One:v[0-9]+]], 127; SI-DAG: v_cndmask_b32_e64 128; SI-DAG: v_cndmask_b32_e64 129; SI-DAG: v_add_i32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]], 130; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]], 131; SI-DAG: v_cndmask_b32_e64 132; SI-DAG: v_cndmask_b32_e64 133; SI-DAG: v_rcp_iflag_f32_e32 [[SECOND_RCP:v[0-9]+]] 134; SI-DAG: v_mul_hi_u32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]] 135; SI-DAG: v_mul_lo_i32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]] 136; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], 0, [[SECOND_RCP_LO]] 137; SI-DAG: v_cndmask_b32_e64 138; SI-DAG: v_mul_hi_u32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]] 139; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] 140; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] 141; SI-DAG: v_cndmask_b32_e64 142; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]] 143; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]] 144; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder:v[0-9]+]], [[SECOND_Num_S_Remainder]], v{{[0-9]+}} 145; SI-DAG: v_cndmask_b32_e64 146; SI-DAG: v_cndmask_b32_e64 147; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]] 148; SI-DAG: v_add_i32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]] 149; SI-DAG: v_subrev_i32_e32 [[SECOND_Quotient_S_One:v[0-9]+]], 150; SI-DAG: v_cndmask_b32_e64 151; SI-DAG: v_cndmask_b32_e64 152; SI-DAG: v_add_i32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]], 153; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]], 154; SI-DAG: v_cndmask_b32_e64 155; SI-DAG: v_cndmask_b32_e64 156; SI: s_endpgm 157define void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) { 158 %result0 = udiv <2 x i32> %x, %y 159 store <2 x i32> %result0, <2 x i32> addrspace(1)* %out 160 %result1 = urem <2 x i32> %x, %y 161 store <2 x i32> %result1, <2 x i32> addrspace(1)* %out 162 ret void 163} 164 165 166; FUNC-LABEL: {{^}}test_udivrem_v4: 167; EG-DAG: RECIP_UINT 168; EG-DAG: MULHI 169; EG-DAG: MULLO_INT 170; EG-DAG: SUB_INT 171; EG-DAG: CNDE_INT 172; EG-DAG: MULHI 173; EG-DAG: ADD_INT 174; EG-DAG: SUB_INT 175; EG-DAG: CNDE_INT 176; EG-DAG: MULHI 177; EG-DAG: MULLO_INT 178; EG-DAG: SUB_INT 179; EG-DAG: SETGE_UINT 180; EG-DAG: SETGE_UINT 181; EG-DAG: AND_INT 182; EG-DAG: ADD_INT 183; EG-DAG: SUB_INT 184; EG-DAG: CNDE_INT 185; EG-DAG: CNDE_INT 186; EG-DAG: ADD_INT 187; EG-DAG: SUB_INT 188; EG-DAG: CNDE_INT 189; EG-DAG: CNDE_INT 190; EG-DAG: RECIP_UINT 191; EG-DAG: MULHI 192; EG-DAG: MULLO_INT 193; EG-DAG: SUB_INT 194; EG-DAG: CNDE_INT 195; EG-DAG: MULHI 196; EG-DAG: ADD_INT 197; EG-DAG: SUB_INT 198; EG-DAG: CNDE_INT 199; EG-DAG: MULHI 200; EG-DAG: MULLO_INT 201; EG-DAG: SUB_INT 202; EG-DAG: SETGE_UINT 203; EG-DAG: SETGE_UINT 204; EG-DAG: AND_INT 205; EG-DAG: ADD_INT 206; EG-DAG: SUB_INT 207; EG-DAG: CNDE_INT 208; EG-DAG: CNDE_INT 209; EG-DAG: ADD_INT 210; EG-DAG: SUB_INT 211; EG-DAG: CNDE_INT 212; EG-DAG: CNDE_INT 213; EG-DAG: RECIP_UINT 214; EG-DAG: MULHI 215; EG-DAG: MULLO_INT 216; EG-DAG: SUB_INT 217; EG-DAG: CNDE_INT 218; EG-DAG: MULHI 219; EG-DAG: ADD_INT 220; EG-DAG: SUB_INT 221; EG-DAG: CNDE_INT 222; EG-DAG: MULHI 223; EG-DAG: MULLO_INT 224; EG-DAG: SUB_INT 225; EG-DAG: SETGE_UINT 226; EG-DAG: SETGE_UINT 227; EG-DAG: AND_INT 228; EG-DAG: ADD_INT 229; EG-DAG: SUB_INT 230; EG-DAG: CNDE_INT 231; EG-DAG: CNDE_INT 232; EG-DAG: ADD_INT 233; EG-DAG: SUB_INT 234; EG-DAG: CNDE_INT 235; EG-DAG: CNDE_INT 236; EG-DAG: RECIP_UINT 237; EG-DAG: MULHI 238; EG-DAG: MULLO_INT 239; EG-DAG: SUB_INT 240; EG-DAG: CNDE_INT 241; EG-DAG: MULHI 242; EG-DAG: ADD_INT 243; EG-DAG: SUB_INT 244; EG-DAG: CNDE_INT 245; EG-DAG: MULHI 246; EG-DAG: MULLO_INT 247; EG-DAG: SUB_INT 248; EG-DAG: SETGE_UINT 249; EG-DAG: SETGE_UINT 250; EG-DAG: AND_INT 251; EG-DAG: ADD_INT 252; EG-DAG: SUB_INT 253; EG-DAG: CNDE_INT 254; EG-DAG: CNDE_INT 255; EG-DAG: ADD_INT 256; EG-DAG: SUB_INT 257; EG-DAG: CNDE_INT 258; EG-DAG: CNDE_INT 259 260; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]] 261; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]] 262; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]] 263; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], 0, [[FIRST_RCP_LO]] 264; SI-DAG: v_cndmask_b32_e64 265; SI-DAG: v_mul_hi_u32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]] 266; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] 267; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], [[FIRST_E]], [[FIRST_RCP]] 268; SI-DAG: v_cndmask_b32_e64 269; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]] 270; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]] 271; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder:v[l0-9]+]], [[FIRST_Num_S_Remainder]], v{{[0-9]+}} 272; SI-DAG: v_cndmask_b32_e64 273; SI-DAG: v_cndmask_b32_e64 274; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]] 275; SI-DAG: v_add_i32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]] 276; SI-DAG: v_subrev_i32_e32 [[FIRST_Quotient_S_One:v[0-9]+]], 277; SI-DAG: v_cndmask_b32_e64 278; SI-DAG: v_cndmask_b32_e64 279; SI-DAG: v_add_i32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]], 280; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]], 281; SI-DAG: v_cndmask_b32_e64 282; SI-DAG: v_cndmask_b32_e64 283; SI-DAG: v_rcp_iflag_f32_e32 [[SECOND_RCP:v[0-9]+]] 284; SI-DAG: v_mul_hi_u32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]] 285; SI-DAG: v_mul_lo_i32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]] 286; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], 0, [[SECOND_RCP_LO]] 287; SI-DAG: v_cndmask_b32_e64 288; SI-DAG: v_mul_hi_u32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]] 289; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] 290; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], [[SECOND_E]], [[SECOND_RCP]] 291; SI-DAG: v_cndmask_b32_e64 292; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]] 293; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]] 294; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder:v[0-9]+]], [[SECOND_Num_S_Remainder]], v{{[0-9]+}} 295; SI-DAG: v_cndmask_b32_e64 296; SI-DAG: v_cndmask_b32_e64 297; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]] 298; SI-DAG: v_add_i32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]] 299; SI-DAG: v_subrev_i32_e32 [[SECOND_Quotient_S_One:v[0-9]+]], 300; SI-DAG: v_cndmask_b32_e64 301; SI-DAG: v_cndmask_b32_e64 302; SI-DAG: v_add_i32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]], 303; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]], 304; SI-DAG: v_cndmask_b32_e64 305; SI-DAG: v_cndmask_b32_e64 306; SI-DAG: v_rcp_iflag_f32_e32 [[THIRD_RCP:v[0-9]+]] 307; SI-DAG: v_mul_hi_u32 [[THIRD_RCP_HI:v[0-9]+]], [[THIRD_RCP]] 308; SI-DAG: v_mul_lo_i32 [[THIRD_RCP_LO:v[0-9]+]], [[THIRD_RCP]] 309; SI-DAG: v_sub_i32_e32 [[THIRD_NEG_RCP_LO:v[0-9]+]], 0, [[THIRD_RCP_LO]] 310; SI-DAG: v_cndmask_b32_e64 311; SI-DAG: v_mul_hi_u32 [[THIRD_E:v[0-9]+]], {{v[0-9]+}}, [[THIRD_RCP]] 312; SI-DAG: v_add_i32_e32 [[THIRD_RCP_A_E:v[0-9]+]], [[THIRD_E]], [[THIRD_RCP]] 313; SI-DAG: v_subrev_i32_e32 [[THIRD_RCP_S_E:v[0-9]+]], [[THIRD_E]], [[THIRD_RCP]] 314; SI-DAG: v_cndmask_b32_e64 315; SI-DAG: v_mul_hi_u32 [[THIRD_Quotient:v[0-9]+]] 316; SI-DAG: v_mul_lo_i32 [[THIRD_Num_S_Remainder:v[0-9]+]] 317; SI-DAG: v_subrev_i32_e32 [[THIRD_Remainder:v[0-9]+]], [[THIRD_Num_S_Remainder]], {{v[0-9]+}} 318; SI-DAG: v_cndmask_b32_e64 319; SI-DAG: v_cndmask_b32_e64 320; SI-DAG: v_and_b32_e32 [[THIRD_Tmp1:v[0-9]+]] 321; SI-DAG: v_add_i32_e32 [[THIRD_Quotient_A_One:v[0-9]+]], {{.*}}, [[THIRD_Quotient]] 322; SI-DAG: v_subrev_i32_e32 [[THIRD_Quotient_S_One:v[0-9]+]], 323; SI-DAG: v_cndmask_b32_e64 324; SI-DAG: v_cndmask_b32_e64 325; SI-DAG: v_add_i32_e32 [[THIRD_Remainder_A_Den:v[0-9]+]], 326; SI-DAG: v_subrev_i32_e32 [[THIRD_Remainder_S_Den:v[0-9]+]], 327; SI-DAG: v_cndmask_b32_e64 328; SI-DAG: v_cndmask_b32_e64 329; SI-DAG: v_rcp_iflag_f32_e32 [[FOURTH_RCP:v[0-9]+]] 330; SI-DAG: v_mul_hi_u32 [[FOURTH_RCP_HI:v[0-9]+]], [[FOURTH_RCP]] 331; SI-DAG: v_mul_lo_i32 [[FOURTH_RCP_LO:v[0-9]+]], [[FOURTH_RCP]] 332; SI-DAG: v_sub_i32_e32 [[FOURTH_NEG_RCP_LO:v[0-9]+]], 0, [[FOURTH_RCP_LO]] 333; SI-DAG: v_cndmask_b32_e64 334; SI-DAG: v_mul_hi_u32 [[FOURTH_E:v[0-9]+]], {{v[0-9]+}}, [[FOURTH_RCP]] 335; SI-DAG: v_add_i32_e32 [[FOURTH_RCP_A_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]] 336; SI-DAG: v_subrev_i32_e32 [[FOURTH_RCP_S_E:v[0-9]+]], [[FOURTH_E]], [[FOURTH_RCP]] 337; SI-DAG: v_cndmask_b32_e64 338; SI: s_endpgm 339define void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) { 340 %result0 = udiv <4 x i32> %x, %y 341 store <4 x i32> %result0, <4 x i32> addrspace(1)* %out 342 %result1 = urem <4 x i32> %x, %y 343 store <4 x i32> %result1, <4 x i32> addrspace(1)* %out 344 ret void 345} 346