1; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s 2; 3; Verify that the DAGCombiner is able to fold a vector AND into a blend 4; if one of the operands to the AND is a vector of all constants, and each 5; constant element is either zero or all-ones. 6 7 8define <4 x i32> @test1(<4 x i32> %A) { 9; CHECK-LABEL: test1: 10; CHECK: # BB#0: 11; CHECK-NEXT: pxor %xmm1, %xmm1 12; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7] 13; CHECK-NEXT: retq 14 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 0> 15 ret <4 x i32> %1 16} 17 18define <4 x i32> @test2(<4 x i32> %A) { 19; CHECK-LABEL: test2: 20; CHECK: # BB#0: 21; CHECK-NEXT: pxor %xmm1, %xmm1 22; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7] 23; CHECK-NEXT: retq 24 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 0> 25 ret <4 x i32> %1 26} 27 28define <4 x i32> @test3(<4 x i32> %A) { 29; CHECK-LABEL: test3: 30; CHECK: # BB#0: 31; CHECK-NEXT: pxor %xmm1, %xmm1 32; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7] 33; CHECK-NEXT: retq 34 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 0> 35 ret <4 x i32> %1 36} 37 38define <4 x i32> @test4(<4 x i32> %A) { 39; CHECK-LABEL: test4: 40; CHECK: # BB#0: 41; CHECK-NEXT: pxor %xmm1, %xmm1 42; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7] 43; CHECK-NEXT: retq 44 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 0, i32 -1> 45 ret <4 x i32> %1 46} 47 48define <4 x i32> @test5(<4 x i32> %A) { 49; CHECK-LABEL: test5: 50; CHECK: # BB#0: 51; CHECK-NEXT: pxor %xmm1, %xmm1 52; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 53; CHECK-NEXT: retq 54 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0> 55 ret <4 x i32> %1 56} 57 58define <4 x i32> @test6(<4 x i32> %A) { 59; CHECK-LABEL: test6: 60; CHECK: # BB#0: 61; CHECK-NEXT: pxor %xmm1, %xmm1 62; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7] 63; CHECK-NEXT: retq 64 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1> 65 ret <4 x i32> %1 66} 67 68define <4 x i32> @test7(<4 x i32> %A) { 69; CHECK-LABEL: test7: 70; CHECK: # BB#0: 71; CHECK-NEXT: pxor %xmm1, %xmm1 72; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] 73; CHECK-NEXT: retq 74 %1 = and <4 x i32> %A, <i32 0, i32 0, i32 -1, i32 -1> 75 ret <4 x i32> %1 76} 77 78define <4 x i32> @test8(<4 x i32> %A) { 79; CHECK-LABEL: test8: 80; CHECK: # BB#0: 81; CHECK-NEXT: pxor %xmm1, %xmm1 82; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7] 83; CHECK-NEXT: retq 84 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 0, i32 -1> 85 ret <4 x i32> %1 86} 87 88define <4 x i32> @test9(<4 x i32> %A) { 89; CHECK-LABEL: test9: 90; CHECK: # BB#0: 91; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero 92; CHECK-NEXT: retq 93 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 0> 94 ret <4 x i32> %1 95} 96 97define <4 x i32> @test10(<4 x i32> %A) { 98; CHECK-LABEL: test10: 99; CHECK: # BB#0: 100; CHECK-NEXT: pxor %xmm1, %xmm1 101; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7] 102; CHECK-NEXT: retq 103 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 0> 104 ret <4 x i32> %1 105} 106 107define <4 x i32> @test11(<4 x i32> %A) { 108; CHECK-LABEL: test11: 109; CHECK: # BB#0: 110; CHECK-NEXT: pxor %xmm1, %xmm1 111; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7] 112; CHECK-NEXT: retq 113 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 -1, i32 -1> 114 ret <4 x i32> %1 115} 116 117define <4 x i32> @test12(<4 x i32> %A) { 118; CHECK-LABEL: test12: 119; CHECK: # BB#0: 120; CHECK-NEXT: pxor %xmm1, %xmm1 121; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7] 122; CHECK-NEXT: retq 123 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 0> 124 ret <4 x i32> %1 125} 126 127define <4 x i32> @test13(<4 x i32> %A) { 128; CHECK-LABEL: test13: 129; CHECK: # BB#0: 130; CHECK-NEXT: pxor %xmm1, %xmm1 131; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7] 132; CHECK-NEXT: retq 133 %1 = and <4 x i32> %A, <i32 -1, i32 -1, i32 0, i32 -1> 134 ret <4 x i32> %1 135} 136 137define <4 x i32> @test14(<4 x i32> %A) { 138; CHECK-LABEL: test14: 139; CHECK: # BB#0: 140; CHECK-NEXT: pxor %xmm1, %xmm1 141; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7] 142; CHECK-NEXT: retq 143 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1> 144 ret <4 x i32> %1 145} 146 147define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) { 148; CHECK-LABEL: test15: 149; CHECK: # BB#0: 150; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7] 151; CHECK-NEXT: retq 152 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 -1> 153 %2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 0> 154 %3 = or <4 x i32> %1, %2 155 ret <4 x i32> %3 156} 157 158define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) { 159; CHECK-LABEL: test16: 160; CHECK: # BB#0: 161; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] 162; CHECK-NEXT: retq 163 %1 = and <4 x i32> %A, <i32 -1, i32 0, i32 -1, i32 0> 164 %2 = and <4 x i32> %B, <i32 0, i32 -1, i32 0, i32 -1> 165 %3 = or <4 x i32> %1, %2 166 ret <4 x i32> %3 167} 168 169define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) { 170; CHECK-LABEL: test17: 171; CHECK: # BB#0: 172; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7] 173; CHECK-NEXT: retq 174 %1 = and <4 x i32> %A, <i32 0, i32 -1, i32 0, i32 -1> 175 %2 = and <4 x i32> %B, <i32 -1, i32 0, i32 -1, i32 0> 176 %3 = or <4 x i32> %1, %2 177 ret <4 x i32> %3 178} 179