1# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s 2 3# This file is checking Thumbv7 encodings which are globally invalid, usually due 4# to the constraints of the instructions not being met. For example invalid 5# combinations of registers. 6 7#------------------------------------------------------------------------------ 8# Undefined encoding for b.cc 9#------------------------------------------------------------------------------ 10 11# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) 12# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 13# ------------------------------------------------------------------------------------------------- 14# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| 15# ------------------------------------------------------------------------------------------------- 16# 17# A8.6.16 B 18# if cond<3:1> == '111' then SEE "Related Encodings" 19 20[0xaf 0xf7 0x44 0x8b] 21# CHECK: warning: invalid instruction encoding 22# CHECK-NEXT: [0xaf 0xf7 0x44 0x8b] 23 24#------------------------------------------------------------------------------ 25# Undefined encoding for it 26#------------------------------------------------------------------------------ 27 28[0xff 0xbf 0x6b 0x80 0x00 0x75] 29# CHECK: potentially undefined instruction encoding 30# CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75] 31 32[0x50 0xbf] # hint #5; legal as the third instruction for the iteee above 33 34# Two warnings from this block since there are two instructions in there 35[0xdb 0xbf 0x42 0xbb] 36# CHECK: potentially undefined instruction encoding 37# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb] 38# CHECK: potentially undefined instruction encoding 39# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb] 40 41#------------------------------------------------------------------------------ 42# Undefined encoding for ldm 43#------------------------------------------------------------------------------ 44 45# Writeback is not allowed is Rn is in the target register list. 46[0xb4 0xe8 0x34 0x04] 47# CHECK: potentially undefined instruction encoding 48# CHECK-NEXT: [0xb4 0xe8 0x34 0x04] 49 50 51#------------------------------------------------------------------------------ 52# Undefined encoding for ldrd 53#------------------------------------------------------------------------------ 54 55# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) 56# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 57# ------------------------------------------------------------------------------------------------- 58# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 59# ------------------------------------------------------------------------------------------------- 60# 61# A8.6.66 LDRD (immediate) 62# if Rn = '1111' then SEE LDRD (literal) 63# A8.6.67 LDRD (literal) 64# Inst{21} = 0 65 66[0xff 0xe9 0x0 0xeb] 67# CHECK: potentially undefined 68# CHECK-NEXT: [0xff 0xe9 0x0 0xeb] 69 70 71#------------------------------------------------------------------------------ 72# Undefined encodings for ldrbt 73#------------------------------------------------------------------------------ 74 75# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) 76# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 77# ------------------------------------------------------------------------------------------------- 78# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 79# ------------------------------------------------------------------------------------------------- 80# 81# The unpriviledged Load/Store cannot have SP or PC as Rt. 82[0x10 0xf8 0x3 0xfe] 83# CHECK: potentially undefined instruction encoding 84# CHECK-NEXT: [0x10 0xf8 0x3 0xfe] 85 86 87#------------------------------------------------------------------------------ 88# Undefined encodings for ldrsh 89#------------------------------------------------------------------------------ 90 91# invalid LDRSHs Rt=PC 92[0x30 0xf9 0x00 0xf0] 93# CHECK: invalid instruction encoding 94# CHECK-NEXT: [0x30 0xf9 0x00 0xf0] 95 96# invalid LDRSHi8 Rt=PC 97[0x30 0xf9 0x00 0xfc] 98# CHECK: invalid instruction encoding 99# CHECK-NEXT: [0x30 0xf9 0x00 0xfc] 100 101# invalid LDRSHi12 Rt=PC 102[0xb0 0xf9 0x00 0xf0] 103# CHECK: invalid instruction encoding 104# CHECK-NEXT: [0xb0 0xf9 0x00 0xf0] 105 106# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) 107# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 108# ------------------------------------------------------------------------------------------------- 109# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 110# ------------------------------------------------------------------------------------------------- 111# 112# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints" 113[0x35 0xf9 0x00 0xfc] 114# CHECK: invalid instruction encoding 115# CHECK-NEXT: [0x35 0xf9 0x00 0xfc] 116 117# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) 118# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 119# ------------------------------------------------------------------------------------------------- 120# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1| 121# ------------------------------------------------------------------------------------------------- 122# 123# if Rt = '1111' then SEE "Unallocated memory hints" 124[0xb3 0xf9 0xdf 0xf8] 125# CHECK: invalid instruction encoding 126# CHECK-NEXT: [0xb3 0xf9 0xdf 0xf8] 127 128 129#------------------------------------------------------------------------------ 130# Undefined encoding for push 131#------------------------------------------------------------------------------ 132 133# SP and PC are not allowed in the register list on STM instructions in Thumb2. 134[0x2d 0xe9 0xf7 0xb6] 135# CHECK: invalid instruction encoding 136# CHECK-NEXT: [0x2d 0xe9 0xf7 0xb6] 137 138 139#------------------------------------------------------------------------------ 140# Undefined encoding for stmia 141#------------------------------------------------------------------------------ 142 143# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) 144# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 145# ------------------------------------------------------------------------------------------------- 146# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 147# ------------------------------------------------------------------------------------------------- 148# 149# if BitCount(registers) < 1 then UNPREDICTABLE 150[0x00 0xc7] 151# CHECK: invalid instruction encoding 152# CHECK-NEXT: [0x00 0xc7] 153 154 155#------------------------------------------------------------------------------ 156# Undefined encodings for str 157#------------------------------------------------------------------------------ 158 159# invalid STRi12 Rn=PC 160[0xcf 0xf8 0x00 0x00] 161# CHECK: invalid instruction encoding 162# CHECK-NEXT: [0xcf 0xf8 0x00 0x00] 163 164# invalid STRi8 Rn=PC 165[0x4f 0xf8 0x00 0x0c] 166# CHECK: invalid instruction encoding 167# CHECK-NEXT: [0x4f 0xf8 0x00 0x0c] 168 169# invalid STRs Rn=PC 170[0x4f 0xf8 0x00 0x00] 171# CHECK: invalid instruction encoding 172# CHECK-NEXT: [0x4f 0xf8 0x00 0x00] 173 174# invalid STRBi12 Rn=PC 175[0x0f 0xf8 0x00 0x00] 176# CHECK: invalid instruction encoding 177# CHECK-NEXT: [0x0f 0xf8 0x00 0x00] 178 179# invalid STRBi8 Rn=PC 180[0x0f 0xf8 0x00 0x0c] 181# CHECK: invalid instruction encoding 182# CHECK-NEXT: [0x0f 0xf8 0x00 0x0c] 183 184# invalid STRBs Rn=PC 185[0x0f 0xf8 0x00 0x00] 186# CHECK: invalid instruction encoding 187# CHECK-NEXT: [0x0f 0xf8 0x00 0x00] 188 189# invalid STRHi12 Rn=PC 190[0xaf 0xf8 0x00 0x00] 191# CHECK: invalid instruction encoding 192# CHECK-NEXT: [0xaf 0xf8 0x00 0x00] 193 194# invalid STRHi8 Rn=PC 195[0x2f 0xf8 0x00 0x0c] 196# CHECK: invalid instruction encoding 197# CHECK-NEXT: [0x2f 0xf8 0x00 0x0c] 198 199# invalid STRHs Rn=PC 200[0x2f 0xf8 0x00 0x00] 201# CHECK: invalid instruction encoding 202# CHECK-NEXT: [0x2f 0xf8 0x00 0x00] 203 204# invalid STRBT Rn=PC 205[0x0f 0xf8 0x00 0x0e] 206# CHECK: invalid instruction encoding 207# CHECK-NEXT: [0x0f 0xf8 0x00 0x0e] 208 209# invalid STRHT Rn=PC 210[0x2f 0xf8 0x00 0x0e] 211# CHECK: invalid instruction encoding 212# CHECK-NEXT: [0x2f 0xf8 0x00 0x0e] 213 214# invalid STRT Rn=PC 215[0x4f 0xf8 0x00 0x0e] 216# CHECK: invalid instruction encoding 217# CHECK-NEXT: [0x4f 0xf8 0x00 0x0e] 218 219# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) 220# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 221# ------------------------------------------------------------------------------------------------- 222# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 223# ------------------------------------------------------------------------------------------------- 224# 225# if Rn == '1111' then UNDEFINED 226 227[0x4f 0xf8 0xff 0xeb] 228# CHECK: invalid instruction encoding 229# CHECK-NEXT: [0x4f 0xf8 0xff 0xeb] 230 231#------------------------------------------------------------------------------ 232# Undefined encodings for strd 233#------------------------------------------------------------------------------ 234 235# Rt == Rn is UNPREDICTABLE 236[0xe4 0xe9 0x02 0x46] 237# CHECK: warning: potentially undefined instruction encoding 238# CHECK-NEXT: [0xe4 0xe9 0x02 0x46] 239 240#------------------------------------------------------------------------------ 241# Undefined encodings for NEON vld instructions 242#------------------------------------------------------------------------------ 243 244# size = '00' and index_align == '0001' so UNDEFINED 245[0xa0 0xf9 0x10 0x08] 246# CHECK: invalid instruction encoding 247# CHECK-NEXT: [0xa0 0xf9 0x10 0x08] 248 249 250# vld3 251 252# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) 253# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 254# ------------------------------------------------------------------------------------------------- 255# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0| 256# ------------------------------------------------------------------------------------------------- 257# 258# A8.6.315 VLD3 (single 3-element structure to all lanes) 259# The a bit must be encoded as 0. 260 261[0xa2 0xf9 0x92 0x2e] 262# CHECK: invalid instruction encoding 263# CHECK-NEXT: [0xa2 0xf9 0x92 0x2e] 264 265 266# Some vld4 ones 267# size == '11' and a == '0' so UNDEFINED 268[0xa0 0xf9 0xc0 0x0f] 269# CHECK: invalid instruction encoding 270# CHECK-NEXT: [0xa0 0xf9 0xc0 0x0f] 271 272[0xa0 0xf9 0x30 0x0b] 273# CHECK: invalid instruction encoding 274# CHECK-NEXT: [0xa0 0xf9 0x30 0x0b] 275 276 277# VLD1 multi-element, type=0b1010 align=0b11 278[0x24 0xf9 0xbf 0x8a] 279# CHECK: invalid instruction encoding 280# CHECK-NEXT: [0x24 0xf9 0xbf 0x8a] 281 282# VLD1 multi-element type=0b0111 align=0b1x 283[0x24 0xf9 0xbf 0x87] 284# CHECK: invalid instruction encoding 285# CHECK-NEXT: [0x24 0xf9 0xbf 0x87] 286 287# VLD1 multi-element type=0b0010 align=0b1x 288[0x24 0xf9 0xbf 0x86] 289# CHECK: invalid instruction encoding 290# CHECK-NEXT: [0x24 0xf9 0xbf 0x86] 291 292# VLD2 multi-element size=0b11 293[0x60 0xf9 0xcf 0x08] 294# CHECK: invalid instruction encoding 295# CHECK-NEXT: [0x60 0xf9 0xcf 0x08] 296 297# VLD2 multi-element type=0b1111 align=0b11 298[0x60 0xf9 0xbf 0x08] 299# CHECK: invalid instruction encoding 300# CHECK-NEXT: [0x60 0xf9 0xbf 0x08] 301 302# VLD2 multi-element type=0b1001 align=0b11 303[0x60 0xf9 0xbf 0x09] 304# CHECK: invalid instruction encoding 305# CHECK-NEXT: [0x60 0xf9 0xbf 0x09] 306 307# VLD3 multi-element size=0b11 308[0x60 0xf9 0x7f 0x04] 309# CHECK: invalid instruction encoding 310# CHECK-NEXT: [0x60 0xf9 0x7f 0x04] 311 312# VLD3 multi-element align=0b1x 313[0x60 0xf9 0xcf 0x04] 314# CHECK: invalid instruction encoding 315# CHECK-NEXT: [0x60 0xf9 0xcf 0x04] 316 317# VLD4 multi-element size=0b11 318[0x60 0xf9 0xcd 0x11] 319# CHECK: invalid instruction encoding 320# CHECK-NEXT: [0x60 0xf9 0xcd 0x11] 321 322 323#------------------------------------------------------------------------------ 324# Undefined encodings for NEON vst1 325#------------------------------------------------------------------------------ 326 327# size == '10' and index_align == '0001' so UNDEFINED 328[0x80 0xf9 0x10 0x08] 329# CHECK: invalid instruction encoding 330# CHECK-NEXT: [0x80 0xf9 0x10 0x08] 331 332# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) 333# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 334# ------------------------------------------------------------------------------------------------- 335# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| 336# ------------------------------------------------------------------------------------------------- 337# 338# A8.6.391 VST1 (multiple single elements) 339# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128] 340# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> 341# contains two or four registers. rdar://11220250 342[0x00 0xf9 0x2f 0x06] 343# CHECK: invalid instruction encoding 344# CHECK-NEXT: [0x00 0xf9 0x2f 0x06] 345 346#------------------------------------------------------------------------------ 347# Undefined encodings for NEON vst4 348#------------------------------------------------------------------------------ 349 350[0x80 0xf9 0x30 0x0b] 351# CHECK: invalid instruction encoding 352# CHECK-NEXT: [0x80 0xf9 0x30 0x0b] 353 354 355#------------------------------------------------------------------------------ 356# Unpredictable STMs 357#------------------------------------------------------------------------------ 358 359# 32-bit Thumb STM instructions cannot have a writeback register which appears 360# in the list. 361 362[0xa1,0xe8,0x07,0x04] 363# CHECK: warning: potentially undefined instruction encoding 364# CHECK-NEXT: [0xa1,0xe8,0x07,0x04] 365 366[0x21,0xe9,0x07,0x04] 367# CHECK: warning: potentially undefined instruction encoding 368# CHECK-NEXT: [0x21,0xe9,0x07,0x04] 369