1
2 /* To compile:
3 aarch64-linux-gnu-gcc -Wall -g -O0 -o memory none/tests/arm64/memory.c
4 */
5
6 #include <stdio.h>
7 #include <malloc.h> // memalign
8 #include <string.h> // memset
9 #include <assert.h>
10
11 typedef unsigned char UChar;
12 typedef unsigned short int UShort;
13 typedef unsigned int UInt;
14 typedef signed int Int;
15 typedef unsigned char UChar;
16 typedef signed long long int Long;
17 typedef unsigned long long int ULong;
18
19 typedef unsigned char Bool;
20 #define False ((Bool)0)
21 #define True ((Bool)1)
22
23 __attribute__((noinline))
memalign16(size_t szB)24 static void* memalign16(size_t szB)
25 {
26 void* x;
27 x = memalign(16, szB);
28 assert(x);
29 assert(0 == ((16-1) & (unsigned long)x));
30 return x;
31 }
32
randUChar(void)33 static inline UChar randUChar ( void )
34 {
35 static UInt seed = 80021;
36 seed = 1103515245 * seed + 12345;
37 return (seed >> 17) & 0xFF;
38 }
39
randULong(void)40 static ULong randULong ( void )
41 {
42 Int i;
43 ULong r = 0;
44 for (i = 0; i < 8; i++) {
45 r = (r << 8) | (ULong)(0xFF & randUChar());
46 }
47 return r;
48 }
49
50
51 // Same as TESTINST2 except it doesn't print the RN value, since
52 // that may differ between runs (it's a stack address). Also,
53 // claim it trashes x28 so that can be used as scratch if needed.
54 #define TESTINST2_hide2(instruction, RNval, RD, RN, carryin) \
55 { \
56 ULong out; \
57 ULong nzcv_out; \
58 ULong nzcv_in = (carryin ? (1<<29) : 0); \
59 __asm__ __volatile__( \
60 "msr nzcv,%3;" \
61 "mov " #RN ",%2;" \
62 instruction ";" \
63 "mov %0," #RD ";" \
64 "mrs %1,nzcv;" \
65 : "=&r" (out), "=&r" (nzcv_out) \
66 : "r" (RNval), "r" (nzcv_in) \
67 : #RD, #RN, "cc", "memory", "x28" \
68 ); \
69 printf("%s :: rd %016llx rn (hidden), " \
70 "cin %d, nzcv %08llx %c%c%c%c\n", \
71 instruction, out, \
72 carryin ? 1 : 0, \
73 nzcv_out & 0xffff0000, \
74 ((1<<31) & nzcv_out) ? 'N' : ' ', \
75 ((1<<30) & nzcv_out) ? 'Z' : ' ', \
76 ((1<<29) & nzcv_out) ? 'C' : ' ', \
77 ((1<<28) & nzcv_out) ? 'V' : ' ' \
78 ); \
79 }
80
81 #define TESTINST3_hide2and3(instruction, RMval, RNval, RD, RM, RN, carryin) \
82 { \
83 ULong out; \
84 ULong nzcv_out; \
85 ULong nzcv_in = (carryin ? (1<<29) : 0); \
86 __asm__ __volatile__( \
87 "msr nzcv,%4;" \
88 "mov " #RM ",%2;" \
89 "mov " #RN ",%3;" \
90 instruction ";" \
91 "mov %0," #RD ";" \
92 "mrs %1,nzcv;" \
93 : "=&r" (out), "=&r" (nzcv_out) \
94 : "r" (RMval), "r" (RNval), "r" (nzcv_in) \
95 : #RD, #RM, #RN, "cc", "memory" \
96 ); \
97 printf("%s :: rd %016llx rm (hidden), rn (hidden), " \
98 "cin %d, nzcv %08llx %c%c%c%c\n", \
99 instruction, out, \
100 carryin ? 1 : 0, \
101 nzcv_out & 0xffff0000, \
102 ((1<<31) & nzcv_out) ? 'N' : ' ', \
103 ((1<<30) & nzcv_out) ? 'Z' : ' ', \
104 ((1<<29) & nzcv_out) ? 'C' : ' ', \
105 ((1<<28) & nzcv_out) ? 'V' : ' ' \
106 ); \
107 }
108
109
110 ////////////////////////////////////////////////////////////////
111 ////////////////////////////////////////////////////////////////
112 ////////////////////////////////////////////////////////////////
113 // //
114 // test_memory_old //
115 // //
116 ////////////////////////////////////////////////////////////////
117 ////////////////////////////////////////////////////////////////
118 ////////////////////////////////////////////////////////////////
119
test_memory_old(void)120 static __attribute((noinline)) void test_memory_old ( void )
121 {
122 printf("Integer loads\n");
123
124 unsigned char area[512];
125
126 #define RESET \
127 do { int i; for (i = 0; i < sizeof(area); i++) \
128 area[i] = i | 0x80; \
129 } while (0)
130
131 #define AREA_MID (((ULong)(&area[(sizeof(area)/2)-1])) & (~(ULong)0xF))
132
133 RESET;
134
135 ////////////////////////////////////////////////////////////////
136 printf("LDR,STR (immediate, uimm12) (STR cases are MISSING)");
137 TESTINST2_hide2("ldr x21, [x22, #24]", AREA_MID, x21,x22,0);
138 TESTINST2_hide2("ldr w21, [x22, #20]", AREA_MID, x21,x22,0);
139 TESTINST2_hide2("ldrh w21, [x22, #44]", AREA_MID, x21,x22,0);
140 TESTINST2_hide2("ldrb w21, [x22, #56]", AREA_MID, x21,x22,0);
141
142 ////////////////////////////////////////////////////////////////
143 printf("LDUR,STUR (immediate, simm9) (STR cases and wb check are MISSING)\n");
144 TESTINST2_hide2("ldr x21, [x22], #-24", AREA_MID, x21,x22,0);
145 TESTINST2_hide2("ldr x21, [x22, #-40]!", AREA_MID, x21,x22,0);
146 TESTINST2_hide2("ldr x21, [x22, #-48]", AREA_MID, x21,x22,0);
147 printf("LDUR,STUR (immediate, simm9): STR cases are MISSING");
148
149 ////////////////////////////////////////////////////////////////
150 // TESTINST2_hide2 allows use of x28 as scratch
151 printf("LDP,STP (immediate, simm7) (STR cases and wb check is MISSING)\n");
152
153 TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
154 TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
155 TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
156 TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
157 TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
158 TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
159
160 TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
161 TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
162 TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
163 TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
164 TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
165 TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
166
167 ////////////////////////////////////////////////////////////////
168 // This is a bit tricky. We load the value from just before and
169 // just after the actual instruction. Because TESTINSN2_hide2
170 // generates two fixed insns either side of the test insn, these
171 // should be constant and hence "safe" to check.
172
173 printf("LDR (literal, int reg)\n");
174 TESTINST2_hide2("xyzzy00: ldr x21, xyzzy00 - 8", AREA_MID, x21,x22,0);
175 TESTINST2_hide2("xyzzy01: ldr x21, xyzzy01 + 0", AREA_MID, x21,x22,0);
176 TESTINST2_hide2("xyzzy02: ldr x21, xyzzy02 + 8", AREA_MID, x21,x22,0);
177
178 TESTINST2_hide2("xyzzy03: ldr x21, xyzzy03 - 4", AREA_MID, x21,x22,0);
179 TESTINST2_hide2("xyzzy04: ldr x21, xyzzy04 + 0", AREA_MID, x21,x22,0);
180 TESTINST2_hide2("xyzzy05: ldr x21, xyzzy05 + 4", AREA_MID, x21,x22,0);
181
182 ////////////////////////////////////////////////////////////////
183 printf("{LD,ST}R (integer register) (entirely MISSING)\n");
184
185 ////////////////////////////////////////////////////////////////
186 printf("LDRS{B,H,W} (uimm12)\n");
187 TESTINST2_hide2("ldrsw x21, [x22, #24]", AREA_MID, x21,x22,0);
188 TESTINST2_hide2("ldrsh x21, [x22, #20]", AREA_MID, x21,x22,0);
189 TESTINST2_hide2("ldrsh w21, [x22, #44]", AREA_MID, x21,x22,0);
190 TESTINST2_hide2("ldrsb x21, [x22, #88]", AREA_MID, x21,x22,0);
191 TESTINST2_hide2("ldrsb w21, [x22, #56]", AREA_MID, x21,x22,0);
192
193 ////////////////////////////////////////////////////////////////
194 printf("LDRS{B,H,W} (simm9, upd) (upd check is MISSING)\n");
195 TESTINST2_hide2("ldrsw x21, [x22, #-24]!", AREA_MID, x21,x22,0);
196 TESTINST2_hide2("ldrsh x21, [x22, #-20]!", AREA_MID, x21,x22,0);
197 TESTINST2_hide2("ldrsh w21, [x22, #-44]!", AREA_MID, x21,x22,0);
198 TESTINST2_hide2("ldrsb x21, [x22, #-88]!", AREA_MID, x21,x22,0);
199 TESTINST2_hide2("ldrsb w21, [x22, #-56]!", AREA_MID, x21,x22,0);
200
201 TESTINST2_hide2("ldrsw x21, [x22], #-24", AREA_MID, x21,x22,0);
202 TESTINST2_hide2("ldrsh x21, [x22], #-20", AREA_MID, x21,x22,0);
203 TESTINST2_hide2("ldrsh w21, [x22], #-44", AREA_MID, x21,x22,0);
204 TESTINST2_hide2("ldrsb x21, [x22], #-88", AREA_MID, x21,x22,0);
205 TESTINST2_hide2("ldrsb w21, [x22], #-56", AREA_MID, x21,x22,0);
206
207 ////////////////////////////////////////////////////////////////
208 printf("LDRS{B,H,W} (simm9, noUpd)\n");
209 TESTINST2_hide2("ldrsw x21, [x22, #-24]", AREA_MID, x21,x22,0);
210 TESTINST2_hide2("ldrsh x21, [x22, #-20]", AREA_MID, x21,x22,0);
211 TESTINST2_hide2("ldrsh w21, [x22, #-44]", AREA_MID, x21,x22,0);
212 TESTINST2_hide2("ldrsb x21, [x22, #-88]", AREA_MID, x21,x22,0);
213 TESTINST2_hide2("ldrsb w21, [x22, #-56]", AREA_MID, x21,x22,0);
214
215 ////////////////////////////////////////////////////////////////
216 printf("LDP,STP (immediate, simm7) (FP&VEC) (entirely MISSING)\n");
217
218 ////////////////////////////////////////////////////////////////
219 printf("{LD,ST}R (vector register) (entirely MISSING)\n");
220
221 ////////////////////////////////////////////////////////////////
222 printf("LDRS{B,H,W} (integer register, SX)\n");
223
224 TESTINST3_hide2and3("ldrsw x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
225 TESTINST3_hide2and3("ldrsw x21, [x22,x23, lsl #2]", AREA_MID, 5, x21,x22,x23,0);
226 TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
227 TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #2]", AREA_MID, 5, x21,x22,x23,0);
228 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
229 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #2]", AREA_MID, -5ULL, x21,x22,x23,0);
230
231 TESTINST3_hide2and3("ldrsh x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
232 TESTINST3_hide2and3("ldrsh x21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0);
233 TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
234 TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0);
235 TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
236 TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
237
238 TESTINST3_hide2and3("ldrsh w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
239 TESTINST3_hide2and3("ldrsh w21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0);
240 TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
241 TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0);
242 TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
243 TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
244
245 TESTINST3_hide2and3("ldrsb x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
246 TESTINST3_hide2and3("ldrsb x21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0);
247 TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
248 TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
249 TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
250 TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
251
252 TESTINST3_hide2and3("ldrsb w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
253 TESTINST3_hide2and3("ldrsb w21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0);
254 TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
255 TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
256 TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
257 TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
258
259 ////////////////////////////////////////////////////////////////
260 printf("LDR/STR (immediate, SIMD&FP, unsigned offset) (entirely MISSING)\n");
261
262 ////////////////////////////////////////////////////////////////
263 printf("LDR/STR (immediate, SIMD&FP, pre/post index) (entirely MISSING)\n");
264
265 ////////////////////////////////////////////////////////////////
266 printf("LDUR/STUR (unscaled offset, SIMD&FP) (entirely MISSING)\n");
267
268 ////////////////////////////////////////////////////////////////
269 printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
270
271 ////////////////////////////////////////////////////////////////
272 printf("LD1/ST1 (single structure, no offset) (entirely MISSING)\n");
273
274 ////////////////////////////////////////////////////////////////
275 printf("LD1/ST1 (single structure, post index) (entirely MISSING)\n");
276
277 ////////////////////////////////////////////////////////////////
278 printf("LD{,A}X{R,RH,RB} (entirely MISSING)\n");
279
280 ////////////////////////////////////////////////////////////////
281 printf("ST{,L}X{R,RH,RB} (entirely MISSING)\n");
282
283 ////////////////////////////////////////////////////////////////
284 printf("LDA{R,RH,RB}\n");
285 TESTINST2_hide2("ldar x21, [x22]", AREA_MID, x21,x22,0);
286 TESTINST2_hide2("ldar w21, [x22]", AREA_MID, x21,x22,0);
287 TESTINST2_hide2("ldarh w21, [x22]", AREA_MID, x21,x22,0);
288 TESTINST2_hide2("ldarb w21, [x22]", AREA_MID, x21,x22,0);
289
290 ////////////////////////////////////////////////////////////////
291 printf("STL{R,RH,RB} (entirely MISSING)\n");
292 } /* end of test_memory_old() */
293
294
295 ////////////////////////////////////////////////////////////////
296 ////////////////////////////////////////////////////////////////
297 ////////////////////////////////////////////////////////////////
298 // //
299 // test_memory_new //
300 // //
301 ////////////////////////////////////////////////////////////////
302 ////////////////////////////////////////////////////////////////
303 ////////////////////////////////////////////////////////////////
304
show_block_xor(UChar * block1,UChar * block2,Int n)305 static void show_block_xor ( UChar* block1, UChar* block2, Int n )
306 {
307 Int i;
308 printf(" ");
309 for (i = 0; i < n; i++) {
310 if (i > 0 && 0 == (i & 15)) printf("\n ");
311 if (0 == (i & 15)) printf("[%3d] ", i);
312 UInt diff = 0xFF & (UInt)(block1[i] - block2[i]);
313 if (diff == 0)
314 printf(".. ");
315 else
316 printf("%02x ", diff);
317 }
318 printf("\n");
319 }
320
321
322 // In: rand:
323 // memory area, xferred vec regs, xferred int regs,
324 // caller spec:
325 // addr reg1, addr reg2
326 //
327 // Out: memory area, xferred vec regs, xferred int regs, addr reg1, addr reg2
328 //
329 // INSN may mention the following regs as containing load/store data:
330 // x13 x23 v17 v18 v19 v20
331 // and
332 // x5 as containing the base address
333 // x6 as containing an offset, if required
334 // A memory area is filled with random data, and x13, x23, v17, v18, v19, v20
335 // are loaded with random data too. INSN is then executed, with
336 // x5 set to the middle of the memory area + AREG1OFF, and x6 set to AREG2VAL.
337 //
338 // What is printed out: the XOR of the new and old versions of the
339 // following:
340 // the memory area
341 // x13 x23 v17 v18 v19 v20
342 // and the SUB of the new and old values of the following:
343 // x5 x6
344 // If the insn modifies its base register then (obviously) the x5 "new - old"
345 // value will be nonzero.
346
347 #define MEM_TEST(INSN, AREG1OFF, AREG2VAL) { \
348 int i; \
349 const int N = 256; \
350 UChar* area = memalign16(N); \
351 UChar area2[N]; \
352 for (i = 0; i < N; i++) area[i] = area2[i] = randUChar(); \
353 ULong block[12]; \
354 /* 0:x13 1:x23 2:v17.d[0] 3:v17.d[1] 4:v18.d[0] 5:v18.d[1] */ \
355 /* 6:v19.d[0] 7:v19.d[1] 8:v20.d[0] 9:v20.d[1] 10:x5 11:x6 */ \
356 for (i = 0; i < 12; i++) block[i] = randULong(); \
357 block[10] = (ULong)(&area[128]) + (Long)(Int)AREG1OFF; \
358 block[11] = (Long)AREG2VAL; \
359 ULong block2[12]; \
360 for (i = 0; i < 12; i++) block2[i] = block[i]; \
361 __asm__ __volatile__( \
362 "ldr x13, [%0, #0] ; " \
363 "ldr x23, [%0, #8] ; " \
364 "ldr q17, [%0, #16] ; " \
365 "ldr q18, [%0, #32] ; " \
366 "ldr q19, [%0, #48] ; " \
367 "ldr q20, [%0, #64] ; " \
368 "ldr x5, [%0, #80] ; " \
369 "ldr x6, [%0, #88] ; " \
370 INSN " ; " \
371 "str x13, [%0, #0] ; " \
372 "str x23, [%0, #8] ; " \
373 "str q17, [%0, #16] ; " \
374 "str q18, [%0, #32] ; " \
375 "str q19, [%0, #48] ; " \
376 "str q20, [%0, #64] ; " \
377 "str x5, [%0, #80] ; " \
378 "str x6, [%0, #88] ; " \
379 : : "r"(&block[0]) : "x5", "x6", "x13", "x23", \
380 "v17", "v18", "v19", "v20", "memory", "cc" \
381 ); \
382 printf("%s with x5 = middle_of_block+%lld, x6=%lld\n", \
383 INSN, (Long)AREG1OFF, (Long)AREG2VAL); \
384 show_block_xor(&area2[0], area, 256); \
385 printf(" %016llx x13 (xor, xfer intreg #1)\n", block[0] ^ block2[0]); \
386 printf(" %016llx x23 (xor, xfer intreg #2)\n", block[1] ^ block2[1]); \
387 printf(" %016llx v17.d[0] (xor, xfer vecreg #1)\n", block[2] ^ block2[2]); \
388 printf(" %016llx v17.d[1] (xor, xfer vecreg #1)\n", block[3] ^ block2[3]); \
389 printf(" %016llx v18.d[0] (xor, xfer vecreg #2)\n", block[4] ^ block2[4]); \
390 printf(" %016llx v18.d[1] (xor, xfer vecreg #2)\n", block[5] ^ block2[5]); \
391 printf(" %016llx v19.d[0] (xor, xfer vecreg #3)\n", block[6] ^ block2[6]); \
392 printf(" %016llx v19.d[1] (xor, xfer vecreg #3)\n", block[7] ^ block2[7]); \
393 printf(" %016llx v20.d[0] (xor, xfer vecreg #3)\n", block[8] ^ block2[8]); \
394 printf(" %016llx v20.d[1] (xor, xfer vecreg #3)\n", block[9] ^ block2[9]); \
395 printf(" %16lld x5 (sub, base reg)\n", block[10] - block2[10]); \
396 printf(" %16lld x6 (sub, index reg)\n", block[11] - block2[11]); \
397 printf("\n"); \
398 free(area); \
399 }
400
401
test_memory_new(void)402 static __attribute__((noinline)) void test_memory_new ( void )
403 {
404 ////////////////////////////////////////////////////////////////
405 printf("LDR,STR (immediate, uimm12)");
406 MEM_TEST("ldr x13, [x5, #24]", -1, 0);
407 MEM_TEST("ldr w13, [x5, #20]", 1, 0);
408 MEM_TEST("ldrh w13, [x5, #44]", 2, 0);
409 MEM_TEST("ldrb w13, [x5, #56]", 3, 0);
410 MEM_TEST("str x13, [x5, #24]", -3, 0);
411 MEM_TEST("str w13, [x5, #20]", 5, 0);
412 MEM_TEST("strh w13, [x5, #44]", 6, 0);
413 MEM_TEST("strb w13, [x5, #56]", 7, 0);
414
415 ////////////////////////////////////////////////////////////////
416 printf("LDUR,STUR (immediate, simm9)\n");
417 MEM_TEST("ldr x13, [x5], #-24", 0, 0);
418 MEM_TEST("ldr x13, [x5, #-40]!", 0, 0);
419 MEM_TEST("ldr x13, [x5, #-48]", 0, 0);
420 MEM_TEST("str x13, [x5], #-24", 0, 0);
421 MEM_TEST("str x13, [x5, #-40]!", 0, 0);
422 MEM_TEST("str x13, [x5, #-48]", 0, 0);
423
424 ////////////////////////////////////////////////////////////////
425 printf("LDP,STP (immediate, simm7)\n");
426 MEM_TEST("ldp x13, x23, [x5], #-24", 0, 0);
427 MEM_TEST("ldp x13, x23, [x5, #-40]!", 0, 0);
428 MEM_TEST("ldp x13, x23, [x5, #-40]", 0, 0);
429 MEM_TEST("stp x13, x23, [x5], #-24", 0, 0);
430 MEM_TEST("stp x13, x23, [x5, #-40]!", 0, 0);
431 MEM_TEST("stp x13, x23, [x5, #-40]", 0, 0);
432
433 MEM_TEST("ldp w13, w23, [x5], #-24", 0, 0);
434 MEM_TEST("ldp w13, w23, [x5, #-40]!", 0, 0);
435 MEM_TEST("ldp w13, w23, [x5, #-40]", 0, 0);
436 MEM_TEST("stp w13, w23, [x5], #-24", 0, 0);
437 MEM_TEST("stp w13, w23, [x5, #-40]!", 0, 0);
438 MEM_TEST("stp w13, w23, [x5, #-40]", 0, 0);
439
440 ////////////////////////////////////////////////////////////////
441 printf("LDR (literal, int reg) (done above by test_memory_old)\n");
442
443 ////////////////////////////////////////////////////////////////
444 printf("{LD,ST}R (integer register)\n");
445 MEM_TEST("str x13, [x5, x6]", 12, -4);
446 MEM_TEST("str x13, [x5, x6, lsl #3]", 12, -4);
447 MEM_TEST("str x13, [x5, w6, uxtw]", 12, 4);
448 MEM_TEST("str x13, [x5, w6, uxtw #3]", 12, 4);
449 MEM_TEST("str x13, [x5, w6, sxtw]", 12, 4);
450 MEM_TEST("str x13, [x5, w6, sxtw #3]", 12, -4);
451 MEM_TEST("ldr x13, [x5, x6]", 12, -4);
452 MEM_TEST("ldr x13, [x5, x6, lsl #3]", 12, -4);
453 MEM_TEST("ldr x13, [x5, w6, uxtw]", 12, 4);
454 MEM_TEST("ldr x13, [x5, w6, uxtw #3]", 12, 4);
455 MEM_TEST("ldr x13, [x5, w6, sxtw]", 12, 4);
456 MEM_TEST("ldr x13, [x5, w6, sxtw #3]", 12, -4);
457
458 MEM_TEST("str w13, [x5, x6]", 12, -4);
459 MEM_TEST("str w13, [x5, x6, lsl #2]", 12, -4);
460 MEM_TEST("str w13, [x5, w6, uxtw]", 12, 4);
461 MEM_TEST("str w13, [x5, w6, uxtw #2]", 12, 4);
462 MEM_TEST("str w13, [x5, w6, sxtw]", 12, 4);
463 MEM_TEST("str w13, [x5, w6, sxtw #2]", 12, -4);
464 MEM_TEST("ldr w13, [x5, x6]", 12, -4);
465 MEM_TEST("ldr w13, [x5, x6, lsl #2]", 12, -4);
466 MEM_TEST("ldr w13, [x5, w6, uxtw]", 12, 4);
467 MEM_TEST("ldr w13, [x5, w6, uxtw #2]", 12, 4);
468 MEM_TEST("ldr w13, [x5, w6, sxtw]", 12, 4);
469 MEM_TEST("ldr w13, [x5, w6, sxtw #2]", 12, -4);
470
471 MEM_TEST("strh w13, [x5, x6]", 12, -4);
472 MEM_TEST("strh w13, [x5, x6, lsl #1]", 12, -4);
473 MEM_TEST("strh w13, [x5, w6, uxtw]", 12, 4);
474 MEM_TEST("strh w13, [x5, w6, uxtw #1]", 12, 4);
475 MEM_TEST("strh w13, [x5, w6, sxtw]", 12, 4);
476 MEM_TEST("strh w13, [x5, w6, sxtw #1]", 12, -4);
477 MEM_TEST("ldrh w13, [x5, x6]", 12, -4);
478 MEM_TEST("ldrh w13, [x5, x6, lsl #1]", 12, -4);
479 MEM_TEST("ldrh w13, [x5, w6, uxtw]", 12, 4);
480 MEM_TEST("ldrh w13, [x5, w6, uxtw #1]", 12, 4);
481 MEM_TEST("ldrh w13, [x5, w6, sxtw]", 12, 4);
482 MEM_TEST("ldrh w13, [x5, w6, sxtw #1]", 12, -4);
483
484 MEM_TEST("strb w13, [x5, x6]", 12, -4);
485 MEM_TEST("strb w13, [x5, x6, lsl #0]", 12, -4);
486 MEM_TEST("strb w13, [x5, w6, uxtw]", 12, 4);
487 MEM_TEST("strb w13, [x5, w6, uxtw #0]", 12, 4);
488 MEM_TEST("strb w13, [x5, w6, sxtw]", 12, 4);
489 MEM_TEST("strb w13, [x5, w6, sxtw #0]", 12, -4);
490 MEM_TEST("ldrb w13, [x5, x6]", 12, -4);
491 MEM_TEST("ldrb w13, [x5, x6, lsl #0]", 12, -4);
492 MEM_TEST("ldrb w13, [x5, w6, uxtw]", 12, 4);
493 MEM_TEST("ldrb w13, [x5, w6, uxtw #0]", 12, 4);
494 MEM_TEST("ldrb w13, [x5, w6, sxtw]", 12, 4);
495 MEM_TEST("ldrb w13, [x5, w6, sxtw #0]", 12, -4);
496
497 ////////////////////////////////////////////////////////////////
498 printf("LDRS{B,H,W} (uimm12)\n");
499 MEM_TEST("ldrsw x13, [x5, #24]", -16, 4);
500 MEM_TEST("ldrsh x13, [x5, #20]", -16, 4);
501 MEM_TEST("ldrsh w13, [x5, #44]", -16, 4);
502 MEM_TEST("ldrsb x13, [x5, #72]", -16, 4);
503 MEM_TEST("ldrsb w13, [x5, #56]", -16, 4);
504
505 ////////////////////////////////////////////////////////////////
506 printf("LDRS{B,H,W} (simm9, upd)\n");
507 MEM_TEST("ldrsw x13, [x5, #-24]!", -16, 4);
508 MEM_TEST("ldrsh x13, [x5, #-20]!", -16, 4);
509 MEM_TEST("ldrsh w13, [x5, #-44]!", -16, 4);
510 MEM_TEST("ldrsb x13, [x5, #-72]!", -16, 4);
511 MEM_TEST("ldrsb w13, [x5, #-56]!", -16, 4);
512
513 MEM_TEST("ldrsw x13, [x5], #-24", -16, 4);
514 MEM_TEST("ldrsh x13, [x5], #-20", -16, 4);
515 MEM_TEST("ldrsh w13, [x5], #-44", -16, 4);
516 MEM_TEST("ldrsb x13, [x5], #-72", -16, 4);
517 MEM_TEST("ldrsb w13, [x5], #-56", -16, 4);
518
519 ////////////////////////////////////////////////////////////////
520 printf("LDRS{B,H,W} (simm9, noUpd)\n");
521 MEM_TEST("ldrsw x13, [x5, #-24]", -16, 4);
522 MEM_TEST("ldrsh x13, [x5, #-20]", -16, 4);
523 MEM_TEST("ldrsh w13, [x5, #-44]", -16, 4);
524 MEM_TEST("ldrsb x13, [x5, #-72]", -16, 4);
525 MEM_TEST("ldrsb w13, [x5, #-56]", -16, 4);
526
527 ////////////////////////////////////////////////////////////////
528 printf("LDP,STP (immediate, simm7) (FP&VEC)\n");
529
530 MEM_TEST("stp q17, q18, [x5, 16]", -15, 4);
531 MEM_TEST("stp q19, q18, [x5, 32]!", -11, 4);
532 MEM_TEST("stp q20, q17, [x5], -48", -7, 4);
533
534 MEM_TEST("stp d18, d17, [x5, 16]", -15, 4);
535 MEM_TEST("stp d17, d19, [x5, 32]!", -11, 4);
536 MEM_TEST("stp d20, d18, [x5], -48", -7, 4);
537
538 MEM_TEST("stp s17, s18, [x5, 16]", -15, 4);
539 MEM_TEST("stp s19, s18, [x5, 32]!", -11, 4);
540 MEM_TEST("stp s20, s17, [x5], -48", -7, 4);
541
542 MEM_TEST("ldp q17, q18, [x5, 16]", -15, 4);
543 MEM_TEST("ldp q18, q19, [x5, 32]!", -11, 4);
544 MEM_TEST("ldp q19, q20, [x5], -48", -7, 4);
545
546 MEM_TEST("ldp d20, d17, [x5, 16]", -15, 4);
547 MEM_TEST("ldp d17, d18, [x5, 32]!", -11, 4);
548 MEM_TEST("ldp d18, d19, [x5], -48", -7, 4);
549
550 MEM_TEST("ldp s19, s20, [x5, 16]", -15, 4);
551 MEM_TEST("ldp s20, s17, [x5, 32]!", -11, 4);
552 MEM_TEST("ldp s17, s18, [x5], -48", -7, 4);
553
554 ////////////////////////////////////////////////////////////////
555 printf("LDNP,STNP (immediate, simm7) (FP&VEC, w/ nontemporal hint)\n");
556
557 MEM_TEST("stnp q18, q17, [x5, 16]", -15, 4);
558 MEM_TEST("stnp d20, d19, [x5, 40]", -15, 4);
559 MEM_TEST("stnp s19, s18, [x5, 68]", -15, 4);
560
561 MEM_TEST("ldnp q18, q17, [x5, 16]", -15, 4);
562 MEM_TEST("ldnp d17, d20, [x5, 40]", -15, 4);
563 MEM_TEST("ldnp s20, s19, [x5, 68]", -15, 4);
564
565 ////////////////////////////////////////////////////////////////
566 printf("{LD,ST}R (vector register)\n");
567
568 MEM_TEST("str q17, [x5, x6]", 12, -4);
569 MEM_TEST("str q17, [x5, x6, lsl #4]", 12, -4);
570 MEM_TEST("str q17, [x5, w6, uxtw]", 12, 4);
571 MEM_TEST("str q17, [x5, w6, uxtw #4]", 12, 4);
572 MEM_TEST("str q17, [x5, w6, sxtw]", 12, 4);
573 MEM_TEST("str q17, [x5, w6, sxtw #4]", 12, -4);
574 MEM_TEST("ldr q17, [x5, x6]", 12, -4);
575 MEM_TEST("ldr q17, [x5, x6, lsl #4]", 12, -4);
576 MEM_TEST("ldr q17, [x5, w6, uxtw]", 12, 4);
577 MEM_TEST("ldr q17, [x5, w6, uxtw #4]", 12, 4);
578 MEM_TEST("ldr q17, [x5, w6, sxtw]", 12, 4);
579 MEM_TEST("ldr q17, [x5, w6, sxtw #4]", 12, -4);
580
581 MEM_TEST("str d17, [x5, x6]", 12, -4);
582 MEM_TEST("str d17, [x5, x6, lsl #3]", 12, -4);
583 MEM_TEST("str d17, [x5, w6, uxtw]", 12, 4);
584 MEM_TEST("str d17, [x5, w6, uxtw #3]", 12, 4);
585 MEM_TEST("str d17, [x5, w6, sxtw]", 12, 4);
586 MEM_TEST("str d17, [x5, w6, sxtw #3]", 12, -4);
587 MEM_TEST("ldr d17, [x5, x6]", 12, -4);
588 MEM_TEST("ldr d17, [x5, x6, lsl #3]", 12, -4);
589 MEM_TEST("ldr d17, [x5, w6, uxtw]", 12, 4);
590 MEM_TEST("ldr d17, [x5, w6, uxtw #3]", 12, 4);
591 MEM_TEST("ldr d17, [x5, w6, sxtw]", 12, 4);
592 MEM_TEST("ldr d17, [x5, w6, sxtw #3]", 12, -4);
593
594 MEM_TEST("str s17, [x5, x6]", 12, -4);
595 MEM_TEST("str s17, [x5, x6, lsl #2]", 12, -4);
596 MEM_TEST("str s17, [x5, w6, uxtw]", 12, 4);
597 MEM_TEST("str s17, [x5, w6, uxtw #2]", 12, 4);
598 MEM_TEST("str s17, [x5, w6, sxtw]", 12, 4);
599 MEM_TEST("str s17, [x5, w6, sxtw #2]", 12, -4);
600 MEM_TEST("ldr s17, [x5, x6]", 12, -4);
601 MEM_TEST("ldr s17, [x5, x6, lsl #2]", 12, -4);
602 MEM_TEST("ldr s17, [x5, w6, uxtw]", 12, 4);
603 MEM_TEST("ldr s17, [x5, w6, uxtw #2]", 12, 4);
604 MEM_TEST("ldr s17, [x5, w6, sxtw]", 12, 4);
605 MEM_TEST("ldr s17, [x5, w6, sxtw #2]", 12, -4);
606
607 MEM_TEST("str h17, [x5, x6]", 12, -4);
608 MEM_TEST("str h17, [x5, x6, lsl #1]", 12, -4);
609 MEM_TEST("str h17, [x5, w6, uxtw]", 12, 4);
610 MEM_TEST("str h17, [x5, w6, uxtw #1]", 12, 4);
611 MEM_TEST("str h17, [x5, w6, sxtw]", 12, 4);
612 MEM_TEST("str h17, [x5, w6, sxtw #1]", 12, -4);
613 MEM_TEST("ldr h17, [x5, x6]", 12, -4);
614 MEM_TEST("ldr h17, [x5, x6, lsl #1]", 12, -4);
615 MEM_TEST("ldr h17, [x5, w6, uxtw]", 12, 4);
616 MEM_TEST("ldr h17, [x5, w6, uxtw #1]", 12, 4);
617 MEM_TEST("ldr h17, [x5, w6, sxtw]", 12, 4);
618 MEM_TEST("ldr h17, [x5, w6, sxtw #1]", 12, -4);
619
620 MEM_TEST("str b17, [x5, x6]", 12, -4);
621 MEM_TEST("str b17, [x5, x6, lsl #0]", 12, -4);
622 MEM_TEST("str b17, [x5, w6, uxtw]", 12, 4);
623 MEM_TEST("str b17, [x5, w6, uxtw #0]", 12, 4);
624 MEM_TEST("str b17, [x5, w6, sxtw]", 12, 4);
625 MEM_TEST("str b17, [x5, w6, sxtw #0]", 12, -4);
626 MEM_TEST("ldr b17, [x5, x6]", 12, -4);
627 MEM_TEST("ldr b17, [x5, x6, lsl #0]", 12, -4);
628 MEM_TEST("ldr b17, [x5, w6, uxtw]", 12, 4);
629 MEM_TEST("ldr b17, [x5, w6, uxtw #0]", 12, 4);
630 MEM_TEST("ldr b17, [x5, w6, sxtw]", 12, 4);
631 MEM_TEST("ldr b17, [x5, w6, sxtw #0]", 12, -4);
632
633 ////////////////////////////////////////////////////////////////
634 printf("LDRS{B,H,W} (integer register, SX)\n");
635
636 MEM_TEST("ldrsw x13, [x5,x6]", 12, -4);
637 MEM_TEST("ldrsw x13, [x5,x6, lsl #2]", 12, -4);
638 MEM_TEST("ldrsw x13, [x5,w6,uxtw #0]", 12, 4);
639 MEM_TEST("ldrsw x13, [x5,w6,uxtw #2]", 12, 4);
640 MEM_TEST("ldrsw x13, [x5,w6,sxtw #0]", 12, 4);
641 MEM_TEST("ldrsw x13, [x5,w6,sxtw #2]", 12, -4);
642
643 MEM_TEST("ldrsh x13, [x5,x6]", 12, -4);
644 MEM_TEST("ldrsh x13, [x5,x6, lsl #1]", 12, -4);
645 MEM_TEST("ldrsh x13, [x5,w6,uxtw #0]", 12, 4);
646 MEM_TEST("ldrsh x13, [x5,w6,uxtw #1]", 12, 4);
647 MEM_TEST("ldrsh x13, [x5,w6,sxtw #0]", 12, 4);
648 MEM_TEST("ldrsh x13, [x5,w6,sxtw #1]", 12, -4);
649
650 MEM_TEST("ldrsh w13, [x5,x6]", 12, -4);
651 MEM_TEST("ldrsh w13, [x5,x6, lsl #1]", 12, -4);
652 MEM_TEST("ldrsh w13, [x5,w6,uxtw #0]", 12, 4);
653 MEM_TEST("ldrsh w13, [x5,w6,uxtw #1]", 12, 4);
654 MEM_TEST("ldrsh w13, [x5,w6,sxtw #0]", 12, 4);
655 MEM_TEST("ldrsh w13, [x5,w6,sxtw #1]", 12, -4);
656
657 MEM_TEST("ldrsb x13, [x5,x6]", 12, -4);
658 MEM_TEST("ldrsb x13, [x5,x6, lsl #0]", 12, -4);
659 MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4);
660 MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4);
661 MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, 4);
662 MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, -4);
663
664 MEM_TEST("ldrsb w13, [x5,x6]", 12, -4);
665 MEM_TEST("ldrsb w13, [x5,x6, lsl #0]", 12, -4);
666 MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4);
667 MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4);
668 MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, 4);
669 MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, -4);
670
671 ////////////////////////////////////////////////////////////////
672 printf("LDR/STR (immediate, SIMD&FP, unsigned offset)\n");
673
674 MEM_TEST("str q17, [x5, #-32]", 16, 0);
675 MEM_TEST("str d17, [x5, #-32]", 16, 0);
676 MEM_TEST("str s17, [x5, #-32]", 16, 0);
677 MEM_TEST("str h17, [x5, #-32]", 16, 0);
678 MEM_TEST("str b17, [x5, #-32]", 16, 0);
679 MEM_TEST("ldr q17, [x5, #-32]", 16, 0);
680 MEM_TEST("ldr d17, [x5, #-32]", 16, 0);
681 MEM_TEST("ldr s17, [x5, #-32]", 16, 0);
682 MEM_TEST("ldr h17, [x5, #-32]", 16, 0);
683 MEM_TEST("ldr b17, [x5, #-32]", 16, 0);
684
685 ////////////////////////////////////////////////////////////////
686 printf("LDR/STR (immediate, SIMD&FP, pre/post index)\n");
687
688 MEM_TEST("str q17, [x5], #-32", 16, 0);
689 MEM_TEST("str d17, [x5], #-32", 16, 0);
690 MEM_TEST("str s17, [x5], #-32", 16, 0);
691 MEM_TEST("str h17, [x5], #-32", 16, 0);
692 MEM_TEST("str b17, [x5], #-32", 16, 0);
693 MEM_TEST("ldr q17, [x5], #-32", 16, 0);
694 MEM_TEST("ldr d17, [x5], #-32", 16, 0);
695 MEM_TEST("ldr s17, [x5], #-32", 16, 0);
696 MEM_TEST("ldr h17, [x5], #-32", 16, 0);
697 MEM_TEST("ldr b17, [x5], #-32", 16, 0);
698
699 MEM_TEST("str q17, [x5, #-32]!", 16, 0);
700 MEM_TEST("str d17, [x5, #-32]!", 16, 0);
701 MEM_TEST("str s17, [x5, #-32]!", 16, 0);
702 MEM_TEST("str h17, [x5, #-32]!", 16, 0);
703 MEM_TEST("str b17, [x5, #-32]!", 16, 0);
704 MEM_TEST("ldr q17, [x5, #-32]!", 16, 0);
705 MEM_TEST("ldr d17, [x5, #-32]!", 16, 0);
706 MEM_TEST("ldr s17, [x5, #-32]!", 16, 0);
707 MEM_TEST("ldr h17, [x5, #-32]!", 16, 0);
708 MEM_TEST("ldr b17, [x5, #-32]!", 16, 0);
709
710 ////////////////////////////////////////////////////////////////
711 printf("LDUR/STUR (unscaled offset, SIMD&FP)\n");
712
713 MEM_TEST("str q17, [x5, #-13]", 16, 0);
714 MEM_TEST("str d17, [x5, #-13]", 16, 0);
715 MEM_TEST("str s17, [x5, #-13]", 16, 0);
716 MEM_TEST("str h17, [x5, #-13]", 16, 0);
717 MEM_TEST("str b17, [x5, #-13]", 16, 0);
718 MEM_TEST("ldr q17, [x5, #-13]", 16, 0);
719 MEM_TEST("ldr d17, [x5, #-13]", 16, 0);
720 MEM_TEST("ldr s17, [x5, #-13]", 16, 0);
721 MEM_TEST("ldr h17, [x5, #-13]", 16, 0);
722 MEM_TEST("ldr b17, [x5, #-13]", 16, 0);
723
724 ////////////////////////////////////////////////////////////////
725 printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
726
727 MEM_TEST("xyzzy10: ldr s17, xyzzy10 - 8", 0, 0)
728 MEM_TEST("xyzzy11: ldr d17, xyzzy11 + 8", 0, 0)
729 MEM_TEST("xyzzy12: ldr q17, xyzzy12 + 4", 0, 0)
730
731 ////////////////////////////////////////////////////////////////
732 printf("LD1/ST1 (multiple 1-elem structs to/from 1 reg\n");
733
734 MEM_TEST("st1 {v18.2d}, [x5]", 17, 7)
735 MEM_TEST("st1 {v18.2d}, [x5], #16", 9, 9)
736 MEM_TEST("st1 {v18.2d}, [x5], x6", -13, -5)
737
738 MEM_TEST("st1 {v18.1d}, [x5]", 17, 7)
739 MEM_TEST("st1 {v18.1d}, [x5], #8", 9, 9)
740 MEM_TEST("st1 {v18.1d}, [x5], x6", -13, -5)
741
742 MEM_TEST("st1 {v18.4s}, [x5]", 17, 7)
743 MEM_TEST("st1 {v18.4s}, [x5], #16", 9, 9)
744 MEM_TEST("st1 {v18.4s}, [x5], x6", -13, -5)
745
746 MEM_TEST("st1 {v18.2s}, [x5]", 17, 7)
747 MEM_TEST("st1 {v18.2s}, [x5], #8", 9, 9)
748 MEM_TEST("st1 {v18.2s}, [x5], x6", -13, -5)
749
750 MEM_TEST("st1 {v18.8h}, [x5]", 17, 7)
751 MEM_TEST("st1 {v18.8h}, [x5], #16", 9, 9)
752 MEM_TEST("st1 {v18.8h}, [x5], x6", -13, -5)
753
754 MEM_TEST("st1 {v18.4h}, [x5]", 17, 7)
755 MEM_TEST("st1 {v18.4h}, [x5], #8", 9, 9)
756 MEM_TEST("st1 {v18.4h}, [x5], x6", -13, -5)
757
758 MEM_TEST("st1 {v18.16b}, [x5]", 17, 7)
759 MEM_TEST("st1 {v18.16b}, [x5], #16", 9, 9)
760 MEM_TEST("st1 {v18.16b}, [x5], x6", -13, -5)
761
762 MEM_TEST("st1 {v18.8b}, [x5]", 17, 7)
763 MEM_TEST("st1 {v18.8b}, [x5], #8", 9, 9)
764 MEM_TEST("st1 {v18.8b}, [x5], x6", -13, -5)
765
766 MEM_TEST("ld1 {v18.2d}, [x5]", 17, 7)
767 MEM_TEST("ld1 {v18.2d}, [x5], #16", 9, 9)
768 MEM_TEST("ld1 {v18.2d}, [x5], x6", -13, -5)
769
770 MEM_TEST("ld1 {v18.1d}, [x5]", 17, 7)
771 MEM_TEST("ld1 {v18.1d}, [x5], #8", 9, 9)
772 MEM_TEST("ld1 {v18.1d}, [x5], x6", -13, -5)
773
774 MEM_TEST("ld1 {v18.4s}, [x5]", 17, 7)
775 MEM_TEST("ld1 {v18.4s}, [x5], #16", 9, 9)
776 MEM_TEST("ld1 {v18.4s}, [x5], x6", -13, -5)
777
778 MEM_TEST("ld1 {v18.2s}, [x5]", 17, 7)
779 MEM_TEST("ld1 {v18.2s}, [x5], #8", 9, 9)
780 MEM_TEST("ld1 {v18.2s}, [x5], x6", -13, -5)
781
782 MEM_TEST("ld1 {v18.8h}, [x5]", 17, 7)
783 MEM_TEST("ld1 {v18.8h}, [x5], #16", 9, 9)
784 MEM_TEST("ld1 {v18.8h}, [x5], x6", -13, -5)
785
786 MEM_TEST("ld1 {v18.4h}, [x5]", 17, 7)
787 MEM_TEST("ld1 {v18.4h}, [x5], #8", 9, 9)
788 MEM_TEST("ld1 {v18.4h}, [x5], x6", -13, -5)
789
790 MEM_TEST("ld1 {v18.16b}, [x5]", 17, 7)
791 MEM_TEST("ld1 {v18.16b}, [x5], #16", 9, 9)
792 MEM_TEST("ld1 {v18.16b}, [x5], x6", -13, -5)
793
794 MEM_TEST("ld1 {v18.8b}, [x5]", 17, 7)
795 MEM_TEST("ld1 {v18.8b}, [x5], #8", 9, 9)
796 MEM_TEST("ld1 {v18.8b}, [x5], x6", -13, -5)
797
798 ////////////////////////////////////////////////////////////////
799 printf("LD2/ST2 (multiple 2-elem structs to/from 2 regs\n");
800
801 MEM_TEST("st2 {v18.2d, v19.2d}, [x5]", 17, 7)
802 MEM_TEST("st2 {v18.2d, v19.2d}, [x5], #32", 9, 9)
803 MEM_TEST("st2 {v18.2d, v19.2d}, [x5], x6", -13, -5)
804
805 /* no 1d case */
806
807 MEM_TEST("st2 {v18.4s, v19.4s}, [x5]", 17, 7)
808 MEM_TEST("st2 {v18.4s, v19.4s}, [x5], #32", 9, 9)
809 MEM_TEST("st2 {v18.4s, v19.4s}, [x5], x6", -13, -5)
810
811 MEM_TEST("st2 {v18.2s, v19.2s}, [x5]", 17, 7)
812 MEM_TEST("st2 {v18.2s, v19.2s}, [x5], #16", 9, 9)
813 MEM_TEST("st2 {v18.2s, v19.2s}, [x5], x6", -13, -5)
814
815 MEM_TEST("st2 {v18.8h, v19.8h}, [x5]", 17, 7)
816 MEM_TEST("st2 {v18.8h, v19.8h}, [x5], #32", 9, 9)
817 MEM_TEST("st2 {v18.8h, v19.8h}, [x5], x6", -13, -5)
818
819 MEM_TEST("st2 {v18.4h, v19.4h}, [x5]", 17, 7)
820 MEM_TEST("st2 {v18.4h, v19.4h}, [x5], #16", 9, 9)
821 MEM_TEST("st2 {v18.4h, v19.4h}, [x5], x6", -13, -5)
822
823 MEM_TEST("st2 {v18.16b, v19.16b}, [x5]", 17, 7)
824 MEM_TEST("st2 {v18.16b, v19.16b}, [x5], #32", 9, 9)
825 MEM_TEST("st2 {v18.16b, v19.16b}, [x5], x6", -13, -5)
826
827 MEM_TEST("st2 {v18.8b, v19.8b}, [x5]", 17, 7)
828 MEM_TEST("st2 {v18.8b, v19.8b}, [x5], #16", 9, 9)
829 MEM_TEST("st2 {v18.8b, v19.8b}, [x5], x6", -13, -5)
830
831 MEM_TEST("ld2 {v18.2d, v19.2d}, [x5]", 17, 7)
832 MEM_TEST("ld2 {v18.2d, v19.2d}, [x5], #32", 9, 9)
833 MEM_TEST("ld2 {v18.2d, v19.2d}, [x5], x6", -13, -5)
834
835 /* no 1d case */
836
837 MEM_TEST("ld2 {v18.4s, v19.4s}, [x5]", 17, 7)
838 MEM_TEST("ld2 {v18.4s, v19.4s}, [x5], #32", 9, 9)
839 MEM_TEST("ld2 {v18.4s, v19.4s}, [x5], x6", -13, -5)
840
841 MEM_TEST("ld2 {v18.2s, v19.2s}, [x5]", 17, 7)
842 MEM_TEST("ld2 {v18.2s, v19.2s}, [x5], #16", 9, 9)
843 MEM_TEST("ld2 {v18.2s, v19.2s}, [x5], x6", -13, -5)
844
845 MEM_TEST("ld2 {v18.8h, v19.8h}, [x5]", 17, 7)
846 MEM_TEST("ld2 {v18.8h, v19.8h}, [x5], #32", 9, 9)
847 MEM_TEST("ld2 {v18.8h, v19.8h}, [x5], x6", -13, -5)
848
849 MEM_TEST("ld2 {v18.4h, v19.4h}, [x5]", 17, 7)
850 MEM_TEST("ld2 {v18.4h, v19.4h}, [x5], #16", 9, 9)
851 MEM_TEST("ld2 {v18.4h, v19.4h}, [x5], x6", -13, -5)
852
853 MEM_TEST("ld2 {v18.16b, v19.16b}, [x5]", 17, 7)
854 MEM_TEST("ld2 {v18.16b, v19.16b}, [x5], #32", 9, 9)
855 MEM_TEST("ld2 {v18.16b, v19.16b}, [x5], x6", -13, -5)
856
857 MEM_TEST("ld2 {v18.8b, v19.8b}, [x5]", 17, 7)
858 MEM_TEST("ld2 {v18.8b, v19.8b}, [x5], #16", 9, 9)
859 MEM_TEST("ld2 {v18.8b, v19.8b}, [x5], x6", -13, -5)
860
861 ////////////////////////////////////////////////////////////////
862 printf("LD3/ST3 (multiple 3-elem structs to/from 3 regs\n");
863
864 MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
865 MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
866 MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
867
868 /* no 1d case */
869
870 MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
871 MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
872 MEM_TEST("st3 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
873
874 MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
875 MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
876 MEM_TEST("st3 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
877
878 MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
879 MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
880 MEM_TEST("st3 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
881
882 MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
883 MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
884 MEM_TEST("st3 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
885
886 MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
887 MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
888 MEM_TEST("st3 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
889
890 MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
891 MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
892 MEM_TEST("st3 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
893
894 MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
895 MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
896 MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
897
898 /* no 1d case */
899
900 MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
901 MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
902 MEM_TEST("ld3 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
903
904 MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
905 MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
906 MEM_TEST("ld3 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
907
908 MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
909 MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
910 MEM_TEST("ld3 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
911
912 MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
913 MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
914 MEM_TEST("ld3 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
915
916 MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
917 MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
918 MEM_TEST("ld3 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
919
920 MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
921 MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
922 MEM_TEST("ld3 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
923
924 ////////////////////////////////////////////////////////////////
925 printf("LD4/ST4 (multiple 4-elem structs to/from 4 regs\n");
926
927 MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
928 MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
929 MEM_TEST("st4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
930
931 /* no 1d case */
932
933 MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
934 MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
935 MEM_TEST("st4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
936
937 MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
938 MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
939 MEM_TEST("st4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
940
941 MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
942 MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
943 MEM_TEST("st4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
944
945 MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
946 MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
947 MEM_TEST("st4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
948
949 MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
950 MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
951 MEM_TEST("st4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
952
953 MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
954 MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
955 MEM_TEST("st4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
956
957 MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
958 MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
959 MEM_TEST("ld4 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
960
961 /* no 1d case */
962
963 MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
964 MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
965 MEM_TEST("ld4 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
966
967 MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
968 MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
969 MEM_TEST("ld4 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
970
971 MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
972 MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
973 MEM_TEST("ld4 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
974
975 MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
976 MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
977 MEM_TEST("ld4 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
978
979 MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
980 MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
981 MEM_TEST("ld4 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
982
983 MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
984 MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
985 MEM_TEST("ld4 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
986
987 ////////////////////////////////////////////////////////////////
988 printf("LD1/ST1 (multiple 1-elem structs to/from 2/3/4 regs\n");
989
990 MEM_TEST("st1 {v19.2d, v20.2d}, [x5]", 17, 7)
991 MEM_TEST("st1 {v19.2d, v20.2d}, [x5], #32", 9, 9)
992 MEM_TEST("st1 {v19.2d, v20.2d}, [x5], x6", -13, -5)
993
994 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
995 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
996 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
997
998 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
999 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
1000 MEM_TEST("st1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
1001
1002
1003 MEM_TEST("st1 {v19.1d, v20.1d}, [x5]", 17, 7)
1004 MEM_TEST("st1 {v19.1d, v20.1d}, [x5], #16", 9, 9)
1005 MEM_TEST("st1 {v19.1d, v20.1d}, [x5], x6", -13, -5)
1006
1007 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5]", 17, 7)
1008 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5], #24", 9, 9)
1009 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d}, [x5], x6", -13, -5)
1010
1011 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5]", 17, 7)
1012 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32", 9, 9)
1013 MEM_TEST("st1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6", -13, -5)
1014
1015
1016 MEM_TEST("st1 {v19.4s, v20.4s}, [x5]", 17, 7)
1017 MEM_TEST("st1 {v19.4s, v20.4s}, [x5], #32", 9, 9)
1018 MEM_TEST("st1 {v19.4s, v20.4s}, [x5], x6", -13, -5)
1019
1020 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
1021 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
1022 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
1023
1024 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
1025 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
1026 MEM_TEST("st1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
1027
1028
1029 MEM_TEST("st1 {v19.2s, v20.2s}, [x5]", 17, 7)
1030 MEM_TEST("st1 {v19.2s, v20.2s}, [x5], #16", 9, 9)
1031 MEM_TEST("st1 {v19.2s, v20.2s}, [x5], x6", -13, -5)
1032
1033 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
1034 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
1035 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
1036
1037 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
1038 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
1039 MEM_TEST("st1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
1040
1041
1042 MEM_TEST("st1 {v19.8h, v20.8h}, [x5]", 17, 7)
1043 MEM_TEST("st1 {v19.8h, v20.8h}, [x5], #32", 9, 9)
1044 MEM_TEST("st1 {v19.8h, v20.8h}, [x5], x6", -13, -5)
1045
1046 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
1047 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
1048 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
1049
1050 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
1051 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
1052 MEM_TEST("st1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
1053
1054
1055 MEM_TEST("st1 {v19.4h, v20.4h}, [x5]", 17, 7)
1056 MEM_TEST("st1 {v19.4h, v20.4h}, [x5], #16", 9, 9)
1057 MEM_TEST("st1 {v19.4h, v20.4h}, [x5], x6", -13, -5)
1058
1059 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
1060 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
1061 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
1062
1063 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
1064 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
1065 MEM_TEST("st1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
1066
1067
1068 MEM_TEST("st1 {v19.16b, v20.16b}, [x5]", 17, 7)
1069 MEM_TEST("st1 {v19.16b, v20.16b}, [x5], #32", 9, 9)
1070 MEM_TEST("st1 {v19.16b, v20.16b}, [x5], x6", -13, -5)
1071
1072 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
1073 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
1074 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
1075
1076 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
1077 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
1078 MEM_TEST("st1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
1079
1080
1081 MEM_TEST("st1 {v19.8b, v20.8b}, [x5]", 17, 7)
1082 MEM_TEST("st1 {v19.8b, v20.8b}, [x5], #16", 9, 9)
1083 MEM_TEST("st1 {v19.8b, v20.8b}, [x5], x6", -13, -5)
1084
1085 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
1086 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
1087 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
1088
1089 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
1090 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
1091 MEM_TEST("st1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
1092
1093
1094 MEM_TEST("ld1 {v19.2d, v20.2d}, [x5]", 17, 7)
1095 MEM_TEST("ld1 {v19.2d, v20.2d}, [x5], #32", 9, 9)
1096 MEM_TEST("ld1 {v19.2d, v20.2d}, [x5], x6", -13, -5)
1097
1098 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5]", 17, 7)
1099 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5], #48", 9, 9)
1100 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d}, [x5], x6", -13, -5)
1101
1102 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5]", 17, 7)
1103 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], #64", 9, 9)
1104 MEM_TEST("ld1 {v17.2d, v18.2d, v19.2d, v20.2d}, [x5], x6", -13, -5)
1105
1106
1107 MEM_TEST("ld1 {v19.1d, v20.1d}, [x5]", 17, 7)
1108 MEM_TEST("ld1 {v19.1d, v20.1d}, [x5], #16", 9, 9)
1109 MEM_TEST("ld1 {v19.1d, v20.1d}, [x5], x6", -13, -5)
1110
1111 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5]", 17, 7)
1112 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5], #24", 9, 9)
1113 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d}, [x5], x6", -13, -5)
1114
1115 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5]", 17, 7)
1116 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], #32", 9, 9)
1117 MEM_TEST("ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x5], x6", -13, -5)
1118
1119
1120 MEM_TEST("ld1 {v19.4s, v20.4s}, [x5]", 17, 7)
1121 MEM_TEST("ld1 {v19.4s, v20.4s}, [x5], #32", 9, 9)
1122 MEM_TEST("ld1 {v19.4s, v20.4s}, [x5], x6", -13, -5)
1123
1124 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5]", 17, 7)
1125 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5], #48", 9, 9)
1126 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s}, [x5], x6", -13, -5)
1127
1128 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5]", 17, 7)
1129 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], #64", 9, 9)
1130 MEM_TEST("ld1 {v17.4s, v18.4s, v19.4s, v20.4s}, [x5], x6", -13, -5)
1131
1132
1133 MEM_TEST("ld1 {v19.2s, v20.2s}, [x5]", 17, 7)
1134 MEM_TEST("ld1 {v19.2s, v20.2s}, [x5], #16", 9, 9)
1135 MEM_TEST("ld1 {v19.2s, v20.2s}, [x5], x6", -13, -5)
1136
1137 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5]", 17, 7)
1138 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5], #24", 9, 9)
1139 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s}, [x5], x6", -13, -5)
1140
1141 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5]", 17, 7)
1142 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], #32", 9, 9)
1143 MEM_TEST("ld1 {v17.2s, v18.2s, v19.2s, v20.2s}, [x5], x6", -13, -5)
1144
1145
1146 MEM_TEST("ld1 {v19.8h, v20.8h}, [x5]", 17, 7)
1147 MEM_TEST("ld1 {v19.8h, v20.8h}, [x5], #32", 9, 9)
1148 MEM_TEST("ld1 {v19.8h, v20.8h}, [x5], x6", -13, -5)
1149
1150 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5]", 17, 7)
1151 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5], #48", 9, 9)
1152 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h}, [x5], x6", -13, -5)
1153
1154 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5]", 17, 7)
1155 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], #64", 9, 9)
1156 MEM_TEST("ld1 {v17.8h, v18.8h, v19.8h, v20.8h}, [x5], x6", -13, -5)
1157
1158
1159 MEM_TEST("ld1 {v19.4h, v20.4h}, [x5]", 17, 7)
1160 MEM_TEST("ld1 {v19.4h, v20.4h}, [x5], #16", 9, 9)
1161 MEM_TEST("ld1 {v19.4h, v20.4h}, [x5], x6", -13, -5)
1162
1163 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5]", 17, 7)
1164 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5], #24", 9, 9)
1165 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h}, [x5], x6", -13, -5)
1166
1167 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5]", 17, 7)
1168 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], #32", 9, 9)
1169 MEM_TEST("ld1 {v17.4h, v18.4h, v19.4h, v20.4h}, [x5], x6", -13, -5)
1170
1171
1172 MEM_TEST("ld1 {v19.16b, v20.16b}, [x5]", 17, 7)
1173 MEM_TEST("ld1 {v19.16b, v20.16b}, [x5], #32", 9, 9)
1174 MEM_TEST("ld1 {v19.16b, v20.16b}, [x5], x6", -13, -5)
1175
1176 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5]", 17, 7)
1177 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5], #48", 9, 9)
1178 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5], x6", -13, -5)
1179
1180 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 17, 7)
1181 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #64", 9, 9)
1182 MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", -13, -5)
1183
1184
1185 MEM_TEST("ld1 {v19.8b, v20.8b}, [x5]", 17, 7)
1186 MEM_TEST("ld1 {v19.8b, v20.8b}, [x5], #16", 9, 9)
1187 MEM_TEST("ld1 {v19.8b, v20.8b}, [x5], x6", -13, -5)
1188
1189 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5]", 17, 7)
1190 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5], #24", 9, 9)
1191 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b}, [x5], x6", -13, -5)
1192
1193 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5]", 17, 7)
1194 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], #32", 9, 9)
1195 MEM_TEST("ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x5], x6", -13, -5)
1196
1197
1198 ////////////////////////////////////////////////////////////////
1199 printf("LD1R (single structure, replicate)\n");
1200
1201 MEM_TEST("ld1r {v17.2d}, [x5]", 3, -5)
1202 MEM_TEST("ld1r {v17.1d}, [x5]", 3, -4)
1203 MEM_TEST("ld1r {v17.4s}, [x5]", 3, -3)
1204 MEM_TEST("ld1r {v17.2s}, [x5]", 3, -2)
1205 MEM_TEST("ld1r {v17.8h}, [x5]", 3, -1)
1206 MEM_TEST("ld1r {v17.4h}, [x5]", 3, 1)
1207 MEM_TEST("ld1r {v17.16b}, [x5]", 3, 2)
1208 MEM_TEST("ld1r {v17.8b}, [x5]", 3, 3)
1209
1210 MEM_TEST("ld1r {v17.2d}, [x5], #8", 3, -5)
1211 MEM_TEST("ld1r {v17.1d}, [x5], #8", 3, -4)
1212 MEM_TEST("ld1r {v17.4s}, [x5], #4", 3, -3)
1213 MEM_TEST("ld1r {v17.2s}, [x5], #4", 3, -2)
1214 MEM_TEST("ld1r {v17.8h}, [x5], #2", 3, -1)
1215 MEM_TEST("ld1r {v17.4h}, [x5], #2", 3, 1)
1216 MEM_TEST("ld1r {v17.16b}, [x5], #1", 3, 2)
1217 MEM_TEST("ld1r {v17.8b}, [x5], #1", 3, 3)
1218
1219 MEM_TEST("ld1r {v17.2d}, [x5], x6", 3, -5)
1220 MEM_TEST("ld1r {v17.1d}, [x5], x6", 3, -4)
1221 MEM_TEST("ld1r {v17.4s}, [x5], x6", 3, -3)
1222 MEM_TEST("ld1r {v17.2s}, [x5], x6", 3, -2)
1223 MEM_TEST("ld1r {v17.8h}, [x5], x6", 3, -1)
1224 MEM_TEST("ld1r {v17.4h}, [x5], x6", 3, 1)
1225 MEM_TEST("ld1r {v17.16b}, [x5], x6", 3, 2)
1226 MEM_TEST("ld1r {v17.8b}, [x5], x6", 3, 3)
1227
1228
1229 ////////////////////////////////////////////////////////////////
1230 printf("LD2R (single structure, replicate)\n");
1231
1232 MEM_TEST("ld2r {v17.2d , v18.2d }, [x5]", 3, -5)
1233 MEM_TEST("ld2r {v18.1d , v19.1d }, [x5]", 3, -4)
1234 MEM_TEST("ld2r {v19.4s , v20.4s }, [x5]", 3, -3)
1235 MEM_TEST("ld2r {v17.2s , v18.2s }, [x5]", 3, -2)
1236 MEM_TEST("ld2r {v18.8h , v19.8h }, [x5]", 3, -1)
1237 MEM_TEST("ld2r {v19.4h , v20.4h }, [x5]", 3, 1)
1238 MEM_TEST("ld2r {v17.16b, v18.16b}, [x5]", 3, 2)
1239 MEM_TEST("ld2r {v18.8b , v19.8b }, [x5]", 3, 3)
1240
1241 MEM_TEST("ld2r {v19.2d , v20.2d }, [x5], #16", 3, -5)
1242 MEM_TEST("ld2r {v17.1d , v18.1d }, [x5], #16", 3, -4)
1243 MEM_TEST("ld2r {v18.4s , v19.4s }, [x5], #8", 3, -3)
1244 MEM_TEST("ld2r {v19.2s , v20.2s }, [x5], #8", 3, -2)
1245 MEM_TEST("ld2r {v17.8h , v18.8h }, [x5], #4", 3, -1)
1246 MEM_TEST("ld2r {v18.4h , v19.4h }, [x5], #4", 3, 1)
1247 MEM_TEST("ld2r {v19.16b, v20.16b}, [x5], #2", 3, 2)
1248 MEM_TEST("ld2r {v17.8b , v18.8b }, [x5], #2", 3, 3)
1249
1250 MEM_TEST("ld2r {v18.2d , v19.2d }, [x5], x6", 3, -5)
1251 MEM_TEST("ld2r {v19.1d , v20.1d }, [x5], x6", 3, -4)
1252 MEM_TEST("ld2r {v17.4s , v18.4s }, [x5], x6", 3, -3)
1253 MEM_TEST("ld2r {v18.2s , v19.2s }, [x5], x6", 3, -2)
1254 MEM_TEST("ld2r {v19.8h , v20.8h }, [x5], x6", 3, -1)
1255 MEM_TEST("ld2r {v17.4h , v18.4h }, [x5], x6", 3, 1)
1256 MEM_TEST("ld2r {v18.16b, v19.16b}, [x5], x6", 3, 2)
1257 MEM_TEST("ld2r {v19.8b , v20.8b }, [x5], x6", 3, 3)
1258
1259
1260 //////////////////////////////////////////////////////////////////
1261 printf("LD3R (single structure, replicate)\n");
1262
1263 MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5]", 3, -5)
1264 MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5]", 3, -4)
1265 MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5]", 3, -3)
1266 MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5]", 3, -2)
1267 MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5]", 3, -5)
1268 MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5]", 3, -4)
1269 MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5]", 3, -3)
1270 MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5]", 3, -2)
1271
1272 MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5], #24", 3, -5)
1273 MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5], #24", 3, -4)
1274 MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5], #12", 3, -3)
1275 MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5], #12", 3, -2)
1276 MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5], #6", 3, -5)
1277 MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5], #6", 3, -4)
1278 MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5], #3", 3, -3)
1279 MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5], #3", 3, -2)
1280
1281 MEM_TEST("ld3r {v17.2d , v18.2d , v19.2d }, [x5], x6", 3, -5)
1282 MEM_TEST("ld3r {v18.1d , v19.1d , v20.1d }, [x5], x6", 3, -4)
1283 MEM_TEST("ld3r {v17.4s , v18.4s , v19.4s }, [x5], x6", 3, -3)
1284 MEM_TEST("ld3r {v18.2s , v19.2s , v20.2s }, [x5], x6", 3, -2)
1285 MEM_TEST("ld3r {v17.8h , v18.8h , v19.8h }, [x5], x6", 3, -5)
1286 MEM_TEST("ld3r {v18.4h , v19.4h , v20.4h }, [x5], x6", 3, -4)
1287 MEM_TEST("ld3r {v17.16b, v18.16b, v19.16b}, [x5], x6", 3, -3)
1288 MEM_TEST("ld3r {v18.8b , v19.8b , v20.8b }, [x5], x6", 3, -2)
1289
1290
1291 ////////////////////////////////////////////////////////////////
1292 printf("LD4R (single structure, replicate)\n");
1293
1294 MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5]", 3, -5)
1295 MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5]", 3, -4)
1296 MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5]", 3, -3)
1297 MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5]", 3, -2)
1298 MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5]", 3, -5)
1299 MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5]", 3, -4)
1300 MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5]", 3, -3)
1301 MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5]", 3, -2)
1302
1303 MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], #32", 3, -5)
1304 MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], #32", 3, -4)
1305 MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], #16", 3, -3)
1306 MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], #16", 3, -2)
1307 MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], #8", 3, -5)
1308 MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], #8", 3, -4)
1309 MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], #4", 3, -3)
1310 MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], #4", 3, -2)
1311
1312 MEM_TEST("ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5], x6", 3, -5)
1313 MEM_TEST("ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5], x6", 3, -4)
1314 MEM_TEST("ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5], x6", 3, -3)
1315 MEM_TEST("ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5], x6", 3, -2)
1316 MEM_TEST("ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5], x6", 3, -5)
1317 MEM_TEST("ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5], x6", 3, -4)
1318 MEM_TEST("ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5], x6", 3, -3)
1319 MEM_TEST("ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5], x6", 3, -2)
1320
1321
1322 ////////////////////////////////////////////////////////////////
1323 printf("LD1/ST1 (single 1-elem struct to/from one lane of 1 reg\n");
1324
1325 MEM_TEST("st1 {v19.d}[0], [x5]", 17, 7)
1326 MEM_TEST("st1 {v19.d}[0], [x5], #8", -9, 12)
1327 MEM_TEST("st1 {v19.d}[0], [x5], x6", 9, 13)
1328
1329 MEM_TEST("st1 {v19.d}[1], [x5]", 17, 7)
1330 MEM_TEST("st1 {v19.d}[1], [x5], #8", -9, 12)
1331 MEM_TEST("st1 {v19.d}[1], [x5], x6", 9, 13)
1332
1333 MEM_TEST("st1 {v19.s}[0], [x5]", 17, 7)
1334 MEM_TEST("st1 {v19.s}[0], [x5], #4", -9, 12)
1335 MEM_TEST("st1 {v19.s}[0], [x5], x6", 9, 13)
1336
1337 MEM_TEST("st1 {v19.s}[3], [x5]", 17, 7)
1338 MEM_TEST("st1 {v19.s}[3], [x5], #4", -9, 12)
1339 MEM_TEST("st1 {v19.s}[3], [x5], x6", 9, 13)
1340
1341 MEM_TEST("st1 {v19.h}[0], [x5]", 17, 7)
1342 MEM_TEST("st1 {v19.h}[0], [x5], #2", -9, 12)
1343 MEM_TEST("st1 {v19.h}[0], [x5], x6", 9, 13)
1344
1345 MEM_TEST("st1 {v19.h}[6], [x5]", 17, 7)
1346 MEM_TEST("st1 {v19.h}[6], [x5], #2", -9, 12)
1347 MEM_TEST("st1 {v19.h}[6], [x5], x6", 9, 13)
1348
1349 MEM_TEST("st1 {v19.b}[0], [x5]", 17, 7)
1350 MEM_TEST("st1 {v19.b}[0], [x5], #1", -9, 12)
1351 MEM_TEST("st1 {v19.b}[0], [x5], x6", 9, 13)
1352
1353 MEM_TEST("st1 {v19.b}[13], [x5]", 17, 7)
1354 MEM_TEST("st1 {v19.b}[13], [x5], #1", -9, 12)
1355 MEM_TEST("st1 {v19.b}[13], [x5], x6", 9, 13)
1356
1357
1358 MEM_TEST("ld1 {v19.d}[0], [x5]", 17, 7)
1359 MEM_TEST("ld1 {v19.d}[0], [x5], #8", -9, 12)
1360 MEM_TEST("ld1 {v19.d}[0], [x5], x6", 9, 13)
1361
1362 MEM_TEST("ld1 {v19.d}[1], [x5]", 17, 7)
1363 MEM_TEST("ld1 {v19.d}[1], [x5], #8", -9, 12)
1364 MEM_TEST("ld1 {v19.d}[1], [x5], x6", 9, 13)
1365
1366 MEM_TEST("ld1 {v19.s}[0], [x5]", 17, 7)
1367 MEM_TEST("ld1 {v19.s}[0], [x5], #4", -9, 12)
1368 MEM_TEST("ld1 {v19.s}[0], [x5], x6", 9, 13)
1369
1370 MEM_TEST("ld1 {v19.s}[3], [x5]", 17, 7)
1371 MEM_TEST("ld1 {v19.s}[3], [x5], #4", -9, 12)
1372 MEM_TEST("ld1 {v19.s}[3], [x5], x6", 9, 13)
1373
1374 MEM_TEST("ld1 {v19.h}[0], [x5]", 17, 7)
1375 MEM_TEST("ld1 {v19.h}[0], [x5], #2", -9, 12)
1376 MEM_TEST("ld1 {v19.h}[0], [x5], x6", 9, 13)
1377
1378 MEM_TEST("ld1 {v19.h}[6], [x5]", 17, 7)
1379 MEM_TEST("ld1 {v19.h}[6], [x5], #2", -9, 12)
1380 MEM_TEST("ld1 {v19.h}[6], [x5], x6", 9, 13)
1381
1382 MEM_TEST("ld1 {v19.b}[0], [x5]", 17, 7)
1383 MEM_TEST("ld1 {v19.b}[0], [x5], #1", -9, 12)
1384 MEM_TEST("ld1 {v19.b}[0], [x5], x6", 9, 13)
1385
1386 MEM_TEST("ld1 {v19.b}[13], [x5]", 17, 7)
1387 MEM_TEST("ld1 {v19.b}[13], [x5], #1", -9, 12)
1388 MEM_TEST("ld1 {v19.b}[13], [x5], x6", 9, 13)
1389
1390
1391 ////////////////////////////////////////////////////////////////
1392 printf("LD2/ST2 (single 2-elem struct to/from one lane of 2 regs\n");
1393
1394 MEM_TEST("st2 {v18.d, v19.d}[0], [x5]", 17, 7)
1395 MEM_TEST("st2 {v18.d, v19.d}[0], [x5], #16", -9, 12)
1396 MEM_TEST("st2 {v18.d, v19.d}[0], [x5], x6", 9, 13)
1397
1398 MEM_TEST("st2 {v18.d, v19.d}[1], [x5]", 17, 7)
1399 MEM_TEST("st2 {v18.d, v19.d}[1], [x5], #16", -9, 12)
1400 MEM_TEST("st2 {v18.d, v19.d}[1], [x5], x6", 9, 13)
1401
1402 MEM_TEST("st2 {v18.s, v19.s}[0], [x5]", 17, 7)
1403 MEM_TEST("st2 {v18.s, v19.s}[0], [x5], #8", -9, 12)
1404 MEM_TEST("st2 {v18.s, v19.s}[0], [x5], x6", 9, 13)
1405
1406 MEM_TEST("st2 {v18.s, v19.s}[3], [x5]", 17, 7)
1407 MEM_TEST("st2 {v18.s, v19.s}[3], [x5], #8", -9, 12)
1408 MEM_TEST("st2 {v18.s, v19.s}[3], [x5], x6", 9, 13)
1409
1410 MEM_TEST("st2 {v18.h, v19.h}[0], [x5]", 17, 7)
1411 MEM_TEST("st2 {v18.h, v19.h}[0], [x5], #4", -9, 12)
1412 MEM_TEST("st2 {v18.h, v19.h}[0], [x5], x6", 9, 13)
1413
1414 MEM_TEST("st2 {v18.h, v19.h}[6], [x5]", 17, 7)
1415 MEM_TEST("st2 {v18.h, v19.h}[6], [x5], #4", -9, 12)
1416 MEM_TEST("st2 {v18.h, v19.h}[6], [x5], x6", 9, 13)
1417
1418 MEM_TEST("st2 {v18.b, v19.b}[0], [x5]", 17, 7)
1419 MEM_TEST("st2 {v18.b, v19.b}[0], [x5], #2", -9, 12)
1420 MEM_TEST("st2 {v18.b, v19.b}[0], [x5], x6", 9, 13)
1421
1422 MEM_TEST("st2 {v18.b, v19.b}[13], [x5]", 17, 7)
1423 MEM_TEST("st2 {v18.b, v19.b}[13], [x5], #2", -9, 12)
1424 MEM_TEST("st2 {v18.b, v19.b}[13], [x5], x6", 9, 13)
1425
1426
1427 MEM_TEST("ld2 {v18.d, v19.d}[0], [x5]", 17, 7)
1428 MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], #16", -9, 12)
1429 MEM_TEST("ld2 {v18.d, v19.d}[0], [x5], x6", 9, 13)
1430
1431 MEM_TEST("ld2 {v18.d, v19.d}[1], [x5]", 17, 7)
1432 MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], #16", -9, 12)
1433 MEM_TEST("ld2 {v18.d, v19.d}[1], [x5], x6", 9, 13)
1434
1435 MEM_TEST("ld2 {v18.s, v19.s}[0], [x5]", 17, 7)
1436 MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], #8", -9, 12)
1437 MEM_TEST("ld2 {v18.s, v19.s}[0], [x5], x6", 9, 13)
1438
1439 MEM_TEST("ld2 {v18.s, v19.s}[3], [x5]", 17, 7)
1440 MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], #8", -9, 12)
1441 MEM_TEST("ld2 {v18.s, v19.s}[3], [x5], x6", 9, 13)
1442
1443 MEM_TEST("ld2 {v18.h, v19.h}[0], [x5]", 17, 7)
1444 MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], #4", -9, 12)
1445 MEM_TEST("ld2 {v18.h, v19.h}[0], [x5], x6", 9, 13)
1446
1447 MEM_TEST("ld2 {v18.h, v19.h}[6], [x5]", 17, 7)
1448 MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], #4", -9, 12)
1449 MEM_TEST("ld2 {v18.h, v19.h}[6], [x5], x6", 9, 13)
1450
1451 MEM_TEST("ld2 {v18.b, v19.b}[0], [x5]", 17, 7)
1452 MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], #2", -9, 12)
1453 MEM_TEST("ld2 {v18.b, v19.b}[0], [x5], x6", 9, 13)
1454
1455 MEM_TEST("ld2 {v18.b, v19.b}[13], [x5]", 17, 7)
1456 MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], #2", -9, 12)
1457 MEM_TEST("ld2 {v18.b, v19.b}[13], [x5], x6", 9, 13)
1458
1459
1460 ////////////////////////////////////////////////////////////////
1461 printf("LD3/ST3 (single 3-elem struct to/from one lane of 3 regs\n");
1462
1463 MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5]", 17, 7)
1464 MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], #24", -9, 12)
1465 MEM_TEST("st3 {v17.d, v18.d, v19.d}[0], [x5], x6", 9, 13)
1466
1467 MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5]", 17, 7)
1468 MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], #24", -9, 12)
1469 MEM_TEST("st3 {v17.d, v18.d, v19.d}[1], [x5], x6", 9, 13)
1470
1471 MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5]", 17, 7)
1472 MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], #12", -9, 12)
1473 MEM_TEST("st3 {v17.s, v18.s, v19.s}[0], [x5], x6", 9, 13)
1474
1475 MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5]", 17, 7)
1476 MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], #12", -9, 12)
1477 MEM_TEST("st3 {v17.s, v18.s, v19.s}[3], [x5], x6", 9, 13)
1478
1479 MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5]", 17, 7)
1480 MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], #6", -9, 12)
1481 MEM_TEST("st3 {v17.h, v18.h, v19.h}[0], [x5], x6", 9, 13)
1482
1483 MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5]", 17, 7)
1484 MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], #6", -9, 12)
1485 MEM_TEST("st3 {v17.h, v18.h, v19.h}[6], [x5], x6", 9, 13)
1486
1487 MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5]", 17, 7)
1488 MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], #3", -9, 12)
1489 MEM_TEST("st3 {v17.b, v18.b, v19.b}[0], [x5], x6", 9, 13)
1490
1491 MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5]", 17, 7)
1492 MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], #3", -9, 12)
1493 MEM_TEST("st3 {v17.b, v18.b, v19.b}[13], [x5], x6", 9, 13)
1494
1495
1496 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5]", 17, 7)
1497 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], #24", -9, 12)
1498 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[0], [x5], x6", 9, 13)
1499
1500 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5]", 17, 7)
1501 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], #24", -9, 12)
1502 MEM_TEST("ld3 {v17.d, v18.d, v19.d}[1], [x5], x6", 9, 13)
1503
1504 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5]", 17, 7)
1505 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], #12", -9, 12)
1506 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[0], [x5], x6", 9, 13)
1507
1508 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5]", 17, 7)
1509 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], #12", -9, 12)
1510 MEM_TEST("ld3 {v17.s, v18.s, v19.s}[3], [x5], x6", 9, 13)
1511
1512 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5]", 17, 7)
1513 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], #6", -9, 12)
1514 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[0], [x5], x6", 9, 13)
1515
1516 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5]", 17, 7)
1517 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], #6", -9, 12)
1518 MEM_TEST("ld3 {v17.h, v18.h, v19.h}[6], [x5], x6", 9, 13)
1519
1520 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5]", 17, 7)
1521 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], #3", -9, 12)
1522 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[0], [x5], x6", 9, 13)
1523
1524 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5]", 17, 7)
1525 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], #3", -9, 12)
1526 MEM_TEST("ld3 {v17.b, v18.b, v19.b}[13], [x5], x6", 9, 13)
1527
1528
1529 ////////////////////////////////////////////////////////////////
1530 printf("LD4/ST4 (single 4-elem struct to/from one lane of 4 regs\n");
1531
1532 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]", 17, 7)
1533 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32", -9, 12)
1534 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6", 9, 13)
1535
1536 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]", 17, 7)
1537 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32", -9, 12)
1538 MEM_TEST("st4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6", 9, 13)
1539
1540 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]", 17, 7)
1541 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16", -9, 12)
1542 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6", 9, 13)
1543
1544 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]", 17, 7)
1545 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16", -9, 12)
1546 MEM_TEST("st4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6", 9, 13)
1547
1548 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]", 17, 7)
1549 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8", -9, 12)
1550 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6", 9, 13)
1551
1552 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]", 17, 7)
1553 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8", -9, 12)
1554 MEM_TEST("st4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6", 9, 13)
1555
1556 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]", 17, 7)
1557 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4", -9, 12)
1558 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6", 9, 13)
1559
1560 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]", 17, 7)
1561 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4", -9, 12)
1562 MEM_TEST("st4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6", 9, 13)
1563
1564
1565 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5]", 17, 7)
1566 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], #32", -9, 12)
1567 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[0], [x5], x6", 9, 13)
1568
1569 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5]", 17, 7)
1570 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], #32", -9, 12)
1571 MEM_TEST("ld4 {v17.d, v18.d, v19.d, v20.d}[1], [x5], x6", 9, 13)
1572
1573 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5]", 17, 7)
1574 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], #16", -9, 12)
1575 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[0], [x5], x6", 9, 13)
1576
1577 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5]", 17, 7)
1578 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], #16", -9, 12)
1579 MEM_TEST("ld4 {v17.s, v18.s, v19.s, v20.s}[3], [x5], x6", 9, 13)
1580
1581 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5]", 17, 7)
1582 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], #8", -9, 12)
1583 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[0], [x5], x6", 9, 13)
1584
1585 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5]", 17, 7)
1586 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], #8", -9, 12)
1587 MEM_TEST("ld4 {v17.h, v18.h, v19.h, v20.h}[6], [x5], x6", 9, 13)
1588
1589 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5]", 17, 7)
1590 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], #4", -9, 12)
1591 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[0], [x5], x6", 9, 13)
1592
1593 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5]", 17, 7)
1594 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], #4", -9, 12)
1595 MEM_TEST("ld4 {v17.b, v18.b, v19.b, v20.b}[13], [x5], x6", 9, 13)
1596
1597 ////////////////////////////////////////////////////////////////
1598 printf("PRFM (immediate)\n");
1599
1600 MEM_TEST("prfm pldl1keep, [x5, #40]", 12, -4);
1601 MEM_TEST("prfm pstl3strm, [x5, #56]", 12, -4);
1602
1603 } /* end of test_memory2() */
1604
1605 ////////////////////////////////////////////////////////////////
1606 ////////////////////////////////////////////////////////////////
1607 ////////////////////////////////////////////////////////////////
1608 ////////////////////////////////////////////////////////////////
1609 ////////////////////////////////////////////////////////////////
1610 ////////////////////////////////////////////////////////////////
1611
main(void)1612 int main ( void )
1613 {
1614 if (1) test_memory_old();
1615 if (1) test_memory_new();
1616 return 0;
1617 }
1618