1 // Copyright 2015, ARM Limited 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 28 // --------------------------------------------------------------------- 29 // This file is auto generated using tools/generate_simulator_traces.py. 30 // 31 // PLEASE DO NOT EDIT. 32 // --------------------------------------------------------------------- 33 34 #ifndef VIXL_SIM_FCMP_SZ_TRACE_A64_H_ 35 #define VIXL_SIM_FCMP_SZ_TRACE_A64_H_ 36 37 const uint8_t kExpected_fcmp_sz[] = { 38 0x6, 39 0x2, 40 0x2, 41 0x2, 42 0x2, 43 0x2, 44 0x2, 45 0x2, 46 0x2, 47 0x2, 48 0x3, 49 0x2, 50 0x3, 51 0x3, 52 0x3, 53 0x3, 54 0x2, 55 0x2, 56 0x2, 57 0x6, 58 0x8, 59 0x8, 60 0x8, 61 0x8, 62 0x8, 63 0x8, 64 0x8, 65 0x8, 66 0x8, 67 0x3, 68 0x8, 69 0x3, 70 0x3, 71 0x3, 72 0x3, 73 0x8, 74 0x8, 75 0x8, 76 }; 77 const unsigned kExpectedCount_fcmp_sz = 38; 78 79 #endif // VIXL_SIM_FCMP_SZ_TRACE_A64_H_ 80