1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_MSM_MDP_H_ 20 #define _UAPI_MSM_MDP_H_ 21 #include <linux/types.h> 22 #include <linux/fb.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define MSMFB_IOCTL_MAGIC 'm' 25 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 26 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 27 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 30 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 31 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 32 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 35 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 36 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) 37 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) 40 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 41 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) 42 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) 45 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 46 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) 47 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) 50 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 51 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 52 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) 55 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) 56 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 57 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 60 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) 61 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) 62 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 65 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 66 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 67 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 70 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) 71 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 72 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) 75 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 76 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) 77 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define FB_TYPE_3D_PANEL 0x10101010 80 #define MDP_IMGTYPE2_START 0x10000 81 #define MSMFB_DRIVER_VERSION 0xF9E8D701 82 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 85 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 86 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 87 #define IS_MDSS_MAJOR_MINOR_SAME(rev1,rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define MDSS_MDP_REV(major,minor,step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) 90 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) 91 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) 92 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) 95 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) 96 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) 97 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) 100 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) 101 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) 102 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) 105 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) 106 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) 107 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 enum { 110 NOTIFY_UPDATE_INIT, 111 NOTIFY_UPDATE_DEINIT, 112 NOTIFY_UPDATE_START, 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 NOTIFY_UPDATE_STOP, 115 NOTIFY_UPDATE_POWER_OFF, 116 }; 117 enum { 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 NOTIFY_TYPE_NO_UPDATE, 120 NOTIFY_TYPE_SUSPEND, 121 NOTIFY_TYPE_UPDATE, 122 NOTIFY_TYPE_BL_UPDATE, 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 125 }; 126 enum { 127 MDP_RGB_565, 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 MDP_XRGB_8888, 130 MDP_Y_CBCR_H2V2, 131 MDP_Y_CBCR_H2V2_ADRENO, 132 MDP_ARGB_8888, 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 MDP_RGB_888, 135 MDP_Y_CRCB_H2V2, 136 MDP_YCRYCB_H2V1, 137 MDP_CBYCRY_H2V1, 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 MDP_Y_CRCB_H2V1, 140 MDP_Y_CBCR_H2V1, 141 MDP_Y_CRCB_H1V2, 142 MDP_Y_CBCR_H1V2, 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 MDP_RGBA_8888, 145 MDP_BGRA_8888, 146 MDP_RGBX_8888, 147 MDP_Y_CRCB_H2V2_TILE, 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 MDP_Y_CBCR_H2V2_TILE, 150 MDP_Y_CR_CB_H2V2, 151 MDP_Y_CR_CB_GH2V2, 152 MDP_Y_CB_CR_H2V2, 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 MDP_Y_CRCB_H1V1, 155 MDP_Y_CBCR_H1V1, 156 MDP_YCRCB_H1V1, 157 MDP_YCBCR_H1V1, 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 MDP_BGR_565, 160 MDP_BGR_888, 161 MDP_Y_CBCR_H2V2_VENUS, 162 MDP_BGRX_8888, 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 MDP_RGBA_8888_TILE, 165 MDP_ARGB_8888_TILE, 166 MDP_ABGR_8888_TILE, 167 MDP_BGRA_8888_TILE, 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 MDP_RGBX_8888_TILE, 170 MDP_XRGB_8888_TILE, 171 MDP_XBGR_8888_TILE, 172 MDP_BGRX_8888_TILE, 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 MDP_YCBYCR_H2V1, 175 MDP_RGB_565_TILE, 176 MDP_BGR_565_TILE, 177 MDP_ARGB_1555, 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 MDP_RGBA_5551, 180 MDP_ARGB_4444, 181 MDP_RGBA_4444, 182 MDP_RGB_565_UBWC, 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 MDP_RGBA_8888_UBWC, 185 MDP_Y_CBCR_H2V2_UBWC, 186 MDP_IMGTYPE_LIMIT, 187 MDP_RGB_BORDERFILL, 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 MDP_FB_FORMAT = MDP_IMGTYPE2_START, 190 MDP_IMGTYPE_LIMIT2 191 }; 192 enum { 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 PMEM_IMG, 195 FB_IMG, 196 }; 197 enum { 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 HSIC_HUE = 0, 200 HSIC_SAT, 201 HSIC_INT, 202 HSIC_CON, 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 NUM_HSIC_PARAM, 205 }; 206 #define MDSS_MDP_ROT_ONLY 0x80 207 #define MDSS_MDP_RIGHT_MIXER 0x100 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 #define MDSS_MDP_DUAL_PIPE 0x200 210 #define MDP_ROT_NOP 0 211 #define MDP_FLIP_LR 0x1 212 #define MDP_FLIP_UD 0x2 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 #define MDP_ROT_90 0x4 215 #define MDP_ROT_180 (MDP_FLIP_UD | MDP_FLIP_LR) 216 #define MDP_ROT_270 (MDP_ROT_90 | MDP_FLIP_UD | MDP_FLIP_LR) 217 #define MDP_DITHER 0x8 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 #define MDP_BLUR 0x10 220 #define MDP_BLEND_FG_PREMULT 0x20000 221 #define MDP_IS_FG 0x40000 222 #define MDP_SOLID_FILL 0x00000020 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define MDP_VPU_PIPE 0x00000040 225 #define MDP_DEINTERLACE 0x80000000 226 #define MDP_SHARPENING 0x40000000 227 #define MDP_NO_DMA_BARRIER_START 0x20000000 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define MDP_NO_DMA_BARRIER_END 0x10000000 230 #define MDP_NO_BLIT 0x08000000 231 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 232 #define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define MDP_BLIT_SRC_GEM 0x04000000 235 #define MDP_BLIT_DST_GEM 0x02000000 236 #define MDP_BLIT_NON_CACHED 0x01000000 237 #define MDP_OV_PIPE_SHARE 0x00800000 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 #define MDP_DEINTERLACE_ODD 0x00400000 240 #define MDP_OV_PLAY_NOWAIT 0x00200000 241 #define MDP_SOURCE_ROTATED_90 0x00100000 242 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 #define MDP_BACKEND_COMPOSITION 0x00040000 245 #define MDP_BORDERFILL_SUPPORTED 0x00010000 246 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 247 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 250 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 251 #define MDP_BWC_EN 0x00000400 252 #define MDP_DECIMATION_EN 0x00000800 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 #define MDP_SMP_FORCE_ALLOC 0x00200000 255 #define MDP_TRANSP_NOP 0xffffffff 256 #define MDP_ALPHA_NOP 0xff 257 #define MDP_SMART_BLIT 0xC0000000 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 260 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 261 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 262 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 265 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 266 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 267 struct mdp_rect { 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 uint32_t x; 270 uint32_t y; 271 uint32_t w; 272 uint32_t h; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 }; 275 struct mdp_img { 276 uint32_t width; 277 uint32_t height; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 uint32_t format; 280 uint32_t offset; 281 int memory_id; 282 uint32_t priv; 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 }; 285 #define MDP_CCS_RGB2YUV 0 286 #define MDP_CCS_YUV2RGB 1 287 #define MDP_CCS_SIZE 9 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define MDP_BV_SIZE 3 290 struct mdp_ccs { 291 int direction; 292 uint16_t ccs[MDP_CCS_SIZE]; 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 uint16_t bv[MDP_BV_SIZE]; 295 }; 296 struct mdp_csc { 297 int id; 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 uint32_t csc_mv[9]; 300 uint32_t csc_pre_bv[3]; 301 uint32_t csc_post_bv[3]; 302 uint32_t csc_pre_lv[6]; 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 uint32_t csc_post_lv[6]; 305 }; 306 #define MDP_BLIT_REQ_VERSION 2 307 struct color { 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 uint32_t r; 310 uint32_t g; 311 uint32_t b; 312 uint32_t alpha; 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 }; 315 struct mdp_blit_req { 316 struct mdp_img src; 317 struct mdp_img dst; 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 struct mdp_rect src_rect; 320 struct mdp_rect dst_rect; 321 struct color const_color; 322 uint32_t alpha; 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 uint32_t transp_mask; 325 uint32_t flags; 326 int sharpening_strength; 327 uint8_t color_space; 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 uint32_t fps; 330 }; 331 struct mdp_blit_req_list { 332 uint32_t count; 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 struct mdp_blit_req req[]; 335 }; 336 #define MSMFB_DATA_VERSION 2 337 struct msmfb_data { 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 uint32_t offset; 340 int memory_id; 341 int id; 342 uint32_t flags; 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 uint32_t priv; 345 uint32_t iova; 346 }; 347 #define MSMFB_NEW_REQUEST - 1 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 struct msmfb_overlay_data { 350 uint32_t id; 351 struct msmfb_data data; 352 uint32_t version_key; 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 struct msmfb_data plane1_data; 355 struct msmfb_data plane2_data; 356 struct msmfb_data dst_data; 357 }; 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 struct msmfb_img { 360 uint32_t width; 361 uint32_t height; 362 uint32_t format; 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 }; 365 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 366 struct msmfb_writeback_data { 367 struct msmfb_data buf_info; 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 struct msmfb_img img; 370 }; 371 #define MDP_PP_OPS_ENABLE 0x1 372 #define MDP_PP_OPS_READ 0x2 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 #define MDP_PP_OPS_WRITE 0x4 375 #define MDP_PP_OPS_DISABLE 0x8 376 #define MDP_PP_IGC_FLAG_ROM0 0x10 377 #define MDP_PP_IGC_FLAG_ROM1 0x20 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 #define MDP_PP_PA_HUE_ENABLE 0x10 380 #define MDP_PP_PA_SAT_ENABLE 0x20 381 #define MDP_PP_PA_VAL_ENABLE 0x40 382 #define MDP_PP_PA_CONT_ENABLE 0x80 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 385 #define MDP_PP_PA_SKIN_ENABLE 0x200 386 #define MDP_PP_PA_SKY_ENABLE 0x400 387 #define MDP_PP_PA_FOL_ENABLE 0x800 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 #define MDP_PP_PA_HUE_MASK 0x1000 390 #define MDP_PP_PA_SAT_MASK 0x2000 391 #define MDP_PP_PA_VAL_MASK 0x4000 392 #define MDP_PP_PA_CONT_MASK 0x8000 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 395 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 396 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 397 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 400 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 401 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 402 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 #define MDSS_PP_DSPP_CFG 0x000 405 #define MDSS_PP_SSPP_CFG 0x100 406 #define MDSS_PP_LM_CFG 0x200 407 #define MDSS_PP_WB_CFG 0x300 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 #define MDSS_PP_ARG_MASK 0x3C00 410 #define MDSS_PP_ARG_NUM 4 411 #define MDSS_PP_ARG_SHIFT 10 412 #define MDSS_PP_LOCATION_MASK 0x0300 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 #define MDSS_PP_LOGICAL_MASK 0x00FF 415 #define MDSS_PP_ADD_ARG(var,arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 416 #define PP_ARG(x,var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 417 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 420 struct mdp_qseed_cfg { 421 uint32_t table_num; 422 uint32_t ops; 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 uint32_t len; 425 uint32_t * data; 426 }; 427 struct mdp_sharp_cfg { 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 uint32_t flags; 430 uint32_t strength; 431 uint32_t edge_thr; 432 uint32_t smooth_thr; 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 uint32_t noise_thr; 435 }; 436 struct mdp_qseed_cfg_data { 437 uint32_t block; 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 struct mdp_qseed_cfg qseed_data; 440 }; 441 #define MDP_OVERLAY_PP_CSC_CFG 0x1 442 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 #define MDP_OVERLAY_PP_PA_CFG 0x4 445 #define MDP_OVERLAY_PP_IGC_CFG 0x8 446 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 447 #define MDP_OVERLAY_PP_HIST_CFG 0x20 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 450 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 451 #define MDP_CSC_FLAG_ENABLE 0x1 452 #define MDP_CSC_FLAG_YUV_IN 0x2 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 #define MDP_CSC_FLAG_YUV_OUT 0x4 455 struct mdp_csc_cfg { 456 uint32_t flags; 457 uint32_t csc_mv[9]; 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 uint32_t csc_pre_bv[3]; 460 uint32_t csc_post_bv[3]; 461 uint32_t csc_pre_lv[6]; 462 uint32_t csc_post_lv[6]; 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 }; 465 struct mdp_csc_cfg_data { 466 uint32_t block; 467 struct mdp_csc_cfg csc_data; 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 }; 470 struct mdp_pa_cfg { 471 uint32_t flags; 472 uint32_t hue_adj; 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 uint32_t sat_adj; 475 uint32_t val_adj; 476 uint32_t cont_adj; 477 }; 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 struct mdp_pa_mem_col_cfg { 480 uint32_t color_adjust_p0; 481 uint32_t color_adjust_p1; 482 uint32_t hue_region; 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 uint32_t sat_region; 485 uint32_t val_region; 486 }; 487 #define MDP_SIX_ZONE_LUT_SIZE 384 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 struct mdp_pa_v2_data { 490 uint32_t flags; 491 uint32_t global_hue_adj; 492 uint32_t global_sat_adj; 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 uint32_t global_val_adj; 495 uint32_t global_cont_adj; 496 struct mdp_pa_mem_col_cfg skin_cfg; 497 struct mdp_pa_mem_col_cfg sky_cfg; 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 struct mdp_pa_mem_col_cfg fol_cfg; 500 uint32_t six_zone_len; 501 uint32_t six_zone_thresh; 502 uint32_t * six_zone_curve_p0; 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 uint32_t * six_zone_curve_p1; 505 }; 506 struct mdp_igc_lut_data { 507 uint32_t block; 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 uint32_t len, ops; 510 uint32_t * c0_c1_data; 511 uint32_t * c2_data; 512 }; 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 struct mdp_histogram_cfg { 515 uint32_t ops; 516 uint32_t block; 517 uint8_t frame_cnt; 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 uint8_t bit_mask; 520 uint16_t num_bins; 521 }; 522 struct mdp_hist_lut_data { 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 uint32_t block; 525 uint32_t ops; 526 uint32_t len; 527 uint32_t * data; 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 }; 530 struct mdp_overlay_pp_params { 531 uint32_t config_ops; 532 struct mdp_csc_cfg csc_cfg; 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 struct mdp_qseed_cfg qseed_cfg[2]; 535 struct mdp_pa_cfg pa_cfg; 536 struct mdp_pa_v2_data pa_v2_cfg; 537 struct mdp_igc_lut_data igc_cfg; 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 struct mdp_sharp_cfg sharp_cfg; 540 struct mdp_histogram_cfg hist_cfg; 541 struct mdp_hist_lut_data hist_lut_cfg; 542 }; 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 enum mdss_mdp_blend_op { 545 BLEND_OP_NOT_DEFINED = 0, 546 BLEND_OP_OPAQUE, 547 BLEND_OP_PREMULTIPLIED, 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 BLEND_OP_COVERAGE, 550 BLEND_OP_MAX, 551 }; 552 #define DECIMATED_DIMENSION(dim,deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 #define MAX_PLANES 4 555 struct mdp_scale_data { 556 uint8_t enable_pxl_ext; 557 int init_phase_x[MAX_PLANES]; 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 int phase_step_x[MAX_PLANES]; 560 int init_phase_y[MAX_PLANES]; 561 int phase_step_y[MAX_PLANES]; 562 int num_ext_pxls_left[MAX_PLANES]; 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 int num_ext_pxls_right[MAX_PLANES]; 565 int num_ext_pxls_top[MAX_PLANES]; 566 int num_ext_pxls_btm[MAX_PLANES]; 567 int left_ftch[MAX_PLANES]; 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 int left_rpt[MAX_PLANES]; 570 int right_ftch[MAX_PLANES]; 571 int right_rpt[MAX_PLANES]; 572 int top_rpt[MAX_PLANES]; 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 int btm_rpt[MAX_PLANES]; 575 int top_ftch[MAX_PLANES]; 576 int btm_ftch[MAX_PLANES]; 577 uint32_t roi_w[MAX_PLANES]; 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 }; 580 enum mdp_overlay_pipe_type { 581 PIPE_TYPE_AUTO = 0, 582 PIPE_TYPE_VIG, 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 PIPE_TYPE_RGB, 585 PIPE_TYPE_DMA, 586 PIPE_TYPE_CURSOR, 587 PIPE_TYPE_MAX, 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 }; 590 struct mdp_overlay { 591 struct msmfb_img src; 592 struct mdp_rect src_rect; 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 struct mdp_rect dst_rect; 595 uint32_t z_order; 596 uint32_t is_fg; 597 uint32_t alpha; 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 uint32_t blend_op; 600 uint32_t transp_mask; 601 uint32_t flags; 602 uint32_t pipe_type; 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 uint32_t id; 605 uint8_t priority; 606 uint32_t user_data[6]; 607 uint32_t bg_color; 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 uint8_t horz_deci; 610 uint8_t vert_deci; 611 struct mdp_overlay_pp_params overlay_pp_cfg; 612 struct mdp_scale_data scale; 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 uint8_t color_space; 615 }; 616 struct msmfb_overlay_3d { 617 uint32_t is_3d; 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 uint32_t width; 620 uint32_t height; 621 }; 622 struct msmfb_overlay_blt { 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 uint32_t enable; 625 uint32_t offset; 626 uint32_t width; 627 uint32_t height; 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 uint32_t bpp; 630 }; 631 struct mdp_histogram { 632 uint32_t frame_cnt; 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 uint32_t bin_cnt; 635 uint32_t * r; 636 uint32_t * g; 637 uint32_t * b; 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 }; 640 #define MISR_CRC_BATCH_SIZE 32 641 enum { 642 DISPLAY_MISR_EDP, 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 DISPLAY_MISR_DSI0, 645 DISPLAY_MISR_DSI1, 646 DISPLAY_MISR_HDMI, 647 DISPLAY_MISR_LCDC, 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 DISPLAY_MISR_MDP, 650 DISPLAY_MISR_ATV, 651 DISPLAY_MISR_DSI_CMD, 652 DISPLAY_MISR_MAX 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 }; 655 enum { 656 MISR_OP_NONE, 657 MISR_OP_SFM, 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 MISR_OP_MFM, 660 MISR_OP_BM, 661 MISR_OP_MAX 662 }; 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 struct mdp_misr { 665 uint32_t block_id; 666 uint32_t frame_count; 667 uint32_t crc_op_mode; 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 670 }; 671 enum { 672 MDP_BLOCK_RESERVED = 0, 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 MDP_BLOCK_OVERLAY_0, 675 MDP_BLOCK_OVERLAY_1, 676 MDP_BLOCK_VG_1, 677 MDP_BLOCK_VG_2, 678 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 MDP_BLOCK_RGB_1, 680 MDP_BLOCK_RGB_2, 681 MDP_BLOCK_DMA_P, 682 MDP_BLOCK_DMA_S, 683 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 MDP_BLOCK_DMA_E, 685 MDP_BLOCK_OVERLAY_2, 686 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 687 MDP_LOGICAL_BLOCK_DISP_1, 688 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 MDP_LOGICAL_BLOCK_DISP_2, 690 MDP_BLOCK_MAX, 691 }; 692 struct mdp_histogram_start_req { 693 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 uint32_t block; 695 uint8_t frame_cnt; 696 uint8_t bit_mask; 697 uint16_t num_bins; 698 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 }; 700 struct mdp_histogram_data { 701 uint32_t block; 702 uint32_t bin_cnt; 703 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 uint32_t * c0; 705 uint32_t * c1; 706 uint32_t * c2; 707 uint32_t * extra_info; 708 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 }; 710 struct mdp_pcc_coeff { 711 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 712 }; 713 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 struct mdp_pcc_cfg_data { 715 uint32_t block; 716 uint32_t ops; 717 struct mdp_pcc_coeff r, g, b; 718 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 }; 720 #define MDP_GAMUT_TABLE_NUM 8 721 enum { 722 mdp_lut_igc, 723 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724 mdp_lut_pgc, 725 mdp_lut_hist, 726 mdp_lut_rgb, 727 mdp_lut_max, 728 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 }; 730 struct mdp_ar_gc_lut_data { 731 uint32_t x_start; 732 uint32_t slope; 733 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734 uint32_t offset; 735 }; 736 struct mdp_pgc_lut_data { 737 uint32_t block; 738 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739 uint32_t flags; 740 uint8_t num_r_stages; 741 uint8_t num_g_stages; 742 uint8_t num_b_stages; 743 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 struct mdp_ar_gc_lut_data * r_data; 745 struct mdp_ar_gc_lut_data * g_data; 746 struct mdp_ar_gc_lut_data * b_data; 747 }; 748 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749 struct mdp_rgb_lut_data { 750 uint32_t flags; 751 uint32_t lut_type; 752 struct fb_cmap cmap; 753 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754 }; 755 enum { 756 mdp_rgb_lut_gc, 757 mdp_rgb_lut_hist, 758 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759 }; 760 struct mdp_lut_cfg_data { 761 uint32_t lut_type; 762 union { 763 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764 struct mdp_igc_lut_data igc_lut_data; 765 struct mdp_pgc_lut_data pgc_lut_data; 766 struct mdp_hist_lut_data hist_lut_data; 767 struct mdp_rgb_lut_data rgb_lut_data; 768 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769 } data; 770 }; 771 struct mdp_bl_scale_data { 772 uint32_t min_lvl; 773 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774 uint32_t scale; 775 }; 776 struct mdp_pa_cfg_data { 777 uint32_t block; 778 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 struct mdp_pa_cfg pa_data; 780 }; 781 struct mdp_pa_v2_cfg_data { 782 uint32_t block; 783 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784 struct mdp_pa_v2_data pa_v2_data; 785 }; 786 struct mdp_dither_cfg_data { 787 uint32_t block; 788 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789 uint32_t flags; 790 uint32_t g_y_depth; 791 uint32_t r_cr_depth; 792 uint32_t b_cb_depth; 793 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794 }; 795 struct mdp_gamut_cfg_data { 796 uint32_t block; 797 uint32_t flags; 798 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799 uint32_t gamut_first; 800 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 801 uint16_t * r_tbl[MDP_GAMUT_TABLE_NUM]; 802 uint16_t * g_tbl[MDP_GAMUT_TABLE_NUM]; 803 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804 uint16_t * b_tbl[MDP_GAMUT_TABLE_NUM]; 805 }; 806 struct mdp_calib_config_data { 807 uint32_t ops; 808 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809 uint32_t addr; 810 uint32_t data; 811 }; 812 struct mdp_calib_config_buffer { 813 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814 uint32_t ops; 815 uint32_t size; 816 uint32_t * buffer; 817 }; 818 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819 struct mdp_calib_dcm_state { 820 uint32_t ops; 821 uint32_t dcm_state; 822 }; 823 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824 struct mdp_pp_init_data { 825 uint32_t init_request; 826 }; 827 enum { 828 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829 MDP_PP_DISABLE, 830 MDP_PP_ENABLE, 831 }; 832 enum { 833 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834 DCM_UNINIT, 835 DCM_UNBLANK, 836 DCM_ENTER, 837 DCM_EXIT, 838 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839 DCM_BLANK, 840 DTM_ENTER, 841 DTM_EXIT, 842 }; 843 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 845 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 846 #define MDSS_PP_SPLIT_MASK 0x30000000 847 #define MDSS_MAX_BL_BRIGHTNESS 255 848 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849 #define AD_BL_LIN_LEN 256 850 #define AD_BL_ATT_LUT_LEN 33 851 #define MDSS_AD_MODE_AUTO_BL 0x0 852 #define MDSS_AD_MODE_AUTO_STR 0x1 853 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854 #define MDSS_AD_MODE_TARG_STR 0x3 855 #define MDSS_AD_MODE_MAN_STR 0x7 856 #define MDSS_AD_MODE_CALIB 0xF 857 #define MDP_PP_AD_INIT 0x10 858 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859 #define MDP_PP_AD_CFG 0x20 860 struct mdss_ad_init { 861 uint32_t asym_lut[33]; 862 uint32_t color_corr_lut[33]; 863 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864 uint8_t i_control[2]; 865 uint16_t black_lvl; 866 uint16_t white_lvl; 867 uint8_t var; 868 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869 uint8_t limit_ampl; 870 uint8_t i_dither; 871 uint8_t slope_max; 872 uint8_t slope_min; 873 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874 uint8_t dither_ctl; 875 uint8_t format; 876 uint8_t auto_size; 877 uint16_t frame_w; 878 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879 uint16_t frame_h; 880 uint8_t logo_v; 881 uint8_t logo_h; 882 uint32_t alpha; 883 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884 uint32_t alpha_base; 885 uint32_t bl_lin_len; 886 uint32_t bl_att_len; 887 uint32_t * bl_lin; 888 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889 uint32_t * bl_lin_inv; 890 uint32_t * bl_att_lut; 891 }; 892 #define MDSS_AD_BL_CTRL_MODE_EN 1 893 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894 #define MDSS_AD_BL_CTRL_MODE_DIS 0 895 struct mdss_ad_cfg { 896 uint32_t mode; 897 uint32_t al_calib_lut[33]; 898 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899 uint16_t backlight_min; 900 uint16_t backlight_max; 901 uint16_t backlight_scale; 902 uint16_t amb_light_min; 903 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904 uint16_t filter[2]; 905 uint16_t calib[4]; 906 uint8_t strength_limit; 907 uint8_t t_filter_recursion; 908 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909 uint16_t stab_itr; 910 uint32_t bl_ctrl_mode; 911 }; 912 struct mdss_ad_init_cfg { 913 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914 uint32_t ops; 915 union { 916 struct mdss_ad_init init; 917 struct mdss_ad_cfg cfg; 918 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919 } params; 920 }; 921 struct mdss_ad_input { 922 uint32_t mode; 923 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924 union { 925 uint32_t amb_light; 926 uint32_t strength; 927 uint32_t calib_bl; 928 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929 } in; 930 uint32_t output; 931 }; 932 #define MDSS_CALIB_MODE_BL 0x1 933 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934 struct mdss_calib_cfg { 935 uint32_t ops; 936 uint32_t calib_mask; 937 }; 938 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939 enum { 940 mdp_op_pcc_cfg, 941 mdp_op_csc_cfg, 942 mdp_op_lut_cfg, 943 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944 mdp_op_qseed_cfg, 945 mdp_bl_scale_cfg, 946 mdp_op_pa_cfg, 947 mdp_op_pa_v2_cfg, 948 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949 mdp_op_dither_cfg, 950 mdp_op_gamut_cfg, 951 mdp_op_calib_cfg, 952 mdp_op_ad_cfg, 953 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 954 mdp_op_ad_input, 955 mdp_op_calib_mode, 956 mdp_op_calib_buffer, 957 mdp_op_calib_dcm_state, 958 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 959 mdp_op_max, 960 mdp_op_pp_init_cfg, 961 }; 962 enum { 963 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 964 WB_FORMAT_NV12, 965 WB_FORMAT_RGB_565, 966 WB_FORMAT_RGB_888, 967 WB_FORMAT_xRGB_8888, 968 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 969 WB_FORMAT_ARGB_8888, 970 WB_FORMAT_BGRA_8888, 971 WB_FORMAT_BGRX_8888, 972 WB_FORMAT_ARGB_8888_INPUT_ALPHA 973 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 974 }; 975 struct msmfb_mdp_pp { 976 uint32_t op; 977 union { 978 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 979 struct mdp_pcc_cfg_data pcc_cfg_data; 980 struct mdp_csc_cfg_data csc_cfg_data; 981 struct mdp_lut_cfg_data lut_cfg_data; 982 struct mdp_qseed_cfg_data qseed_cfg_data; 983 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 984 struct mdp_bl_scale_data bl_scale_data; 985 struct mdp_pa_cfg_data pa_cfg_data; 986 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 987 struct mdp_dither_cfg_data dither_cfg_data; 988 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 989 struct mdp_gamut_cfg_data gamut_cfg_data; 990 struct mdp_calib_config_data calib_cfg; 991 struct mdss_ad_init_cfg ad_init_cfg; 992 struct mdss_calib_cfg mdss_calib_cfg; 993 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 994 struct mdss_ad_input ad_input; 995 struct mdp_calib_config_buffer calib_buffer; 996 struct mdp_calib_dcm_state calib_dcm; 997 struct mdp_pp_init_data init_data; 998 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 999 } data; 1000 }; 1001 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 1002 enum { 1003 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1004 metadata_op_none, 1005 metadata_op_base_blend, 1006 metadata_op_frame_rate, 1007 metadata_op_vic, 1008 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1009 metadata_op_wb_format, 1010 metadata_op_wb_secure, 1011 metadata_op_get_caps, 1012 metadata_op_crc, 1013 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1014 metadata_op_get_ion_fd, 1015 metadata_op_max 1016 }; 1017 struct mdp_blend_cfg { 1018 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1019 uint32_t is_premultiplied; 1020 }; 1021 struct mdp_mixer_cfg { 1022 uint32_t writeback_format; 1023 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1024 uint32_t alpha; 1025 }; 1026 struct mdss_hw_caps { 1027 uint32_t mdp_rev; 1028 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1029 uint8_t rgb_pipes; 1030 uint8_t vig_pipes; 1031 uint8_t dma_pipes; 1032 uint8_t max_smp_cnt; 1033 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1034 uint8_t smp_per_pipe; 1035 uint32_t features; 1036 }; 1037 struct msmfb_metadata { 1038 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1039 uint32_t op; 1040 uint32_t flags; 1041 union { 1042 struct mdp_misr misr_request; 1043 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1044 struct mdp_blend_cfg blend_cfg; 1045 struct mdp_mixer_cfg mixer_cfg; 1046 uint32_t panel_frame_rate; 1047 uint32_t video_info_code; 1048 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1049 struct mdss_hw_caps caps; 1050 uint8_t secure_en; 1051 int fbmem_ionfd; 1052 } data; 1053 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1054 }; 1055 #define MDP_MAX_FENCE_FD 32 1056 #define MDP_BUF_SYNC_FLAG_WAIT 1 1057 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1058 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1059 struct mdp_buf_sync { 1060 uint32_t flags; 1061 uint32_t acq_fen_fd_cnt; 1062 uint32_t session_id; 1063 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1064 int * acq_fen_fd; 1065 int * rel_fen_fd; 1066 int * retire_fen_fd; 1067 }; 1068 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1069 struct mdp_async_blit_req_list { 1070 struct mdp_buf_sync sync; 1071 uint32_t count; 1072 struct mdp_blit_req req[]; 1073 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1074 }; 1075 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1076 struct mdp_display_commit { 1077 uint32_t flags; 1078 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1079 uint32_t wait_for_finish; 1080 struct fb_var_screeninfo var; 1081 struct mdp_rect l_roi; 1082 struct mdp_rect r_roi; 1083 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1084 }; 1085 struct mdp_overlay_list { 1086 uint32_t num_overlays; 1087 struct mdp_overlay * * overlay_list; 1088 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1089 uint32_t flags; 1090 uint32_t processed_overlays; 1091 }; 1092 struct mdp_page_protection { 1093 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1094 uint32_t page_protection; 1095 }; 1096 struct mdp_mixer_info { 1097 int pndx; 1098 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1099 int pnum; 1100 int ptype; 1101 int mixer_num; 1102 int z_order; 1103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1104 }; 1105 #define MAX_PIPE_PER_MIXER 7 1106 struct msmfb_mixer_info_req { 1107 int mixer_num; 1108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1109 int cnt; 1110 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1111 }; 1112 enum { 1113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1114 DISPLAY_SUBSYSTEM_ID, 1115 ROTATOR_SUBSYSTEM_ID, 1116 }; 1117 enum { 1118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1119 MDP_IOMMU_DOMAIN_CP, 1120 MDP_IOMMU_DOMAIN_NS, 1121 }; 1122 enum { 1123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1124 MDP_WRITEBACK_MIRROR_OFF, 1125 MDP_WRITEBACK_MIRROR_ON, 1126 MDP_WRITEBACK_MIRROR_PAUSE, 1127 MDP_WRITEBACK_MIRROR_RESUME, 1128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1129 }; 1130 enum { 1131 MDP_CSC_ITU_R_601, 1132 MDP_CSC_ITU_R_601_FR, 1133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 1134 MDP_CSC_ITU_R_709, 1135 }; 1136 #endif 1137 1138