Lines Matching refs:tr1
1339 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
1341 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
1343 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> {
1351 SDPatternOperator operator_cc, TypedReg tr1,
1354 def "" : UnaryVRRa<mnemonic, opcode, operator, tr1, tr2, type, 0, modifier>;
1356 def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 0,
1591 TypedReg tr1, TypedReg tr2, bits<4> type>
1592 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
1594 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1600 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
1601 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
1603 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1617 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
1619 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1621 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1631 SDPatternOperator operator_cc, TypedReg tr1,
1634 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, modifier>;
1636 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1641 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
1643 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
1645 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1654 SDPatternOperator operator_cc, TypedReg tr1,
1657 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, modifier>;
1659 def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1670 TypedReg tr1, TypedReg tr2, bits<4> type>
1671 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
1673 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3),
1904 TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index>
1905 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
1907 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
1914 TypedReg tr1, TypedReg tr2, bits<4> type>
1915 : InstVRId<opcode, (outs tr1.op:$V1),
1918 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1925 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
1926 : InstVRRa<opcode, (outs tr1.op:$V1),
1929 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1937 TypedReg tr1, TypedReg tr2, bits<4> type,
1939 : InstVRRb<opcode, (outs tr1.op:$V1),
1942 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1951 SDPatternOperator operator_cc, TypedReg tr1,
1953 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
1956 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
1959 def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
1962 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
1967 TypedReg tr1, TypedReg tr2>
1968 : InstVRRc<opcode, (outs tr1.op:$V1),
1971 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1979 TypedReg tr1, TypedReg tr2, bits<4> type = 0>
1980 : InstVRRd<opcode, (outs tr1.op:$V1),
1981 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
1983 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1985 (tr1.vt tr1.op:$V4))))]> {
1991 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0>
1992 : InstVRRe<opcode, (outs tr1.op:$V1),
1993 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
1995 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
1997 (tr1.vt tr1.op:$V4))))]> {
2003 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
2004 : InstVRSb<opcode, (outs tr1.op:$V1),
2007 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2027 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index>
2028 : InstVRX<opcode, (outs tr1.op:$V1),
2031 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2041 TypedReg tr1, TypedReg tr2, bits<4> type>
2042 : InstVRId<opcode, (outs tr1.op:$V1),
2045 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src),
2055 SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
2057 : InstVRRd<opcode, (outs tr1.op:$V1),
2060 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2),
2070 SDPatternOperator operator_cc, TypedReg tr1,
2072 def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type,
2075 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
2078 def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type,
2081 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
2409 class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
2410 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
2411 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>;