1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Basic SystemZ instruction definition 12//===----------------------------------------------------------------------===// 13 14class InstSystemZ<int size, dag outs, dag ins, string asmstr, 15 list<dag> pattern> : Instruction { 16 let Namespace = "SystemZ"; 17 18 dag OutOperandList = outs; 19 dag InOperandList = ins; 20 let Size = size; 21 let Pattern = pattern; 22 let AsmString = asmstr; 23 24 // Some instructions come in pairs, one having a 12-bit displacement 25 // and the other having a 20-bit displacement. Both instructions in 26 // the pair have the same DispKey and their DispSizes are "12" and "20" 27 // respectively. 28 string DispKey = ""; 29 string DispSize = "none"; 30 31 // Many register-based <INSN>R instructions have a memory-based <INSN> 32 // counterpart. OpKey uniquely identifies <INSN>, while OpType is 33 // "reg" for <INSN>R and "mem" for <INSN>. 34 string OpKey = ""; 35 string OpType = "none"; 36 37 // Many distinct-operands instructions have older 2-operand equivalents. 38 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs, 39 // with NumOpsValue being "2" or "3" as appropriate. 40 string NumOpsKey = ""; 41 string NumOpsValue = "none"; 42 43 // True if this instruction is a simple D(X,B) load of a register 44 // (with no sign or zero extension). 45 bit SimpleBDXLoad = 0; 46 47 // True if this instruction is a simple D(X,B) store of a register 48 // (with no truncation). 49 bit SimpleBDXStore = 0; 50 51 // True if this instruction has a 20-bit displacement field. 52 bit Has20BitOffset = 0; 53 54 // True if addresses in this instruction have an index register. 55 bit HasIndex = 0; 56 57 // True if this is a 128-bit pseudo instruction that combines two 64-bit 58 // operations. 59 bit Is128Bit = 0; 60 61 // The access size of all memory operands in bytes, or 0 if not known. 62 bits<5> AccessBytes = 0; 63 64 // If the instruction sets CC to a useful value, this gives the mask 65 // of all possible CC results. The mask has the same form as 66 // SystemZ::CCMASK_*. 67 bits<4> CCValues = 0; 68 69 // The subset of CCValues that have the same meaning as they would after 70 // a comparison of the first operand against zero. 71 bits<4> CompareZeroCCMask = 0; 72 73 // True if the instruction is conditional and if the CC mask operand 74 // comes first (as for BRC, etc.). 75 bit CCMaskFirst = 0; 76 77 // Similar, but true if the CC mask operand comes last (as for LOC, etc.). 78 bit CCMaskLast = 0; 79 80 // True if the instruction is the "logical" rather than "arithmetic" form, 81 // in cases where a distinction exists. 82 bit IsLogical = 0; 83 84 let TSFlags{0} = SimpleBDXLoad; 85 let TSFlags{1} = SimpleBDXStore; 86 let TSFlags{2} = Has20BitOffset; 87 let TSFlags{3} = HasIndex; 88 let TSFlags{4} = Is128Bit; 89 let TSFlags{9-5} = AccessBytes; 90 let TSFlags{13-10} = CCValues; 91 let TSFlags{17-14} = CompareZeroCCMask; 92 let TSFlags{18} = CCMaskFirst; 93 let TSFlags{19} = CCMaskLast; 94 let TSFlags{20} = IsLogical; 95} 96 97//===----------------------------------------------------------------------===// 98// Mappings between instructions 99//===----------------------------------------------------------------------===// 100 101// Return the version of an instruction that has an unsigned 12-bit 102// displacement. 103def getDisp12Opcode : InstrMapping { 104 let FilterClass = "InstSystemZ"; 105 let RowFields = ["DispKey"]; 106 let ColFields = ["DispSize"]; 107 let KeyCol = ["20"]; 108 let ValueCols = [["12"]]; 109} 110 111// Return the version of an instruction that has a signed 20-bit displacement. 112def getDisp20Opcode : InstrMapping { 113 let FilterClass = "InstSystemZ"; 114 let RowFields = ["DispKey"]; 115 let ColFields = ["DispSize"]; 116 let KeyCol = ["12"]; 117 let ValueCols = [["20"]]; 118} 119 120// Return the memory form of a register instruction. 121def getMemOpcode : InstrMapping { 122 let FilterClass = "InstSystemZ"; 123 let RowFields = ["OpKey"]; 124 let ColFields = ["OpType"]; 125 let KeyCol = ["reg"]; 126 let ValueCols = [["mem"]]; 127} 128 129// Return the 3-operand form of a 2-operand instruction. 130def getThreeOperandOpcode : InstrMapping { 131 let FilterClass = "InstSystemZ"; 132 let RowFields = ["NumOpsKey"]; 133 let ColFields = ["NumOpsValue"]; 134 let KeyCol = ["2"]; 135 let ValueCols = [["3"]]; 136} 137 138//===----------------------------------------------------------------------===// 139// Instruction formats 140//===----------------------------------------------------------------------===// 141// 142// Formats are specified using operand field declarations of the form: 143// 144// bits<4> Rn : register input or output for operand n 145// bits<5> Vn : vector register input or output for operand n 146// bits<m> In : immediate value of width m for operand n 147// bits<4> BDn : address operand n, which has a base and a displacement 148// bits<m> XBDn : address operand n, which has an index, a base and a 149// displacement 150// bits<m> VBDn : address operand n, which has a vector index, a base and a 151// displacement 152// bits<4> Xn : index register for address operand n 153// bits<4> Mn : mode value for operand n 154// 155// The operand numbers ("n" in the list above) follow the architecture manual. 156// Assembly operands sometimes have a different order; in particular, R3 often 157// is often written between operands 1 and 2. 158// 159//===----------------------------------------------------------------------===// 160 161class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 162 : InstSystemZ<4, outs, ins, asmstr, pattern> { 163 field bits<32> Inst; 164 field bits<32> SoftFail = 0; 165 166 bits<4> R1; 167 bits<16> I2; 168 169 let Inst{31-24} = op{11-4}; 170 let Inst{23-20} = R1; 171 let Inst{19-16} = op{3-0}; 172 let Inst{15-0} = I2; 173} 174 175class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 176 : InstSystemZ<6, outs, ins, asmstr, pattern> { 177 field bits<48> Inst; 178 field bits<48> SoftFail = 0; 179 180 bits<4> R1; 181 bits<4> R2; 182 bits<4> M3; 183 bits<16> RI4; 184 185 let Inst{47-40} = op{15-8}; 186 let Inst{39-36} = R1; 187 let Inst{35-32} = R2; 188 let Inst{31-16} = RI4; 189 let Inst{15-12} = M3; 190 let Inst{11-8} = 0; 191 let Inst{7-0} = op{7-0}; 192} 193 194class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 195 : InstSystemZ<6, outs, ins, asmstr, pattern> { 196 field bits<48> Inst; 197 field bits<48> SoftFail = 0; 198 199 bits<4> R1; 200 bits<8> I2; 201 bits<4> M3; 202 bits<16> RI4; 203 204 let Inst{47-40} = op{15-8}; 205 let Inst{39-36} = R1; 206 let Inst{35-32} = M3; 207 let Inst{31-16} = RI4; 208 let Inst{15-8} = I2; 209 let Inst{7-0} = op{7-0}; 210} 211 212class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 213 : InstSystemZ<6, outs, ins, asmstr, pattern> { 214 field bits<48> Inst; 215 field bits<48> SoftFail = 0; 216 217 bits<4> R1; 218 bits<4> R3; 219 bits<16> I2; 220 221 let Inst{47-40} = op{15-8}; 222 let Inst{39-36} = R1; 223 let Inst{35-32} = R3; 224 let Inst{31-16} = I2; 225 let Inst{15-8} = 0; 226 let Inst{7-0} = op{7-0}; 227} 228 229class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 230 : InstSystemZ<6, outs, ins, asmstr, pattern> { 231 field bits<48> Inst; 232 field bits<48> SoftFail = 0; 233 234 bits<4> R1; 235 bits<4> R2; 236 bits<8> I3; 237 bits<8> I4; 238 bits<8> I5; 239 240 let Inst{47-40} = op{15-8}; 241 let Inst{39-36} = R1; 242 let Inst{35-32} = R2; 243 let Inst{31-24} = I3; 244 let Inst{23-16} = I4; 245 let Inst{15-8} = I5; 246 let Inst{7-0} = op{7-0}; 247} 248 249class InstRIL<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 250 : InstSystemZ<6, outs, ins, asmstr, pattern> { 251 field bits<48> Inst; 252 field bits<48> SoftFail = 0; 253 254 bits<4> R1; 255 bits<32> I2; 256 257 let Inst{47-40} = op{11-4}; 258 let Inst{39-36} = R1; 259 let Inst{35-32} = op{3-0}; 260 let Inst{31-0} = I2; 261} 262 263class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 264 : InstSystemZ<2, outs, ins, asmstr, pattern> { 265 field bits<16> Inst; 266 field bits<16> SoftFail = 0; 267 268 bits<4> R1; 269 bits<4> R2; 270 271 let Inst{15-8} = op; 272 let Inst{7-4} = R1; 273 let Inst{3-0} = R2; 274} 275 276class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 277 : InstSystemZ<4, outs, ins, asmstr, pattern> { 278 field bits<32> Inst; 279 field bits<32> SoftFail = 0; 280 281 bits<4> R1; 282 bits<4> R3; 283 bits<4> R2; 284 285 let Inst{31-16} = op; 286 let Inst{15-12} = R1; 287 let Inst{11-8} = 0; 288 let Inst{7-4} = R3; 289 let Inst{3-0} = R2; 290} 291 292class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 293 : InstSystemZ<4, outs, ins, asmstr, pattern> { 294 field bits<32> Inst; 295 field bits<32> SoftFail = 0; 296 297 bits<4> R1; 298 bits<4> R2; 299 300 let Inst{31-16} = op; 301 let Inst{15-8} = 0; 302 let Inst{7-4} = R1; 303 let Inst{3-0} = R2; 304} 305 306class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 307 : InstSystemZ<4, outs, ins, asmstr, pattern> { 308 field bits<32> Inst; 309 field bits<32> SoftFail = 0; 310 311 bits<4> R1; 312 bits<4> R2; 313 bits<4> R3; 314 bits<4> R4; 315 316 let Inst{31-16} = op; 317 let Inst{15-12} = R3; 318 let Inst{11-8} = R4; 319 let Inst{7-4} = R1; 320 let Inst{3-0} = R2; 321} 322 323class InstRX<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 324 : InstSystemZ<4, outs, ins, asmstr, pattern> { 325 field bits<32> Inst; 326 field bits<32> SoftFail = 0; 327 328 bits<4> R1; 329 bits<20> XBD2; 330 331 let Inst{31-24} = op; 332 let Inst{23-20} = R1; 333 let Inst{19-0} = XBD2; 334 335 let HasIndex = 1; 336} 337 338class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 339 : InstSystemZ<6, outs, ins, asmstr, pattern> { 340 field bits<48> Inst; 341 field bits<48> SoftFail = 0; 342 343 bits<4> R1; 344 bits<20> XBD2; 345 bits<4> M3; 346 347 let Inst{47-40} = op{15-8}; 348 let Inst{39-36} = R1; 349 let Inst{35-16} = XBD2; 350 let Inst{15-12} = M3; 351 let Inst{11-8} = 0; 352 let Inst{7-0} = op{7-0}; 353 354 let HasIndex = 1; 355} 356 357class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 358 : InstSystemZ<6, outs, ins, asmstr, pattern> { 359 field bits<48> Inst; 360 field bits<48> SoftFail = 0; 361 362 bits<4> R1; 363 bits<4> R3; 364 bits<20> XBD2; 365 366 let Inst{47-40} = op{15-8}; 367 let Inst{39-36} = R3; 368 let Inst{35-16} = XBD2; 369 let Inst{15-12} = R1; 370 let Inst{11-8} = 0; 371 let Inst{7-0} = op{7-0}; 372 373 let HasIndex = 1; 374} 375 376class InstRXY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 377 : InstSystemZ<6, outs, ins, asmstr, pattern> { 378 field bits<48> Inst; 379 field bits<48> SoftFail = 0; 380 381 bits<4> R1; 382 bits<28> XBD2; 383 384 let Inst{47-40} = op{15-8}; 385 let Inst{39-36} = R1; 386 let Inst{35-8} = XBD2; 387 let Inst{7-0} = op{7-0}; 388 389 let Has20BitOffset = 1; 390 let HasIndex = 1; 391} 392 393class InstRS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 394 : InstSystemZ<4, outs, ins, asmstr, pattern> { 395 field bits<32> Inst; 396 field bits<32> SoftFail = 0; 397 398 bits<4> R1; 399 bits<4> R3; 400 bits<16> BD2; 401 402 let Inst{31-24} = op; 403 let Inst{23-20} = R1; 404 let Inst{19-16} = R3; 405 let Inst{15-0} = BD2; 406} 407 408class InstRSY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 409 : InstSystemZ<6, outs, ins, asmstr, pattern> { 410 field bits<48> Inst; 411 field bits<48> SoftFail = 0; 412 413 bits<4> R1; 414 bits<4> R3; 415 bits<24> BD2; 416 417 let Inst{47-40} = op{15-8}; 418 let Inst{39-36} = R1; 419 let Inst{35-32} = R3; 420 let Inst{31-8} = BD2; 421 let Inst{7-0} = op{7-0}; 422 423 let Has20BitOffset = 1; 424} 425 426class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 427 : InstSystemZ<4, outs, ins, asmstr, pattern> { 428 field bits<32> Inst; 429 field bits<32> SoftFail = 0; 430 431 bits<16> BD1; 432 bits<8> I2; 433 434 let Inst{31-24} = op; 435 let Inst{23-16} = I2; 436 let Inst{15-0} = BD1; 437} 438 439class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 440 : InstSystemZ<6, outs, ins, asmstr, pattern> { 441 field bits<48> Inst; 442 field bits<48> SoftFail = 0; 443 444 bits<16> BD1; 445 bits<16> I2; 446 447 let Inst{47-32} = op; 448 let Inst{31-16} = BD1; 449 let Inst{15-0} = I2; 450} 451 452class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 453 : InstSystemZ<6, outs, ins, asmstr, pattern> { 454 field bits<48> Inst; 455 field bits<48> SoftFail = 0; 456 457 bits<24> BD1; 458 bits<8> I2; 459 460 let Inst{47-40} = op{15-8}; 461 let Inst{39-32} = I2; 462 let Inst{31-8} = BD1; 463 let Inst{7-0} = op{7-0}; 464 465 let Has20BitOffset = 1; 466} 467 468class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 469 : InstSystemZ<6, outs, ins, asmstr, pattern> { 470 field bits<48> Inst; 471 field bits<48> SoftFail = 0; 472 473 bits<24> BDL1; 474 bits<16> BD2; 475 476 let Inst{47-40} = op; 477 let Inst{39-16} = BDL1; 478 let Inst{15-0} = BD2; 479} 480 481class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 482 : InstSystemZ<4, outs, ins, asmstr, pattern> { 483 field bits<32> Inst; 484 field bits<32> SoftFail = 0; 485 486 bits<16> BD2; 487 488 let Inst{31-16} = op; 489 let Inst{15-0} = BD2; 490} 491 492class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 493 : InstSystemZ<6, outs, ins, asmstr, pattern> { 494 field bits<48> Inst; 495 field bits<48> SoftFail = 0; 496 497 bits<5> V1; 498 bits<16> I2; 499 bits<4> M3; 500 501 let Inst{47-40} = op{15-8}; 502 let Inst{39-36} = V1{3-0}; 503 let Inst{35-32} = 0; 504 let Inst{31-16} = I2; 505 let Inst{15-12} = M3; 506 let Inst{11} = V1{4}; 507 let Inst{10-8} = 0; 508 let Inst{7-0} = op{7-0}; 509} 510 511class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 512 : InstSystemZ<6, outs, ins, asmstr, pattern> { 513 field bits<48> Inst; 514 field bits<48> SoftFail = 0; 515 516 bits<5> V1; 517 bits<8> I2; 518 bits<8> I3; 519 bits<4> M4; 520 521 let Inst{47-40} = op{15-8}; 522 let Inst{39-36} = V1{3-0}; 523 let Inst{35-32} = 0; 524 let Inst{31-24} = I2; 525 let Inst{23-16} = I3; 526 let Inst{15-12} = M4; 527 let Inst{11} = V1{4}; 528 let Inst{10-8} = 0; 529 let Inst{7-0} = op{7-0}; 530} 531 532class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 533 : InstSystemZ<6, outs, ins, asmstr, pattern> { 534 field bits<48> Inst; 535 field bits<48> SoftFail = 0; 536 537 bits<5> V1; 538 bits<5> V3; 539 bits<16> I2; 540 bits<4> M4; 541 542 let Inst{47-40} = op{15-8}; 543 let Inst{39-36} = V1{3-0}; 544 let Inst{35-32} = V3{3-0}; 545 let Inst{31-16} = I2; 546 let Inst{15-12} = M4; 547 let Inst{11} = V1{4}; 548 let Inst{10} = V3{4}; 549 let Inst{9-8} = 0; 550 let Inst{7-0} = op{7-0}; 551} 552 553class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 554 : InstSystemZ<6, outs, ins, asmstr, pattern> { 555 field bits<48> Inst; 556 field bits<48> SoftFail = 0; 557 558 bits<5> V1; 559 bits<5> V2; 560 bits<5> V3; 561 bits<8> I4; 562 bits<4> M5; 563 564 let Inst{47-40} = op{15-8}; 565 let Inst{39-36} = V1{3-0}; 566 let Inst{35-32} = V2{3-0}; 567 let Inst{31-28} = V3{3-0}; 568 let Inst{27-24} = 0; 569 let Inst{23-16} = I4; 570 let Inst{15-12} = M5; 571 let Inst{11} = V1{4}; 572 let Inst{10} = V2{4}; 573 let Inst{9} = V3{4}; 574 let Inst{8} = 0; 575 let Inst{7-0} = op{7-0}; 576} 577 578class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 579 : InstSystemZ<6, outs, ins, asmstr, pattern> { 580 field bits<48> Inst; 581 field bits<48> SoftFail = 0; 582 583 bits<5> V1; 584 bits<5> V2; 585 bits<12> I3; 586 bits<4> M4; 587 bits<4> M5; 588 589 let Inst{47-40} = op{15-8}; 590 let Inst{39-36} = V1{3-0}; 591 let Inst{35-32} = V2{3-0}; 592 let Inst{31-20} = I3; 593 let Inst{19-16} = M5; 594 let Inst{15-12} = M4; 595 let Inst{11} = V1{4}; 596 let Inst{10} = V2{4}; 597 let Inst{9-8} = 0; 598 let Inst{7-0} = op{7-0}; 599} 600 601// Depending on the instruction mnemonic, certain bits may be or-ed into 602// the M4 value provided as explicit operand. These are passed as m4or. 603class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 604 bits<4> m4or = 0> 605 : InstSystemZ<6, outs, ins, asmstr, pattern> { 606 field bits<48> Inst; 607 field bits<48> SoftFail = 0; 608 609 bits<5> V1; 610 bits<5> V2; 611 bits<4> M3; 612 bits<4> M4; 613 bits<4> M5; 614 615 let Inst{47-40} = op{15-8}; 616 let Inst{39-36} = V1{3-0}; 617 let Inst{35-32} = V2{3-0}; 618 let Inst{31-24} = 0; 619 let Inst{23-20} = M5; 620 let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3}); 621 let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2}); 622 let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1}); 623 let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0}); 624 let Inst{15-12} = M3; 625 let Inst{11} = V1{4}; 626 let Inst{10} = V2{4}; 627 let Inst{9-8} = 0; 628 let Inst{7-0} = op{7-0}; 629} 630 631// Depending on the instruction mnemonic, certain bits may be or-ed into 632// the M5 value provided as explicit operand. These are passed as m5or. 633class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 634 bits<4> m5or = 0> 635 : InstSystemZ<6, outs, ins, asmstr, pattern> { 636 field bits<48> Inst; 637 field bits<48> SoftFail = 0; 638 639 bits<5> V1; 640 bits<5> V2; 641 bits<5> V3; 642 bits<4> M4; 643 bits<4> M5; 644 645 let Inst{47-40} = op{15-8}; 646 let Inst{39-36} = V1{3-0}; 647 let Inst{35-32} = V2{3-0}; 648 let Inst{31-28} = V3{3-0}; 649 let Inst{27-24} = 0; 650 let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3}); 651 let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2}); 652 let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1}); 653 let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0}); 654 let Inst{19-16} = 0; 655 let Inst{15-12} = M4; 656 let Inst{11} = V1{4}; 657 let Inst{10} = V2{4}; 658 let Inst{9} = V3{4}; 659 let Inst{8} = 0; 660 let Inst{7-0} = op{7-0}; 661} 662 663class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 664 : InstSystemZ<6, outs, ins, asmstr, pattern> { 665 field bits<48> Inst; 666 field bits<48> SoftFail = 0; 667 668 bits<5> V1; 669 bits<5> V2; 670 bits<5> V3; 671 bits<4> M4; 672 bits<4> M5; 673 bits<4> M6; 674 675 let Inst{47-40} = op{15-8}; 676 let Inst{39-36} = V1{3-0}; 677 let Inst{35-32} = V2{3-0}; 678 let Inst{31-28} = V3{3-0}; 679 let Inst{27-24} = 0; 680 let Inst{23-20} = M6; 681 let Inst{19-16} = M5; 682 let Inst{15-12} = M4; 683 let Inst{11} = V1{4}; 684 let Inst{10} = V2{4}; 685 let Inst{9} = V3{4}; 686 let Inst{8} = 0; 687 let Inst{7-0} = op{7-0}; 688} 689 690// Depending on the instruction mnemonic, certain bits may be or-ed into 691// the M6 value provided as explicit operand. These are passed as m6or. 692class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 693 bits<4> m6or = 0> 694 : InstSystemZ<6, outs, ins, asmstr, pattern> { 695 field bits<48> Inst; 696 field bits<48> SoftFail = 0; 697 698 bits<5> V1; 699 bits<5> V2; 700 bits<5> V3; 701 bits<5> V4; 702 bits<4> M5; 703 bits<4> M6; 704 705 let Inst{47-40} = op{15-8}; 706 let Inst{39-36} = V1{3-0}; 707 let Inst{35-32} = V2{3-0}; 708 let Inst{31-28} = V3{3-0}; 709 let Inst{27-24} = M5; 710 let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3}); 711 let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2}); 712 let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1}); 713 let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0}); 714 let Inst{19-16} = 0; 715 let Inst{15-12} = V4{3-0}; 716 let Inst{11} = V1{4}; 717 let Inst{10} = V2{4}; 718 let Inst{9} = V3{4}; 719 let Inst{8} = V4{4}; 720 let Inst{7-0} = op{7-0}; 721} 722 723class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 724 : InstSystemZ<6, outs, ins, asmstr, pattern> { 725 field bits<48> Inst; 726 field bits<48> SoftFail = 0; 727 728 bits<5> V1; 729 bits<5> V2; 730 bits<5> V3; 731 bits<5> V4; 732 bits<4> M5; 733 bits<4> M6; 734 735 let Inst{47-40} = op{15-8}; 736 let Inst{39-36} = V1{3-0}; 737 let Inst{35-32} = V2{3-0}; 738 let Inst{31-28} = V3{3-0}; 739 let Inst{27-24} = M6; 740 let Inst{23-20} = 0; 741 let Inst{19-16} = M5; 742 let Inst{15-12} = V4{3-0}; 743 let Inst{11} = V1{4}; 744 let Inst{10} = V2{4}; 745 let Inst{9} = V3{4}; 746 let Inst{8} = V4{4}; 747 let Inst{7-0} = op{7-0}; 748} 749 750class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 751 : InstSystemZ<6, outs, ins, asmstr, pattern> { 752 field bits<48> Inst; 753 field bits<48> SoftFail = 0; 754 755 bits<5> V1; 756 bits<4> R2; 757 bits<4> R3; 758 759 let Inst{47-40} = op{15-8}; 760 let Inst{39-36} = V1{3-0}; 761 let Inst{35-32} = R2; 762 let Inst{31-28} = R3; 763 let Inst{27-12} = 0; 764 let Inst{11} = V1{4}; 765 let Inst{10-8} = 0; 766 let Inst{7-0} = op{7-0}; 767} 768 769class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 770 : InstSystemZ<6, outs, ins, asmstr, pattern> { 771 field bits<48> Inst; 772 field bits<48> SoftFail = 0; 773 774 bits<5> V1; 775 bits<16> BD2; 776 bits<5> V3; 777 bits<4> M4; 778 779 let Inst{47-40} = op{15-8}; 780 let Inst{39-36} = V1{3-0}; 781 let Inst{35-32} = V3{3-0}; 782 let Inst{31-16} = BD2; 783 let Inst{15-12} = M4; 784 let Inst{11} = V1{4}; 785 let Inst{10} = V3{4}; 786 let Inst{9-8} = 0; 787 let Inst{7-0} = op{7-0}; 788} 789 790class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 791 : InstSystemZ<6, outs, ins, asmstr, pattern> { 792 field bits<48> Inst; 793 field bits<48> SoftFail = 0; 794 795 bits<5> V1; 796 bits<16> BD2; 797 bits<4> R3; 798 bits<4> M4; 799 800 let Inst{47-40} = op{15-8}; 801 let Inst{39-36} = V1{3-0}; 802 let Inst{35-32} = R3; 803 let Inst{31-16} = BD2; 804 let Inst{15-12} = M4; 805 let Inst{11} = V1{4}; 806 let Inst{10-8} = 0; 807 let Inst{7-0} = op{7-0}; 808} 809 810class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 811 : InstSystemZ<6, outs, ins, asmstr, pattern> { 812 field bits<48> Inst; 813 field bits<48> SoftFail = 0; 814 815 bits<4> R1; 816 bits<16> BD2; 817 bits<5> V3; 818 bits<4> M4; 819 820 let Inst{47-40} = op{15-8}; 821 let Inst{39-36} = R1; 822 let Inst{35-32} = V3{3-0}; 823 let Inst{31-16} = BD2; 824 let Inst{15-12} = M4; 825 let Inst{11} = 0; 826 let Inst{10} = V3{4}; 827 let Inst{9-8} = 0; 828 let Inst{7-0} = op{7-0}; 829} 830 831class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 832 : InstSystemZ<6, outs, ins, asmstr, pattern> { 833 field bits<48> Inst; 834 field bits<48> SoftFail = 0; 835 836 bits<5> V1; 837 bits<21> VBD2; 838 bits<4> M3; 839 840 let Inst{47-40} = op{15-8}; 841 let Inst{39-36} = V1{3-0}; 842 let Inst{35-16} = VBD2{19-0}; 843 let Inst{15-12} = M3; 844 let Inst{11} = V1{4}; 845 let Inst{10} = VBD2{20}; 846 let Inst{9-8} = 0; 847 let Inst{7-0} = op{7-0}; 848} 849 850class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 851 : InstSystemZ<6, outs, ins, asmstr, pattern> { 852 field bits<48> Inst; 853 field bits<48> SoftFail = 0; 854 855 bits<5> V1; 856 bits<20> XBD2; 857 bits<4> M3; 858 859 let Inst{47-40} = op{15-8}; 860 let Inst{39-36} = V1{3-0}; 861 let Inst{35-16} = XBD2; 862 let Inst{15-12} = M3; 863 let Inst{11} = V1{4}; 864 let Inst{10-8} = 0; 865 let Inst{7-0} = op{7-0}; 866} 867 868//===----------------------------------------------------------------------===// 869// Instruction definitions with semantics 870//===----------------------------------------------------------------------===// 871// 872// These classes have the form [Cond]<Category><Format>, where <Format> is one 873// of the formats defined above and where <Category> describes the inputs 874// and outputs. "Cond" is used if the instruction is conditional, 875// in which case the 4-bit condition-code mask is added as a final operand. 876// <Category> can be one of: 877// 878// Inherent: 879// One register output operand and no input operands. 880// 881// BranchUnary: 882// One register output operand, one register input operand and 883// one branch displacement. The instructions stores a modified 884// form of the source register in the destination register and 885// branches on the result. 886// 887// LoadMultiple: 888// One address input operand and two explicit output operands. 889// The instruction loads a range of registers from the address, 890// with the explicit operands giving the first and last register 891// to load. Other loaded registers are added as implicit definitions. 892// 893// StoreMultiple: 894// Two explicit input register operands and an address operand. 895// The instruction stores a range of registers to the address, 896// with the explicit operands giving the first and last register 897// to store. Other stored registers are added as implicit uses. 898// 899// StoreLength: 900// One value operand, one length operand and one address operand. 901// The instruction stores the value operand to the address but 902// doesn't write more than the number of bytes specified by the 903// length operand. 904// 905// Unary: 906// One register output operand and one input operand. 907// 908// Store: 909// One address operand and one other input operand. The instruction 910// stores to the address. 911// 912// Binary: 913// One register output operand and two input operands. 914// 915// StoreBinary: 916// One address operand and two other input operands. The instruction 917// stores to the address. 918// 919// Compare: 920// Two input operands and an implicit CC output operand. 921// 922// Ternary: 923// One register output operand and three input operands. 924// 925// Quaternary: 926// One register output operand and four input operands. 927// 928// LoadAndOp: 929// One output operand and two input operands, one of which is an address. 930// The instruction both reads from and writes to the address. 931// 932// CmpSwap: 933// One output operand and three input operands, one of which is an address. 934// The instruction both reads from and writes to the address. 935// 936// RotateSelect: 937// One output operand and five input operands. The first two operands 938// are registers and the other three are immediates. 939// 940// Prefetch: 941// One 4-bit immediate operand and one address operand. The immediate 942// operand is 1 for a load prefetch and 2 for a store prefetch. 943// 944// The format determines which input operands are tied to output operands, 945// and also determines the shape of any address operand. 946// 947// Multiclasses of the form <Category><Format>Pair define two instructions, 948// one with <Category><Format> and one with <Category><Format>Y. The name 949// of the first instruction has no suffix, the name of the second has 950// an extra "y". 951// 952//===----------------------------------------------------------------------===// 953 954class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, 955 dag src> 956 : InstRRE<opcode, (outs cls:$R1), (ins), 957 mnemonic#"\t$R1", 958 [(set cls:$R1, src)]> { 959 let R2 = 0; 960} 961 962class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value> 963 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> { 964 let I2 = value; 965 let M3 = 0; 966} 967 968class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls> 969 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2), 970 mnemonic##"\t$R1, $I2", []> { 971 let isBranch = 1; 972 let isTerminator = 1; 973 let Constraints = "$R1 = $R1src"; 974 let DisableEncoding = "$R1src"; 975} 976 977class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 978 : InstRSY<opcode, (outs cls:$R1, cls:$R3), (ins bdaddr20only:$BD2), 979 mnemonic#"\t$R1, $R3, $BD2", []> { 980 let mayLoad = 1; 981} 982 983class LoadMultipleVRSa<string mnemonic, bits<16> opcode> 984 : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2), 985 mnemonic#"\t$V1, $V3, $BD2", []> { 986 let M4 = 0; 987 let mayLoad = 1; 988} 989 990class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 991 RegisterOperand cls> 992 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2), 993 mnemonic#"\t$R1, $I2", 994 [(operator cls:$R1, pcrel32:$I2)]> { 995 let mayStore = 1; 996 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 997 // However, BDXs have two extra operands and are therefore 6 units more 998 // complex. 999 let AddedComplexity = 7; 1000} 1001 1002class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1003 RegisterOperand cls, bits<5> bytes, 1004 AddressingMode mode = bdxaddr12only> 1005 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2), 1006 mnemonic#"\t$R1, $XBD2", 1007 [(operator cls:$R1, mode:$XBD2)]> { 1008 let OpKey = mnemonic ## cls; 1009 let OpType = "mem"; 1010 let mayStore = 1; 1011 let AccessBytes = bytes; 1012} 1013 1014class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1015 RegisterOperand cls, bits<5> bytes, 1016 AddressingMode mode = bdxaddr20only> 1017 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2), 1018 mnemonic#"\t$R1, $XBD2", 1019 [(operator cls:$R1, mode:$XBD2)]> { 1020 let OpKey = mnemonic ## cls; 1021 let OpType = "mem"; 1022 let mayStore = 1; 1023 let AccessBytes = bytes; 1024} 1025 1026multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 1027 SDPatternOperator operator, RegisterOperand cls, 1028 bits<5> bytes> { 1029 let DispKey = mnemonic ## #cls in { 1030 let DispSize = "12" in 1031 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 1032 let DispSize = "20" in 1033 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 1034 bdxaddr20pair>; 1035 } 1036} 1037 1038class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1039 TypedReg tr, bits<5> bytes, bits<4> type = 0> 1040 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2), 1041 mnemonic#"\t$V1, $XBD2", 1042 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> { 1043 let M3 = type; 1044 let mayStore = 1; 1045 let AccessBytes = bytes; 1046} 1047 1048class StoreLengthVRSb<string mnemonic, bits<16> opcode, 1049 SDPatternOperator operator, bits<5> bytes> 1050 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2), 1051 mnemonic#"\t$V1, $R3, $BD2", 1052 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> { 1053 let M4 = 0; 1054 let mayStore = 1; 1055 let AccessBytes = bytes; 1056} 1057 1058class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 1059 : InstRSY<opcode, (outs), (ins cls:$R1, cls:$R3, bdaddr20only:$BD2), 1060 mnemonic#"\t$R1, $R3, $BD2", []> { 1061 let mayStore = 1; 1062} 1063 1064class StoreMultipleVRSa<string mnemonic, bits<16> opcode> 1065 : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2), 1066 mnemonic#"\t$V1, $V3, $BD2", []> { 1067 let M4 = 0; 1068 let mayStore = 1; 1069} 1070 1071// StoreSI* instructions are used to store an integer to memory, but the 1072// addresses are more restricted than for normal stores. If we are in the 1073// situation of having to force either the address into a register or the 1074// constant into a register, it's usually better to do the latter. 1075// We therefore match the address in the same way as a normal store and 1076// only use the StoreSI* instruction if the matched address is suitable. 1077class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1078 Immediate imm> 1079 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2), 1080 mnemonic#"\t$BD1, $I2", 1081 [(operator imm:$I2, mviaddr12pair:$BD1)]> { 1082 let mayStore = 1; 1083} 1084 1085class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1086 Immediate imm> 1087 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2), 1088 mnemonic#"\t$BD1, $I2", 1089 [(operator imm:$I2, mviaddr20pair:$BD1)]> { 1090 let mayStore = 1; 1091} 1092 1093class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1094 Immediate imm> 1095 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2), 1096 mnemonic#"\t$BD1, $I2", 1097 [(operator imm:$I2, mviaddr12pair:$BD1)]> { 1098 let mayStore = 1; 1099} 1100 1101multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 1102 SDPatternOperator operator, Immediate imm> { 1103 let DispKey = mnemonic in { 1104 let DispSize = "12" in 1105 def "" : StoreSI<mnemonic, siOpcode, operator, imm>; 1106 let DispSize = "20" in 1107 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>; 1108 } 1109} 1110 1111class CondStoreRSY<string mnemonic, bits<16> opcode, 1112 RegisterOperand cls, bits<5> bytes, 1113 AddressingMode mode = bdaddr20only> 1114 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), 1115 mnemonic#"$R3\t$R1, $BD2", []>, 1116 Requires<[FeatureLoadStoreOnCond]> { 1117 let mayStore = 1; 1118 let AccessBytes = bytes; 1119 let CCMaskLast = 1; 1120} 1121 1122// Like CondStoreRSY, but used for the raw assembly form. The condition-code 1123// mask is the third operand rather than being part of the mnemonic. 1124class AsmCondStoreRSY<string mnemonic, bits<16> opcode, 1125 RegisterOperand cls, bits<5> bytes, 1126 AddressingMode mode = bdaddr20only> 1127 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$R3), 1128 mnemonic#"\t$R1, $BD2, $R3", []>, 1129 Requires<[FeatureLoadStoreOnCond]> { 1130 let mayStore = 1; 1131 let AccessBytes = bytes; 1132} 1133 1134// Like CondStoreRSY, but with a fixed CC mask. 1135class FixedCondStoreRSY<string mnemonic, bits<16> opcode, 1136 RegisterOperand cls, bits<4> ccmask, bits<5> bytes, 1137 AddressingMode mode = bdaddr20only> 1138 : InstRSY<opcode, (outs), (ins cls:$R1, mode:$BD2), 1139 mnemonic#"\t$R1, $BD2", []>, 1140 Requires<[FeatureLoadStoreOnCond]> { 1141 let mayStore = 1; 1142 let AccessBytes = bytes; 1143 let R3 = ccmask; 1144} 1145 1146class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1147 RegisterOperand cls1, RegisterOperand cls2> 1148 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2), 1149 mnemonic#"r\t$R1, $R2", 1150 [(set cls1:$R1, (operator cls2:$R2))]> { 1151 let OpKey = mnemonic ## cls1; 1152 let OpType = "reg"; 1153} 1154 1155class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1156 RegisterOperand cls1, RegisterOperand cls2> 1157 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2), 1158 mnemonic#"r\t$R1, $R2", 1159 [(set cls1:$R1, (operator cls2:$R2))]> { 1160 let OpKey = mnemonic ## cls1; 1161 let OpType = "reg"; 1162} 1163 1164class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1165 RegisterOperand cls2> 1166 : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2), 1167 mnemonic#"r\t$R1, $R3, $R2", []> { 1168 let OpKey = mnemonic ## cls1; 1169 let OpType = "reg"; 1170 let R4 = 0; 1171} 1172 1173class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1174 RegisterOperand cls2> 1175 : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2, imm32zx4:$R4), 1176 mnemonic#"\t$R1, $R3, $R2, $R4", []>; 1177 1178// These instructions are generated by if conversion. The old value of R1 1179// is added as an implicit use. 1180class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1181 RegisterOperand cls2> 1182 : InstRRF<opcode, (outs cls1:$R1), (ins cls2:$R2, cond4:$valid, cond4:$R3), 1183 mnemonic#"r$R3\t$R1, $R2", []>, 1184 Requires<[FeatureLoadStoreOnCond]> { 1185 let CCMaskLast = 1; 1186 let R4 = 0; 1187} 1188 1189// Like CondUnaryRRF, but used for the raw assembly form. The condition-code 1190// mask is the third operand rather than being part of the mnemonic. 1191class AsmCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1192 RegisterOperand cls2> 1193 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2, imm32zx4:$R3), 1194 mnemonic#"r\t$R1, $R2, $R3", []>, 1195 Requires<[FeatureLoadStoreOnCond]> { 1196 let Constraints = "$R1 = $R1src"; 1197 let DisableEncoding = "$R1src"; 1198 let R4 = 0; 1199} 1200 1201// Like CondUnaryRRF, but with a fixed CC mask. 1202class FixedCondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 1203 RegisterOperand cls2, bits<4> ccmask> 1204 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 1205 mnemonic#"\t$R1, $R2", []>, 1206 Requires<[FeatureLoadStoreOnCond]> { 1207 let Constraints = "$R1 = $R1src"; 1208 let DisableEncoding = "$R1src"; 1209 let R3 = ccmask; 1210 let R4 = 0; 1211} 1212 1213class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1214 RegisterOperand cls, Immediate imm> 1215 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2), 1216 mnemonic#"\t$R1, $I2", 1217 [(set cls:$R1, (operator imm:$I2))]>; 1218 1219class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1220 RegisterOperand cls, Immediate imm> 1221 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2), 1222 mnemonic#"\t$R1, $I2", 1223 [(set cls:$R1, (operator imm:$I2))]>; 1224 1225class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1226 RegisterOperand cls> 1227 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2), 1228 mnemonic#"\t$R1, $I2", 1229 [(set cls:$R1, (operator pcrel32:$I2))]> { 1230 let mayLoad = 1; 1231 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 1232 // However, BDXs have two extra operands and are therefore 6 units more 1233 // complex. 1234 let AddedComplexity = 7; 1235} 1236 1237class CondUnaryRSY<string mnemonic, bits<16> opcode, 1238 SDPatternOperator operator, RegisterOperand cls, 1239 bits<5> bytes, AddressingMode mode = bdaddr20only> 1240 : InstRSY<opcode, (outs cls:$R1), 1241 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3), 1242 mnemonic#"$R3\t$R1, $BD2", 1243 [(set cls:$R1, 1244 (z_select_ccmask (load bdaddr20only:$BD2), cls:$R1src, 1245 cond4:$valid, cond4:$R3))]>, 1246 Requires<[FeatureLoadStoreOnCond]> { 1247 let Constraints = "$R1 = $R1src"; 1248 let DisableEncoding = "$R1src"; 1249 let mayLoad = 1; 1250 let AccessBytes = bytes; 1251 let CCMaskLast = 1; 1252} 1253 1254// Like CondUnaryRSY, but used for the raw assembly form. The condition-code 1255// mask is the third operand rather than being part of the mnemonic. 1256class AsmCondUnaryRSY<string mnemonic, bits<16> opcode, 1257 RegisterOperand cls, bits<5> bytes, 1258 AddressingMode mode = bdaddr20only> 1259 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$R3), 1260 mnemonic#"\t$R1, $BD2, $R3", []>, 1261 Requires<[FeatureLoadStoreOnCond]> { 1262 let mayLoad = 1; 1263 let AccessBytes = bytes; 1264 let Constraints = "$R1 = $R1src"; 1265 let DisableEncoding = "$R1src"; 1266} 1267 1268// Like CondUnaryRSY, but with a fixed CC mask. 1269class FixedCondUnaryRSY<string mnemonic, bits<16> opcode, 1270 RegisterOperand cls, bits<4> ccmask, bits<5> bytes, 1271 AddressingMode mode = bdaddr20only> 1272 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2), 1273 mnemonic#"\t$R1, $BD2", []>, 1274 Requires<[FeatureLoadStoreOnCond]> { 1275 let Constraints = "$R1 = $R1src"; 1276 let DisableEncoding = "$R1src"; 1277 let R3 = ccmask; 1278 let mayLoad = 1; 1279 let AccessBytes = bytes; 1280} 1281 1282class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1283 RegisterOperand cls, bits<5> bytes, 1284 AddressingMode mode = bdxaddr12only> 1285 : InstRX<opcode, (outs cls:$R1), (ins mode:$XBD2), 1286 mnemonic#"\t$R1, $XBD2", 1287 [(set cls:$R1, (operator mode:$XBD2))]> { 1288 let OpKey = mnemonic ## cls; 1289 let OpType = "mem"; 1290 let mayLoad = 1; 1291 let AccessBytes = bytes; 1292} 1293 1294class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1295 RegisterOperand cls, bits<5> bytes> 1296 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2), 1297 mnemonic#"\t$R1, $XBD2", 1298 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> { 1299 let OpKey = mnemonic ## cls; 1300 let OpType = "mem"; 1301 let mayLoad = 1; 1302 let AccessBytes = bytes; 1303 let M3 = 0; 1304} 1305 1306class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1307 RegisterOperand cls, bits<5> bytes, 1308 AddressingMode mode = bdxaddr20only> 1309 : InstRXY<opcode, (outs cls:$R1), (ins mode:$XBD2), 1310 mnemonic#"\t$R1, $XBD2", 1311 [(set cls:$R1, (operator mode:$XBD2))]> { 1312 let OpKey = mnemonic ## cls; 1313 let OpType = "mem"; 1314 let mayLoad = 1; 1315 let AccessBytes = bytes; 1316} 1317 1318multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 1319 SDPatternOperator operator, RegisterOperand cls, 1320 bits<5> bytes> { 1321 let DispKey = mnemonic ## #cls in { 1322 let DispSize = "12" in 1323 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 1324 let DispSize = "20" in 1325 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 1326 bdxaddr20pair>; 1327 } 1328} 1329 1330class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1331 TypedReg tr, Immediate imm, bits<4> type = 0> 1332 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2), 1333 mnemonic#"\t$V1, $I2", 1334 [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> { 1335 let M3 = type; 1336} 1337 1338class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1339 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0, 1340 bits<4> m5 = 0> 1341 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2), 1342 mnemonic#"\t$V1, $V2", 1343 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]> { 1344 let M3 = type; 1345 let M4 = m4; 1346 let M5 = m5; 1347} 1348 1349multiclass UnaryVRRaSPair<string mnemonic, bits<16> opcode, 1350 SDPatternOperator operator, 1351 SDPatternOperator operator_cc, TypedReg tr1, 1352 TypedReg tr2, bits<4> type, bits<4> modifier = 0, 1353 bits<4> modifier_cc = 1> { 1354 def "" : UnaryVRRa<mnemonic, opcode, operator, tr1, tr2, type, 0, modifier>; 1355 let Defs = [CC] in 1356 def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 0, 1357 modifier_cc>; 1358} 1359 1360class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1361 TypedReg tr, bits<5> bytes, bits<4> type = 0> 1362 : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2), 1363 mnemonic#"\t$V1, $XBD2", 1364 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2)))]> { 1365 let M3 = type; 1366 let mayLoad = 1; 1367 let AccessBytes = bytes; 1368} 1369 1370class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1371 RegisterOperand cls1, RegisterOperand cls2> 1372 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 1373 mnemonic#"r\t$R1, $R2", 1374 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 1375 let OpKey = mnemonic ## cls1; 1376 let OpType = "reg"; 1377 let Constraints = "$R1 = $R1src"; 1378 let DisableEncoding = "$R1src"; 1379} 1380 1381class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1382 RegisterOperand cls1, RegisterOperand cls2> 1383 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 1384 mnemonic#"r\t$R1, $R2", 1385 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 1386 let OpKey = mnemonic ## cls1; 1387 let OpType = "reg"; 1388 let Constraints = "$R1 = $R1src"; 1389 let DisableEncoding = "$R1src"; 1390} 1391 1392class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1393 RegisterOperand cls1, RegisterOperand cls2> 1394 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R3, cls2:$R2), 1395 mnemonic#"r\t$R1, $R3, $R2", 1396 [(set cls1:$R1, (operator cls1:$R3, cls2:$R2))]> { 1397 let OpKey = mnemonic ## cls1; 1398 let OpType = "reg"; 1399 let R4 = 0; 1400} 1401 1402class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1403 RegisterOperand cls1, RegisterOperand cls2> 1404 : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3), 1405 mnemonic#"rk\t$R1, $R2, $R3", 1406 [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> { 1407 let R4 = 0; 1408} 1409 1410multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 1411 SDPatternOperator operator, RegisterOperand cls1, 1412 RegisterOperand cls2> { 1413 let NumOpsKey = mnemonic in { 1414 let NumOpsValue = "3" in 1415 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>, 1416 Requires<[FeatureDistinctOps]>; 1417 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 1418 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>; 1419 } 1420} 1421 1422multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2, 1423 SDPatternOperator operator, RegisterOperand cls1, 1424 RegisterOperand cls2> { 1425 let NumOpsKey = mnemonic in { 1426 let NumOpsValue = "3" in 1427 def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>, 1428 Requires<[FeatureDistinctOps]>; 1429 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 1430 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>; 1431 } 1432} 1433 1434class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1435 RegisterOperand cls, Immediate imm> 1436 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 1437 mnemonic#"\t$R1, $I2", 1438 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 1439 let Constraints = "$R1 = $R1src"; 1440 let DisableEncoding = "$R1src"; 1441} 1442 1443class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1444 RegisterOperand cls, Immediate imm> 1445 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2), 1446 mnemonic#"\t$R1, $R3, $I2", 1447 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 1448 1449multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2, 1450 SDPatternOperator operator, RegisterOperand cls, 1451 Immediate imm> { 1452 let NumOpsKey = mnemonic in { 1453 let NumOpsValue = "3" in 1454 def K : BinaryRIE<mnemonic##"k", opcode2, null_frag, cls, imm>, 1455 Requires<[FeatureDistinctOps]>; 1456 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 1457 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>; 1458 } 1459} 1460 1461class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1462 RegisterOperand cls, Immediate imm> 1463 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 1464 mnemonic#"\t$R1, $I2", 1465 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 1466 let Constraints = "$R1 = $R1src"; 1467 let DisableEncoding = "$R1src"; 1468} 1469 1470class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1471 RegisterOperand cls> 1472 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2), 1473 mnemonic#"\t$R1, $BD2", 1474 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> { 1475 let R3 = 0; 1476 let Constraints = "$R1 = $R1src"; 1477 let DisableEncoding = "$R1src"; 1478} 1479 1480class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1481 RegisterOperand cls> 1482 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2), 1483 mnemonic#"\t$R1, $R3, $BD2", 1484 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>; 1485 1486multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 1487 SDPatternOperator operator, RegisterOperand cls> { 1488 let NumOpsKey = mnemonic in { 1489 let NumOpsValue = "3" in 1490 def K : BinaryRSY<mnemonic##"k", opcode2, null_frag, cls>, 1491 Requires<[FeatureDistinctOps]>; 1492 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 1493 def "" : BinaryRS<mnemonic, opcode1, operator, cls>; 1494 } 1495} 1496 1497class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1498 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1499 AddressingMode mode = bdxaddr12only> 1500 : InstRX<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2), 1501 mnemonic#"\t$R1, $XBD2", 1502 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 1503 let OpKey = mnemonic ## cls; 1504 let OpType = "mem"; 1505 let Constraints = "$R1 = $R1src"; 1506 let DisableEncoding = "$R1src"; 1507 let mayLoad = 1; 1508 let AccessBytes = bytes; 1509} 1510 1511class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1512 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 1513 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2), 1514 mnemonic#"\t$R1, $XBD2", 1515 [(set cls:$R1, (operator cls:$R1src, 1516 (load bdxaddr12only:$XBD2)))]> { 1517 let OpKey = mnemonic ## cls; 1518 let OpType = "mem"; 1519 let Constraints = "$R1 = $R1src"; 1520 let DisableEncoding = "$R1src"; 1521 let mayLoad = 1; 1522 let AccessBytes = bytes; 1523 let M3 = 0; 1524} 1525 1526class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1527 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1528 AddressingMode mode = bdxaddr20only> 1529 : InstRXY<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2), 1530 mnemonic#"\t$R1, $XBD2", 1531 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 1532 let OpKey = mnemonic ## cls; 1533 let OpType = "mem"; 1534 let Constraints = "$R1 = $R1src"; 1535 let DisableEncoding = "$R1src"; 1536 let mayLoad = 1; 1537 let AccessBytes = bytes; 1538} 1539 1540multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 1541 SDPatternOperator operator, RegisterOperand cls, 1542 SDPatternOperator load, bits<5> bytes> { 1543 let DispKey = mnemonic ## #cls in { 1544 let DispSize = "12" in 1545 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes, 1546 bdxaddr12pair>; 1547 let DispSize = "20" in 1548 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes, 1549 bdxaddr20pair>; 1550 } 1551} 1552 1553class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1554 Operand imm, AddressingMode mode = bdaddr12only> 1555 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 1556 mnemonic#"\t$BD1, $I2", 1557 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> { 1558 let mayLoad = 1; 1559 let mayStore = 1; 1560} 1561 1562class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1563 Operand imm, AddressingMode mode = bdaddr20only> 1564 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 1565 mnemonic#"\t$BD1, $I2", 1566 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> { 1567 let mayLoad = 1; 1568 let mayStore = 1; 1569} 1570 1571multiclass BinarySIPair<string mnemonic, bits<8> siOpcode, 1572 bits<16> siyOpcode, SDPatternOperator operator, 1573 Operand imm> { 1574 let DispKey = mnemonic ## #cls in { 1575 let DispSize = "12" in 1576 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>; 1577 let DispSize = "20" in 1578 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>; 1579 } 1580} 1581 1582class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1583 TypedReg tr, bits<4> type> 1584 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3), 1585 mnemonic#"\t$V1, $I2, $I3", 1586 [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> { 1587 let M4 = type; 1588} 1589 1590class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1591 TypedReg tr1, TypedReg tr2, bits<4> type> 1592 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2), 1593 mnemonic#"\t$V1, $V3, $I2", 1594 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3), 1595 imm32zx16:$I2)))]> { 1596 let M4 = type; 1597} 1598 1599class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1600 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5> 1601 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3), 1602 mnemonic#"\t$V1, $V2, $I3", 1603 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1604 imm32zx12:$I3)))]> { 1605 let M4 = type; 1606 let M5 = m5; 1607} 1608 1609class BinaryVRRa<string mnemonic, bits<16> opcode> 1610 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3), 1611 mnemonic#"\t$V1, $V2, $M3", []> { 1612 let M4 = 0; 1613 let M5 = 0; 1614} 1615 1616class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1617 TypedReg tr1, TypedReg tr2, bits<4> type = 0, 1618 bits<4> modifier = 0> 1619 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), 1620 mnemonic#"\t$V1, $V2, $V3", 1621 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1622 (tr2.vt tr2.op:$V3))))]> { 1623 let M4 = type; 1624 let M5 = modifier; 1625} 1626 1627// Declare a pair of instructions, one which sets CC and one which doesn't. 1628// The CC-setting form ends with "S" and sets the low bit of M5. 1629multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode, 1630 SDPatternOperator operator, 1631 SDPatternOperator operator_cc, TypedReg tr1, 1632 TypedReg tr2, bits<4> type, 1633 bits<4> modifier = 0, bits<4> modifier_cc = 1> { 1634 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, modifier>; 1635 let Defs = [CC] in 1636 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1637 modifier_cc>; 1638} 1639 1640class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1641 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0, 1642 bits<4> m6 = 0> 1643 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), 1644 mnemonic#"\t$V1, $V2, $V3", 1645 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1646 (tr2.vt tr2.op:$V3))))]> { 1647 let M4 = type; 1648 let M5 = m5; 1649 let M6 = m6; 1650} 1651 1652multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode, 1653 SDPatternOperator operator, 1654 SDPatternOperator operator_cc, TypedReg tr1, 1655 TypedReg tr2, bits<4> type, bits<4> m5, 1656 bits<4> modifier = 0, bits<4> modifier_cc = 1> { 1657 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, modifier>; 1658 let Defs = [CC] in 1659 def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1660 m5, modifier_cc>; 1661} 1662 1663class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1664 TypedReg tr> 1665 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3), 1666 mnemonic#"\t$V1, $R2, $R3", 1667 [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>; 1668 1669class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1670 TypedReg tr1, TypedReg tr2, bits<4> type> 1671 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2), 1672 mnemonic#"\t$V1, $V3, $BD2", 1673 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V3), 1674 shift12only:$BD2)))]> { 1675 let M4 = type; 1676} 1677 1678class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1679 bits<5> bytes> 1680 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2), 1681 mnemonic#"\t$V1, $R3, $BD2", 1682 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> { 1683 let M4 = 0; 1684 let mayLoad = 1; 1685 let AccessBytes = bytes; 1686} 1687 1688class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1689 TypedReg tr, bits<4> type> 1690 : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2), 1691 mnemonic#"\t$R1, $V3, $BD2", 1692 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> { 1693 let M4 = type; 1694} 1695 1696class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1697 TypedReg tr, bits<5> bytes> 1698 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 1699 mnemonic#"\t$V1, $XBD2, $M3", 1700 [(set tr.op:$V1, (tr.vt (operator bdxaddr12only:$XBD2, 1701 imm32zx4:$M3)))]> { 1702 let mayLoad = 1; 1703 let AccessBytes = bytes; 1704} 1705 1706class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, 1707 Immediate index> 1708 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3), 1709 mnemonic#"\t$V1, $VBD2, $M3", []> { 1710 let mayStore = 1; 1711 let AccessBytes = bytes; 1712} 1713 1714class StoreBinaryVRX<string mnemonic, bits<16> opcode, 1715 SDPatternOperator operator, TypedReg tr, bits<5> bytes, 1716 Immediate index> 1717 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3), 1718 mnemonic#"\t$V1, $XBD2, $M3", 1719 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> { 1720 let mayStore = 1; 1721 let AccessBytes = bytes; 1722} 1723 1724class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1725 RegisterOperand cls1, RegisterOperand cls2> 1726 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2), 1727 mnemonic#"r\t$R1, $R2", 1728 [(operator cls1:$R1, cls2:$R2)]> { 1729 let OpKey = mnemonic ## cls1; 1730 let OpType = "reg"; 1731 let isCompare = 1; 1732} 1733 1734class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1735 RegisterOperand cls1, RegisterOperand cls2> 1736 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), 1737 mnemonic#"r\t$R1, $R2", 1738 [(operator cls1:$R1, cls2:$R2)]> { 1739 let OpKey = mnemonic ## cls1; 1740 let OpType = "reg"; 1741 let isCompare = 1; 1742} 1743 1744class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1745 RegisterOperand cls, Immediate imm> 1746 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2), 1747 mnemonic#"\t$R1, $I2", 1748 [(operator cls:$R1, imm:$I2)]> { 1749 let isCompare = 1; 1750} 1751 1752class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1753 RegisterOperand cls, Immediate imm> 1754 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2), 1755 mnemonic#"\t$R1, $I2", 1756 [(operator cls:$R1, imm:$I2)]> { 1757 let isCompare = 1; 1758} 1759 1760class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 1761 RegisterOperand cls, SDPatternOperator load> 1762 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2), 1763 mnemonic#"\t$R1, $I2", 1764 [(operator cls:$R1, (load pcrel32:$I2))]> { 1765 let isCompare = 1; 1766 let mayLoad = 1; 1767 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 1768 // However, BDXs have two extra operands and are therefore 6 units more 1769 // complex. 1770 let AddedComplexity = 7; 1771} 1772 1773class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1774 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1775 AddressingMode mode = bdxaddr12only> 1776 : InstRX<opcode, (outs), (ins cls:$R1, mode:$XBD2), 1777 mnemonic#"\t$R1, $XBD2", 1778 [(operator cls:$R1, (load mode:$XBD2))]> { 1779 let OpKey = mnemonic ## cls; 1780 let OpType = "mem"; 1781 let isCompare = 1; 1782 let mayLoad = 1; 1783 let AccessBytes = bytes; 1784} 1785 1786class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1787 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 1788 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2), 1789 mnemonic#"\t$R1, $XBD2", 1790 [(operator cls:$R1, (load bdxaddr12only:$XBD2))]> { 1791 let OpKey = mnemonic ## cls; 1792 let OpType = "mem"; 1793 let isCompare = 1; 1794 let mayLoad = 1; 1795 let AccessBytes = bytes; 1796 let M3 = 0; 1797} 1798 1799class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1800 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 1801 AddressingMode mode = bdxaddr20only> 1802 : InstRXY<opcode, (outs), (ins cls:$R1, mode:$XBD2), 1803 mnemonic#"\t$R1, $XBD2", 1804 [(operator cls:$R1, (load mode:$XBD2))]> { 1805 let OpKey = mnemonic ## cls; 1806 let OpType = "mem"; 1807 let isCompare = 1; 1808 let mayLoad = 1; 1809 let AccessBytes = bytes; 1810} 1811 1812multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 1813 SDPatternOperator operator, RegisterOperand cls, 1814 SDPatternOperator load, bits<5> bytes> { 1815 let DispKey = mnemonic ## #cls in { 1816 let DispSize = "12" in 1817 def "" : CompareRX<mnemonic, rxOpcode, operator, cls, 1818 load, bytes, bdxaddr12pair>; 1819 let DispSize = "20" in 1820 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls, 1821 load, bytes, bdxaddr20pair>; 1822 } 1823} 1824 1825class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 1826 SDPatternOperator load, Immediate imm, 1827 AddressingMode mode = bdaddr12only> 1828 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 1829 mnemonic#"\t$BD1, $I2", 1830 [(operator (load mode:$BD1), imm:$I2)]> { 1831 let isCompare = 1; 1832 let mayLoad = 1; 1833} 1834 1835class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1836 SDPatternOperator load, Immediate imm> 1837 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2), 1838 mnemonic#"\t$BD1, $I2", 1839 [(operator (load bdaddr12only:$BD1), imm:$I2)]> { 1840 let isCompare = 1; 1841 let mayLoad = 1; 1842} 1843 1844class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1845 SDPatternOperator load, Immediate imm, 1846 AddressingMode mode = bdaddr20only> 1847 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 1848 mnemonic#"\t$BD1, $I2", 1849 [(operator (load mode:$BD1), imm:$I2)]> { 1850 let isCompare = 1; 1851 let mayLoad = 1; 1852} 1853 1854multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 1855 SDPatternOperator operator, SDPatternOperator load, 1856 Immediate imm> { 1857 let DispKey = mnemonic in { 1858 let DispSize = "12" in 1859 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>; 1860 let DispSize = "20" in 1861 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm, 1862 bdaddr20pair>; 1863 } 1864} 1865 1866class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1867 TypedReg tr, bits<4> type> 1868 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2), 1869 mnemonic#"\t$V1, $V2", 1870 [(operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2))]> { 1871 let isCompare = 1; 1872 let M3 = type; 1873 let M4 = 0; 1874 let M5 = 0; 1875} 1876 1877class TernaryRRD<string mnemonic, bits<16> opcode, 1878 SDPatternOperator operator, RegisterOperand cls> 1879 : InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2), 1880 mnemonic#"r\t$R1, $R3, $R2", 1881 [(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> { 1882 let OpKey = mnemonic ## cls; 1883 let OpType = "reg"; 1884 let Constraints = "$R1 = $R1src"; 1885 let DisableEncoding = "$R1src"; 1886} 1887 1888class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1889 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 1890 : InstRXF<opcode, (outs cls:$R1), 1891 (ins cls:$R1src, cls:$R3, bdxaddr12only:$XBD2), 1892 mnemonic#"\t$R1, $R3, $XBD2", 1893 [(set cls:$R1, (operator cls:$R1src, cls:$R3, 1894 (load bdxaddr12only:$XBD2)))]> { 1895 let OpKey = mnemonic ## cls; 1896 let OpType = "mem"; 1897 let Constraints = "$R1 = $R1src"; 1898 let DisableEncoding = "$R1src"; 1899 let mayLoad = 1; 1900 let AccessBytes = bytes; 1901} 1902 1903class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1904 TypedReg tr1, TypedReg tr2, Immediate imm, Immediate index> 1905 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3), 1906 mnemonic#"\t$V1, $I2, $M3", 1907 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), 1908 imm:$I2, index:$M3)))]> { 1909 let Constraints = "$V1 = $V1src"; 1910 let DisableEncoding = "$V1src"; 1911} 1912 1913class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1914 TypedReg tr1, TypedReg tr2, bits<4> type> 1915 : InstVRId<opcode, (outs tr1.op:$V1), 1916 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), 1917 mnemonic#"\t$V1, $V2, $V3, $I4", 1918 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1919 (tr2.vt tr2.op:$V3), 1920 imm32zx8:$I4)))]> { 1921 let M5 = type; 1922} 1923 1924class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1925 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or> 1926 : InstVRRa<opcode, (outs tr1.op:$V1), 1927 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5), 1928 mnemonic#"\t$V1, $V2, $M4, $M5", 1929 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1930 imm32zx4:$M4, 1931 imm32zx4:$M5)))], 1932 m4or> { 1933 let M3 = type; 1934} 1935 1936class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1937 TypedReg tr1, TypedReg tr2, bits<4> type, 1938 SDPatternOperator m5mask, bits<4> m5or> 1939 : InstVRRb<opcode, (outs tr1.op:$V1), 1940 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5), 1941 mnemonic#"\t$V1, $V2, $V3, $M5", 1942 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1943 (tr2.vt tr2.op:$V3), 1944 m5mask:$M5)))], 1945 m5or> { 1946 let M4 = type; 1947} 1948 1949multiclass TernaryVRRbSPair<string mnemonic, bits<16> opcode, 1950 SDPatternOperator operator, 1951 SDPatternOperator operator_cc, TypedReg tr1, 1952 TypedReg tr2, bits<4> type, bits<4> m5or> { 1953 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, 1954 imm32zx4even, !and (m5or, 14)>; 1955 def : InstAlias<mnemonic#"\t$V1, $V2, $V3", 1956 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 1957 tr2.op:$V3, 0)>; 1958 let Defs = [CC] in 1959 def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1960 imm32zx4even, !add(!and (m5or, 14), 1)>; 1961 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3", 1962 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, 1963 tr2.op:$V3, 0)>; 1964} 1965 1966class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1967 TypedReg tr1, TypedReg tr2> 1968 : InstVRRc<opcode, (outs tr1.op:$V1), 1969 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4), 1970 mnemonic#"\t$V1, $V2, $V3, $M4", 1971 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1972 (tr2.vt tr2.op:$V3), 1973 imm32zx4:$M4)))]> { 1974 let M5 = 0; 1975 let M6 = 0; 1976} 1977 1978class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1979 TypedReg tr1, TypedReg tr2, bits<4> type = 0> 1980 : InstVRRd<opcode, (outs tr1.op:$V1), 1981 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), 1982 mnemonic#"\t$V1, $V2, $V3, $V4", 1983 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1984 (tr2.vt tr2.op:$V3), 1985 (tr1.vt tr1.op:$V4))))]> { 1986 let M5 = type; 1987 let M6 = 0; 1988} 1989 1990class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator, 1991 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0> 1992 : InstVRRe<opcode, (outs tr1.op:$V1), 1993 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), 1994 mnemonic#"\t$V1, $V2, $V3, $V4", 1995 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 1996 (tr2.vt tr2.op:$V3), 1997 (tr1.vt tr1.op:$V4))))]> { 1998 let M5 = m5; 1999 let M6 = type; 2000} 2001 2002class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2003 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type> 2004 : InstVRSb<opcode, (outs tr1.op:$V1), 2005 (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2), 2006 mnemonic#"\t$V1, $R3, $BD2", 2007 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), 2008 cls:$R3, 2009 shift12only:$BD2)))]> { 2010 let Constraints = "$V1 = $V1src"; 2011 let DisableEncoding = "$V1src"; 2012 let M4 = type; 2013} 2014 2015class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, 2016 Immediate index> 2017 : InstVRV<opcode, (outs VR128:$V1), 2018 (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3), 2019 mnemonic#"\t$V1, $VBD2, $M3", []> { 2020 let Constraints = "$V1 = $V1src"; 2021 let DisableEncoding = "$V1src"; 2022 let mayLoad = 1; 2023 let AccessBytes = bytes; 2024} 2025 2026class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2027 TypedReg tr1, TypedReg tr2, bits<5> bytes, Immediate index> 2028 : InstVRX<opcode, (outs tr1.op:$V1), 2029 (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3), 2030 mnemonic#"\t$V1, $XBD2, $M3", 2031 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), 2032 bdxaddr12only:$XBD2, 2033 index:$M3)))]> { 2034 let Constraints = "$V1 = $V1src"; 2035 let DisableEncoding = "$V1src"; 2036 let mayLoad = 1; 2037 let AccessBytes = bytes; 2038} 2039 2040class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2041 TypedReg tr1, TypedReg tr2, bits<4> type> 2042 : InstVRId<opcode, (outs tr1.op:$V1), 2043 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), 2044 mnemonic#"\t$V1, $V2, $V3, $I4", 2045 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V1src), 2046 (tr2.vt tr2.op:$V2), 2047 (tr2.vt tr2.op:$V3), 2048 imm32zx8:$I4)))]> { 2049 let Constraints = "$V1 = $V1src"; 2050 let DisableEncoding = "$V1src"; 2051 let M5 = type; 2052} 2053 2054class QuaternaryVRRd<string mnemonic, bits<16> opcode, 2055 SDPatternOperator operator, TypedReg tr1, TypedReg tr2, 2056 bits<4> type, SDPatternOperator m6mask, bits<4> m6or> 2057 : InstVRRd<opcode, (outs tr1.op:$V1), 2058 (ins tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, m6mask:$M6), 2059 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", 2060 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2), 2061 (tr2.vt tr2.op:$V3), 2062 (tr2.vt tr2.op:$V4), 2063 m6mask:$M6)))], 2064 m6or> { 2065 let M5 = type; 2066} 2067 2068multiclass QuaternaryVRRdSPair<string mnemonic, bits<16> opcode, 2069 SDPatternOperator operator, 2070 SDPatternOperator operator_cc, TypedReg tr1, 2071 TypedReg tr2, bits<4> type, bits<4> m6or> { 2072 def "" : QuaternaryVRRd<mnemonic, opcode, operator, tr1, tr2, type, 2073 imm32zx4even, !and (m6or, 14)>; 2074 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4", 2075 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 2076 tr2.op:$V3, tr2.op:$V4, 0)>; 2077 let Defs = [CC] in 2078 def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 2079 imm32zx4even, !add (!and (m6or, 14), 1)>; 2080 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4", 2081 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, 2082 tr2.op:$V3, tr2.op:$V4, 0)>; 2083} 2084 2085class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2086 RegisterOperand cls, AddressingMode mode = bdaddr20only> 2087 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2), 2088 mnemonic#"\t$R1, $R3, $BD2", 2089 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> { 2090 let mayLoad = 1; 2091 let mayStore = 1; 2092} 2093 2094class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 2095 RegisterOperand cls, AddressingMode mode = bdaddr12only> 2096 : InstRS<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), 2097 mnemonic#"\t$R1, $R3, $BD2", 2098 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 2099 let Constraints = "$R1 = $R1src"; 2100 let DisableEncoding = "$R1src"; 2101 let mayLoad = 1; 2102 let mayStore = 1; 2103} 2104 2105class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2106 RegisterOperand cls, AddressingMode mode = bdaddr20only> 2107 : InstRSY<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), 2108 mnemonic#"\t$R1, $R3, $BD2", 2109 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 2110 let Constraints = "$R1 = $R1src"; 2111 let DisableEncoding = "$R1src"; 2112 let mayLoad = 1; 2113 let mayStore = 1; 2114} 2115 2116multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 2117 SDPatternOperator operator, RegisterOperand cls> { 2118 let DispKey = mnemonic ## #cls in { 2119 let DispSize = "12" in 2120 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>; 2121 let DispSize = "20" in 2122 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>; 2123 } 2124} 2125 2126class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1, 2127 RegisterOperand cls2> 2128 : InstRIEf<opcode, (outs cls1:$R1), 2129 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 2130 imm32zx6:$I5), 2131 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> { 2132 let Constraints = "$R1 = $R1src"; 2133 let DisableEncoding = "$R1src"; 2134} 2135 2136class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator> 2137 : InstRXY<opcode, (outs), (ins imm32zx4:$R1, bdxaddr20only:$XBD2), 2138 mnemonic##"\t$R1, $XBD2", 2139 [(operator imm32zx4:$R1, bdxaddr20only:$XBD2)]>; 2140 2141class PrefetchRILPC<string mnemonic, bits<12> opcode, 2142 SDPatternOperator operator> 2143 : InstRIL<opcode, (outs), (ins imm32zx4:$R1, pcrel32:$I2), 2144 mnemonic##"\t$R1, $I2", 2145 [(operator imm32zx4:$R1, pcrel32:$I2)]> { 2146 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 2147 // However, BDXs have two extra operands and are therefore 6 units more 2148 // complex. 2149 let AddedComplexity = 7; 2150} 2151 2152// A floating-point load-and test operation. Create both a normal unary 2153// operation and one that acts as a comparison against zero. 2154// Note that the comparison against zero operation is not available if we 2155// have vector support, since load-and-test instructions will partially 2156// clobber the target (vector) register. 2157multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode, 2158 RegisterOperand cls> { 2159 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>; 2160 let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in 2161 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>; 2162} 2163 2164//===----------------------------------------------------------------------===// 2165// Pseudo instructions 2166//===----------------------------------------------------------------------===// 2167// 2168// Convenience instructions that get lowered to real instructions 2169// by either SystemZTargetLowering::EmitInstrWithCustomInserter() 2170// or SystemZInstrInfo::expandPostRAPseudo(). 2171// 2172//===----------------------------------------------------------------------===// 2173 2174class Pseudo<dag outs, dag ins, list<dag> pattern> 2175 : InstSystemZ<0, outs, ins, "", pattern> { 2176 let isPseudo = 1; 2177 let isCodeGenOnly = 1; 2178} 2179 2180// Like UnaryRI, but expanded after RA depending on the choice of register. 2181class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, 2182 Immediate imm> 2183 : Pseudo<(outs cls:$R1), (ins imm:$I2), 2184 [(set cls:$R1, (operator imm:$I2))]>; 2185 2186// Like UnaryRXY, but expanded after RA depending on the choice of register. 2187class UnaryRXYPseudo<string key, SDPatternOperator operator, 2188 RegisterOperand cls, bits<5> bytes, 2189 AddressingMode mode = bdxaddr20only> 2190 : Pseudo<(outs cls:$R1), (ins mode:$XBD2), 2191 [(set cls:$R1, (operator mode:$XBD2))]> { 2192 let OpKey = key ## cls; 2193 let OpType = "mem"; 2194 let mayLoad = 1; 2195 let Has20BitOffset = 1; 2196 let HasIndex = 1; 2197 let AccessBytes = bytes; 2198} 2199 2200// Like UnaryRR, but expanded after RA depending on the choice of registers. 2201class UnaryRRPseudo<string key, SDPatternOperator operator, 2202 RegisterOperand cls1, RegisterOperand cls2> 2203 : Pseudo<(outs cls1:$R1), (ins cls2:$R2), 2204 [(set cls1:$R1, (operator cls2:$R2))]> { 2205 let OpKey = key ## cls1; 2206 let OpType = "reg"; 2207} 2208 2209// Like BinaryRI, but expanded after RA depending on the choice of register. 2210class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, 2211 Immediate imm> 2212 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2), 2213 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 2214 let Constraints = "$R1 = $R1src"; 2215} 2216 2217// Like BinaryRIE, but expanded after RA depending on the choice of register. 2218class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls, 2219 Immediate imm> 2220 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2), 2221 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 2222 2223// Like BinaryRIAndK, but expanded after RA depending on the choice of register. 2224multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator, 2225 RegisterOperand cls, Immediate imm> { 2226 let NumOpsKey = key in { 2227 let NumOpsValue = "3" in 2228 def K : BinaryRIEPseudo<null_frag, cls, imm>, 2229 Requires<[FeatureHighWord, FeatureDistinctOps]>; 2230 let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in 2231 def "" : BinaryRIPseudo<operator, cls, imm>, 2232 Requires<[FeatureHighWord]>; 2233 } 2234} 2235 2236// Like CompareRI, but expanded after RA depending on the choice of register. 2237class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls, 2238 Immediate imm> 2239 : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>; 2240 2241// Like CompareRXY, but expanded after RA depending on the choice of register. 2242class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls, 2243 SDPatternOperator load, bits<5> bytes, 2244 AddressingMode mode = bdxaddr20only> 2245 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2), 2246 [(operator cls:$R1, (load mode:$XBD2))]> { 2247 let mayLoad = 1; 2248 let Has20BitOffset = 1; 2249 let HasIndex = 1; 2250 let AccessBytes = bytes; 2251} 2252 2253// Like StoreRXY, but expanded after RA depending on the choice of register. 2254class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls, 2255 bits<5> bytes, AddressingMode mode = bdxaddr20only> 2256 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2), 2257 [(operator cls:$R1, mode:$XBD2)]> { 2258 let mayStore = 1; 2259 let Has20BitOffset = 1; 2260 let HasIndex = 1; 2261 let AccessBytes = bytes; 2262} 2263 2264// Like RotateSelectRIEf, but expanded after RA depending on the choice 2265// of registers. 2266class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2> 2267 : Pseudo<(outs cls1:$R1), 2268 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 2269 imm32zx6:$I5), 2270 []> { 2271 let Constraints = "$R1 = $R1src"; 2272 let DisableEncoding = "$R1src"; 2273} 2274 2275// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is 2276// the value of the PSW's 2-bit condition code field. 2277class SelectWrapper<RegisterOperand cls> 2278 : Pseudo<(outs cls:$dst), 2279 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc), 2280 [(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, 2281 imm32zx4:$valid, imm32zx4:$cc))]> { 2282 let usesCustomInserter = 1; 2283 // Although the instructions used by these nodes do not in themselves 2284 // change CC, the insertion requires new blocks, and CC cannot be live 2285 // across them. 2286 let Defs = [CC]; 2287 let Uses = [CC]; 2288} 2289 2290// Stores $new to $addr if $cc is true ("" case) or false (Inv case). 2291multiclass CondStores<RegisterOperand cls, SDPatternOperator store, 2292 SDPatternOperator load, AddressingMode mode> { 2293 let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in { 2294 def "" : Pseudo<(outs), 2295 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 2296 [(store (z_select_ccmask cls:$new, (load mode:$addr), 2297 imm32zx4:$valid, imm32zx4:$cc), 2298 mode:$addr)]>; 2299 def Inv : Pseudo<(outs), 2300 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 2301 [(store (z_select_ccmask (load mode:$addr), cls:$new, 2302 imm32zx4:$valid, imm32zx4:$cc), 2303 mode:$addr)]>; 2304 } 2305} 2306 2307// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND 2308// describe the second (non-memory) operand. 2309class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls, 2310 dag pat, DAGOperand operand> 2311 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2), 2312 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> { 2313 let Defs = [CC]; 2314 let Has20BitOffset = 1; 2315 let mayLoad = 1; 2316 let mayStore = 1; 2317 let usesCustomInserter = 1; 2318} 2319 2320// Specializations of AtomicLoadWBinary. 2321class AtomicLoadBinaryReg32<SDPatternOperator operator> 2322 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>; 2323class AtomicLoadBinaryImm32<SDPatternOperator operator, Immediate imm> 2324 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>; 2325class AtomicLoadBinaryReg64<SDPatternOperator operator> 2326 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>; 2327class AtomicLoadBinaryImm64<SDPatternOperator operator, Immediate imm> 2328 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>; 2329 2330// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND 2331// describe the second (non-memory) operand. 2332class AtomicLoadWBinary<SDPatternOperator operator, dag pat, 2333 DAGOperand operand> 2334 : Pseudo<(outs GR32:$dst), 2335 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift, 2336 ADDR32:$negbitshift, uimm32:$bitsize), 2337 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift, 2338 ADDR32:$negbitshift, uimm32:$bitsize))]> { 2339 let Defs = [CC]; 2340 let Has20BitOffset = 1; 2341 let mayLoad = 1; 2342 let mayStore = 1; 2343 let usesCustomInserter = 1; 2344} 2345 2346// Specializations of AtomicLoadWBinary. 2347class AtomicLoadWBinaryReg<SDPatternOperator operator> 2348 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>; 2349class AtomicLoadWBinaryImm<SDPatternOperator operator, Immediate imm> 2350 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>; 2351 2352// Define an instruction that operates on two fixed-length blocks of memory, 2353// and associated pseudo instructions for operating on blocks of any size. 2354// The Sequence form uses a straight-line sequence of instructions and 2355// the Loop form uses a loop of length-256 instructions followed by 2356// another instruction to handle the excess. 2357multiclass MemorySS<string mnemonic, bits<8> opcode, 2358 SDPatternOperator sequence, SDPatternOperator loop> { 2359 def "" : InstSS<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, 2360 bdaddr12only:$BD2), 2361 mnemonic##"\t$BDL1, $BD2", []>; 2362 let usesCustomInserter = 1 in { 2363 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 2364 imm64:$length), 2365 [(sequence bdaddr12only:$dest, bdaddr12only:$src, 2366 imm64:$length)]>; 2367 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 2368 imm64:$length, GR64:$count256), 2369 [(loop bdaddr12only:$dest, bdaddr12only:$src, 2370 imm64:$length, GR64:$count256)]>; 2371 } 2372} 2373 2374// Define an instruction that operates on two strings, both terminated 2375// by the character in R0. The instruction processes a CPU-determinated 2376// number of bytes at a time and sets CC to 3 if the instruction needs 2377// to be repeated. Also define a pseudo instruction that represents 2378// the full loop (the main instruction plus the branch on CC==3). 2379multiclass StringRRE<string mnemonic, bits<16> opcode, 2380 SDPatternOperator operator> { 2381 def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2), 2382 (ins GR64:$R1src, GR64:$R2src), 2383 mnemonic#"\t$R1, $R2", []> { 2384 let Uses = [R0L]; 2385 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 2386 let DisableEncoding = "$R1src, $R2src"; 2387 } 2388 let usesCustomInserter = 1 in 2389 def Loop : Pseudo<(outs GR64:$end), 2390 (ins GR64:$start1, GR64:$start2, GR32:$char), 2391 [(set GR64:$end, (operator GR64:$start1, GR64:$start2, 2392 GR32:$char))]>; 2393} 2394 2395// A pseudo instruction that is a direct alias of a real instruction. 2396// These aliases are used in cases where a particular register operand is 2397// fixed or where the same instruction is used with different register sizes. 2398// The size parameter is the size in bytes of the associated real instruction. 2399class Alias<int size, dag outs, dag ins, list<dag> pattern> 2400 : InstSystemZ<size, outs, ins, "", pattern> { 2401 let isPseudo = 1; 2402 let isCodeGenOnly = 1; 2403} 2404 2405class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2> 2406 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>; 2407 2408// An alias of a UnaryVRR*, but with different register sizes. 2409class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2> 2410 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2), 2411 [(set tr1.op:$V1, (tr1.vt (operator (tr2.vt tr2.op:$V2))))]>; 2412 2413// An alias of a UnaryVRX, but with different register sizes. 2414class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr, 2415 AddressingMode mode = bdxaddr12only> 2416 : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2), 2417 [(set tr.op:$V1, (tr.vt (operator mode:$XBD2)))]>; 2418 2419// An alias of a StoreVRX, but with different register sizes. 2420class StoreAliasVRX<SDPatternOperator operator, TypedReg tr, 2421 AddressingMode mode = bdxaddr12only> 2422 : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2), 2423 [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>; 2424 2425// An alias of a BinaryRI, but with different register sizes. 2426class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls, 2427 Immediate imm> 2428 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 2429 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 2430 let Constraints = "$R1 = $R1src"; 2431} 2432 2433// An alias of a BinaryRIL, but with different register sizes. 2434class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls, 2435 Immediate imm> 2436 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 2437 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 2438 let Constraints = "$R1 = $R1src"; 2439} 2440 2441// An alias of a BinaryVRRf, but with different register sizes. 2442class BinaryAliasVRRf<RegisterOperand cls> 2443 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>; 2444 2445// An alias of a CompareRI, but with different register sizes. 2446class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls, 2447 Immediate imm> 2448 : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> { 2449 let isCompare = 1; 2450} 2451 2452// An alias of a RotateSelectRIEf, but with different register sizes. 2453class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2> 2454 : Alias<6, (outs cls1:$R1), 2455 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 2456 imm32zx6:$I5), []> { 2457 let Constraints = "$R1 = $R1src"; 2458} 2459