| /external/vulkan-validation-layers/libs/glm/detail/ |
| D | intrinsic_integer.inl | 41 __m128i Reg2; local
95 __m128i Reg2; local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 792 unsigned Reg2) { in EmitInstrRegReg()
812 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg()
823 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair()
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| D | MipsISelLowering.cpp | 2440 unsigned Reg2 = State.AllocateReg(IntRegs); in CC_MipsO32() local
3022 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), in LowerFormalArguments() local
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 117 unsigned Reg2, bool isKill2) { in addRegReg()
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| D | X86InstrInfo.cpp | 5658 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg(); in foldMemoryOperandImpl() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 739 unsigned Reg2 = CSI[idx + 1].getReg(); in spillCalleeSavedRegisters() local
816 unsigned Reg2 = CSI[i + 1].getReg(); in restoreCalleeSavedRegisters() local
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 662 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
697 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
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| D | A15SDOptimizer.cpp | 469 unsigned Reg1, unsigned Reg2) { in createRegSequence()
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| D | ARMFastISel.cpp | 2782 unsigned Reg2 = 0; in SelectShift() local
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| D | ARMBaseInstrInfo.cpp | 1262 const unsigned &Reg2) -> bool { in expandMEMCPY()
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 378 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1621 StringRef Reg2(R2); in processInstruction() local
1636 StringRef Reg2(R2); in processInstruction() local
1652 StringRef Reg2(R2); in processInstruction() local
1973 StringRef Reg2(R2); in processInstruction() local
2123 StringRef Reg2(R2); in processInstruction() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 838 unsigned Reg2 = MI->getOperand(2).getReg(); in handleSpecialSwappables() local
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| D | PPCInstrInfo.cpp | 350 unsigned Reg2 = MI->getOperand(2).getReg(); in commuteInstructionImpl() local
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 100 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups()
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| D | TargetInstrInfo.cpp | 141 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstructionImpl() local
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| /external/llvm/lib/MC/ |
| D | MCDwarf.cpp | 1035 unsigned Reg2 = Instr.getRegister2(); in EmitCFIInstruction() local
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1132 CodeGenRegister *Reg2 = i1->second; in computeComposites() local
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1488 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, in emitRRR()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 5901 unsigned Reg2 = Op2.getReg(); in ParseInstruction() local
|