1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the ARM-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // ARMGenFastISel.inc, which is #included here.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "ARM.h"
17 #include "ARMBaseRegisterInfo.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/GetElementPtrTypeIterator.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/IR/Operator.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
50 using namespace llvm;
51
52 namespace {
53
54 // All possible address modes, plus some.
55 typedef struct Address {
56 enum {
57 RegBase,
58 FrameIndexBase
59 } BaseType;
60
61 union {
62 unsigned Reg;
63 int FI;
64 } Base;
65
66 int Offset;
67
68 // Innocuous defaults for our address.
Address__anon68c1b2570111::Address69 Address()
70 : BaseType(RegBase), Offset(0) {
71 Base.Reg = 0;
72 }
73 } Address;
74
75 class ARMFastISel final : public FastISel {
76
77 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
78 /// make the right decision when generating code for different targets.
79 const ARMSubtarget *Subtarget;
80 Module &M;
81 const TargetMachine &TM;
82 const TargetInstrInfo &TII;
83 const TargetLowering &TLI;
84 ARMFunctionInfo *AFI;
85
86 // Convenience variables to avoid some queries.
87 bool isThumb2;
88 LLVMContext *Context;
89
90 public:
ARMFastISel(FunctionLoweringInfo & funcInfo,const TargetLibraryInfo * libInfo)91 explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
92 const TargetLibraryInfo *libInfo)
93 : FastISel(funcInfo, libInfo),
94 Subtarget(
95 &static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget())),
96 M(const_cast<Module &>(*funcInfo.Fn->getParent())),
97 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()),
98 TLI(*Subtarget->getTargetLowering()) {
99 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
100 isThumb2 = AFI->isThumbFunction();
101 Context = &funcInfo.Fn->getContext();
102 }
103
104 // Code from FastISel.cpp.
105 private:
106 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
107 const TargetRegisterClass *RC,
108 unsigned Op0, bool Op0IsKill);
109 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
110 const TargetRegisterClass *RC,
111 unsigned Op0, bool Op0IsKill,
112 unsigned Op1, bool Op1IsKill);
113 unsigned fastEmitInst_rrr(unsigned MachineInstOpcode,
114 const TargetRegisterClass *RC,
115 unsigned Op0, bool Op0IsKill,
116 unsigned Op1, bool Op1IsKill,
117 unsigned Op2, bool Op2IsKill);
118 unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill,
121 uint64_t Imm);
122 unsigned fastEmitInst_rri(unsigned MachineInstOpcode,
123 const TargetRegisterClass *RC,
124 unsigned Op0, bool Op0IsKill,
125 unsigned Op1, bool Op1IsKill,
126 uint64_t Imm);
127 unsigned fastEmitInst_i(unsigned MachineInstOpcode,
128 const TargetRegisterClass *RC,
129 uint64_t Imm);
130
131 // Backend specific FastISel code.
132 private:
133 bool fastSelectInstruction(const Instruction *I) override;
134 unsigned fastMaterializeConstant(const Constant *C) override;
135 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
136 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
137 const LoadInst *LI) override;
138 bool fastLowerArguments() override;
139 private:
140 #include "ARMGenFastISel.inc"
141
142 // Instruction selection routines.
143 private:
144 bool SelectLoad(const Instruction *I);
145 bool SelectStore(const Instruction *I);
146 bool SelectBranch(const Instruction *I);
147 bool SelectIndirectBr(const Instruction *I);
148 bool SelectCmp(const Instruction *I);
149 bool SelectFPExt(const Instruction *I);
150 bool SelectFPTrunc(const Instruction *I);
151 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
152 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
153 bool SelectIToFP(const Instruction *I, bool isSigned);
154 bool SelectFPToI(const Instruction *I, bool isSigned);
155 bool SelectDiv(const Instruction *I, bool isSigned);
156 bool SelectRem(const Instruction *I, bool isSigned);
157 bool SelectCall(const Instruction *I, const char *IntrMemName);
158 bool SelectIntrinsicCall(const IntrinsicInst &I);
159 bool SelectSelect(const Instruction *I);
160 bool SelectRet(const Instruction *I);
161 bool SelectTrunc(const Instruction *I);
162 bool SelectIntExt(const Instruction *I);
163 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
164
165 // Utility routines.
166 private:
167 bool isTypeLegal(Type *Ty, MVT &VT);
168 bool isLoadTypeLegal(Type *Ty, MVT &VT);
169 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
170 bool isZExt);
171 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
172 unsigned Alignment = 0, bool isZExt = true,
173 bool allocReg = true);
174 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
175 unsigned Alignment = 0);
176 bool ARMComputeAddress(const Value *Obj, Address &Addr);
177 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
178 bool ARMIsMemCpySmall(uint64_t Len);
179 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
180 unsigned Alignment);
181 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
182 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
183 unsigned ARMMaterializeInt(const Constant *C, MVT VT);
184 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
185 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
186 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
187 unsigned ARMSelectCallOp(bool UseReg);
188 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
189
getTargetLowering()190 const TargetLowering *getTargetLowering() { return &TLI; }
191
192 // Call handling routines.
193 private:
194 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
195 bool Return,
196 bool isVarArg);
197 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
198 SmallVectorImpl<unsigned> &ArgRegs,
199 SmallVectorImpl<MVT> &ArgVTs,
200 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
201 SmallVectorImpl<unsigned> &RegArgs,
202 CallingConv::ID CC,
203 unsigned &NumBytes,
204 bool isVarArg);
205 unsigned getLibcallReg(const Twine &Name);
206 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
207 const Instruction *I, CallingConv::ID CC,
208 unsigned &NumBytes, bool isVarArg);
209 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
210
211 // OptionalDef handling routines.
212 private:
213 bool isARMNEONPred(const MachineInstr *MI);
214 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
215 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
216 void AddLoadStoreOperands(MVT VT, Address &Addr,
217 const MachineInstrBuilder &MIB,
218 unsigned Flags, bool useAM3);
219 };
220
221 } // end anonymous namespace
222
223 #include "ARMGenCallingConv.inc"
224
225 // DefinesOptionalPredicate - This is different from DefinesPredicate in that
226 // we don't care about implicit defs here, just places we'll need to add a
227 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
DefinesOptionalPredicate(MachineInstr * MI,bool * CPSR)228 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
229 if (!MI->hasOptionalDef())
230 return false;
231
232 // Look to see if our OptionalDef is defining CPSR or CCR.
233 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
234 const MachineOperand &MO = MI->getOperand(i);
235 if (!MO.isReg() || !MO.isDef()) continue;
236 if (MO.getReg() == ARM::CPSR)
237 *CPSR = true;
238 }
239 return true;
240 }
241
isARMNEONPred(const MachineInstr * MI)242 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
243 const MCInstrDesc &MCID = MI->getDesc();
244
245 // If we're a thumb2 or not NEON function we'll be handled via isPredicable.
246 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
247 AFI->isThumb2Function())
248 return MI->isPredicable();
249
250 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
251 if (MCID.OpInfo[i].isPredicate())
252 return true;
253
254 return false;
255 }
256
257 // If the machine is predicable go ahead and add the predicate operands, if
258 // it needs default CC operands add those.
259 // TODO: If we want to support thumb1 then we'll need to deal with optional
260 // CPSR defs that need to be added before the remaining operands. See s_cc_out
261 // for descriptions why.
262 const MachineInstrBuilder &
AddOptionalDefs(const MachineInstrBuilder & MIB)263 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
264 MachineInstr *MI = &*MIB;
265
266 // Do we use a predicate? or...
267 // Are we NEON in ARM mode and have a predicate operand? If so, I know
268 // we're not predicable but add it anyways.
269 if (isARMNEONPred(MI))
270 AddDefaultPred(MIB);
271
272 // Do we optionally set a predicate? Preds is size > 0 iff the predicate
273 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
274 bool CPSR = false;
275 if (DefinesOptionalPredicate(MI, &CPSR)) {
276 if (CPSR)
277 AddDefaultT1CC(MIB);
278 else
279 AddDefaultCC(MIB);
280 }
281 return MIB;
282 }
283
fastEmitInst_r(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,bool Op0IsKill)284 unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
285 const TargetRegisterClass *RC,
286 unsigned Op0, bool Op0IsKill) {
287 unsigned ResultReg = createResultReg(RC);
288 const MCInstrDesc &II = TII.get(MachineInstOpcode);
289
290 // Make sure the input operand is sufficiently constrained to be legal
291 // for this instruction.
292 Op0 = constrainOperandRegClass(II, Op0, 1);
293 if (II.getNumDefs() >= 1) {
294 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
295 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
296 } else {
297 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
298 .addReg(Op0, Op0IsKill * RegState::Kill));
299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
300 TII.get(TargetOpcode::COPY), ResultReg)
301 .addReg(II.ImplicitDefs[0]));
302 }
303 return ResultReg;
304 }
305
fastEmitInst_rr(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,bool Op0IsKill,unsigned Op1,bool Op1IsKill)306 unsigned ARMFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
307 const TargetRegisterClass *RC,
308 unsigned Op0, bool Op0IsKill,
309 unsigned Op1, bool Op1IsKill) {
310 unsigned ResultReg = createResultReg(RC);
311 const MCInstrDesc &II = TII.get(MachineInstOpcode);
312
313 // Make sure the input operands are sufficiently constrained to be legal
314 // for this instruction.
315 Op0 = constrainOperandRegClass(II, Op0, 1);
316 Op1 = constrainOperandRegClass(II, Op1, 2);
317
318 if (II.getNumDefs() >= 1) {
319 AddOptionalDefs(
320 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
321 .addReg(Op0, Op0IsKill * RegState::Kill)
322 .addReg(Op1, Op1IsKill * RegState::Kill));
323 } else {
324 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
325 .addReg(Op0, Op0IsKill * RegState::Kill)
326 .addReg(Op1, Op1IsKill * RegState::Kill));
327 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
328 TII.get(TargetOpcode::COPY), ResultReg)
329 .addReg(II.ImplicitDefs[0]));
330 }
331 return ResultReg;
332 }
333
fastEmitInst_rrr(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,bool Op0IsKill,unsigned Op1,bool Op1IsKill,unsigned Op2,bool Op2IsKill)334 unsigned ARMFastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
335 const TargetRegisterClass *RC,
336 unsigned Op0, bool Op0IsKill,
337 unsigned Op1, bool Op1IsKill,
338 unsigned Op2, bool Op2IsKill) {
339 unsigned ResultReg = createResultReg(RC);
340 const MCInstrDesc &II = TII.get(MachineInstOpcode);
341
342 // Make sure the input operands are sufficiently constrained to be legal
343 // for this instruction.
344 Op0 = constrainOperandRegClass(II, Op0, 1);
345 Op1 = constrainOperandRegClass(II, Op1, 2);
346 Op2 = constrainOperandRegClass(II, Op1, 3);
347
348 if (II.getNumDefs() >= 1) {
349 AddOptionalDefs(
350 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
351 .addReg(Op0, Op0IsKill * RegState::Kill)
352 .addReg(Op1, Op1IsKill * RegState::Kill)
353 .addReg(Op2, Op2IsKill * RegState::Kill));
354 } else {
355 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
356 .addReg(Op0, Op0IsKill * RegState::Kill)
357 .addReg(Op1, Op1IsKill * RegState::Kill)
358 .addReg(Op2, Op2IsKill * RegState::Kill));
359 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
360 TII.get(TargetOpcode::COPY), ResultReg)
361 .addReg(II.ImplicitDefs[0]));
362 }
363 return ResultReg;
364 }
365
fastEmitInst_ri(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,bool Op0IsKill,uint64_t Imm)366 unsigned ARMFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
367 const TargetRegisterClass *RC,
368 unsigned Op0, bool Op0IsKill,
369 uint64_t Imm) {
370 unsigned ResultReg = createResultReg(RC);
371 const MCInstrDesc &II = TII.get(MachineInstOpcode);
372
373 // Make sure the input operand is sufficiently constrained to be legal
374 // for this instruction.
375 Op0 = constrainOperandRegClass(II, Op0, 1);
376 if (II.getNumDefs() >= 1) {
377 AddOptionalDefs(
378 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
379 .addReg(Op0, Op0IsKill * RegState::Kill)
380 .addImm(Imm));
381 } else {
382 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
383 .addReg(Op0, Op0IsKill * RegState::Kill)
384 .addImm(Imm));
385 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
386 TII.get(TargetOpcode::COPY), ResultReg)
387 .addReg(II.ImplicitDefs[0]));
388 }
389 return ResultReg;
390 }
391
fastEmitInst_rri(unsigned MachineInstOpcode,const TargetRegisterClass * RC,unsigned Op0,bool Op0IsKill,unsigned Op1,bool Op1IsKill,uint64_t Imm)392 unsigned ARMFastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
393 const TargetRegisterClass *RC,
394 unsigned Op0, bool Op0IsKill,
395 unsigned Op1, bool Op1IsKill,
396 uint64_t Imm) {
397 unsigned ResultReg = createResultReg(RC);
398 const MCInstrDesc &II = TII.get(MachineInstOpcode);
399
400 // Make sure the input operands are sufficiently constrained to be legal
401 // for this instruction.
402 Op0 = constrainOperandRegClass(II, Op0, 1);
403 Op1 = constrainOperandRegClass(II, Op1, 2);
404 if (II.getNumDefs() >= 1) {
405 AddOptionalDefs(
406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
407 .addReg(Op0, Op0IsKill * RegState::Kill)
408 .addReg(Op1, Op1IsKill * RegState::Kill)
409 .addImm(Imm));
410 } else {
411 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
412 .addReg(Op0, Op0IsKill * RegState::Kill)
413 .addReg(Op1, Op1IsKill * RegState::Kill)
414 .addImm(Imm));
415 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
416 TII.get(TargetOpcode::COPY), ResultReg)
417 .addReg(II.ImplicitDefs[0]));
418 }
419 return ResultReg;
420 }
421
fastEmitInst_i(unsigned MachineInstOpcode,const TargetRegisterClass * RC,uint64_t Imm)422 unsigned ARMFastISel::fastEmitInst_i(unsigned MachineInstOpcode,
423 const TargetRegisterClass *RC,
424 uint64_t Imm) {
425 unsigned ResultReg = createResultReg(RC);
426 const MCInstrDesc &II = TII.get(MachineInstOpcode);
427
428 if (II.getNumDefs() >= 1) {
429 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
430 ResultReg).addImm(Imm));
431 } else {
432 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
433 .addImm(Imm));
434 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
435 TII.get(TargetOpcode::COPY), ResultReg)
436 .addReg(II.ImplicitDefs[0]));
437 }
438 return ResultReg;
439 }
440
441 // TODO: Don't worry about 64-bit now, but when this is fixed remove the
442 // checks from the various callers.
ARMMoveToFPReg(MVT VT,unsigned SrcReg)443 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
444 if (VT == MVT::f64) return 0;
445
446 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
447 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
448 TII.get(ARM::VMOVSR), MoveReg)
449 .addReg(SrcReg));
450 return MoveReg;
451 }
452
ARMMoveToIntReg(MVT VT,unsigned SrcReg)453 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
454 if (VT == MVT::i64) return 0;
455
456 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
457 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
458 TII.get(ARM::VMOVRS), MoveReg)
459 .addReg(SrcReg));
460 return MoveReg;
461 }
462
463 // For double width floating point we need to materialize two constants
464 // (the high and the low) into integer registers then use a move to get
465 // the combined constant into an FP reg.
ARMMaterializeFP(const ConstantFP * CFP,MVT VT)466 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
467 const APFloat Val = CFP->getValueAPF();
468 bool is64bit = VT == MVT::f64;
469
470 // This checks to see if we can use VFP3 instructions to materialize
471 // a constant, otherwise we have to go through the constant pool.
472 if (TLI.isFPImmLegal(Val, VT)) {
473 int Imm;
474 unsigned Opc;
475 if (is64bit) {
476 Imm = ARM_AM::getFP64Imm(Val);
477 Opc = ARM::FCONSTD;
478 } else {
479 Imm = ARM_AM::getFP32Imm(Val);
480 Opc = ARM::FCONSTS;
481 }
482 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
483 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
484 TII.get(Opc), DestReg).addImm(Imm));
485 return DestReg;
486 }
487
488 // Require VFP2 for loading fp constants.
489 if (!Subtarget->hasVFP2()) return false;
490
491 // MachineConstantPool wants an explicit alignment.
492 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
493 if (Align == 0) {
494 // TODO: Figure out if this is correct.
495 Align = DL.getTypeAllocSize(CFP->getType());
496 }
497 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
498 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
499 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
500
501 // The extra reg is for addrmode5.
502 AddOptionalDefs(
503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
504 .addConstantPoolIndex(Idx)
505 .addReg(0));
506 return DestReg;
507 }
508
ARMMaterializeInt(const Constant * C,MVT VT)509 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
510
511 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
512 return 0;
513
514 // If we can do this in a single instruction without a constant pool entry
515 // do so now.
516 const ConstantInt *CI = cast<ConstantInt>(C);
517 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
518 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
519 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
520 &ARM::GPRRegClass;
521 unsigned ImmReg = createResultReg(RC);
522 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
523 TII.get(Opc), ImmReg)
524 .addImm(CI->getZExtValue()));
525 return ImmReg;
526 }
527
528 // Use MVN to emit negative constants.
529 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
530 unsigned Imm = (unsigned)~(CI->getSExtValue());
531 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
532 (ARM_AM::getSOImmVal(Imm) != -1);
533 if (UseImm) {
534 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
535 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
536 &ARM::GPRRegClass;
537 unsigned ImmReg = createResultReg(RC);
538 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
539 TII.get(Opc), ImmReg)
540 .addImm(Imm));
541 return ImmReg;
542 }
543 }
544
545 unsigned ResultReg = 0;
546 if (Subtarget->useMovt(*FuncInfo.MF))
547 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
548
549 if (ResultReg)
550 return ResultReg;
551
552 // Load from constant pool. For now 32-bit only.
553 if (VT != MVT::i32)
554 return 0;
555
556 // MachineConstantPool wants an explicit alignment.
557 unsigned Align = DL.getPrefTypeAlignment(C->getType());
558 if (Align == 0) {
559 // TODO: Figure out if this is correct.
560 Align = DL.getTypeAllocSize(C->getType());
561 }
562 unsigned Idx = MCP.getConstantPoolIndex(C, Align);
563 ResultReg = createResultReg(TLI.getRegClassFor(VT));
564 if (isThumb2)
565 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
566 TII.get(ARM::t2LDRpci), ResultReg)
567 .addConstantPoolIndex(Idx));
568 else {
569 // The extra immediate is for addrmode2.
570 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
571 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
572 TII.get(ARM::LDRcp), ResultReg)
573 .addConstantPoolIndex(Idx)
574 .addImm(0));
575 }
576 return ResultReg;
577 }
578
ARMMaterializeGV(const GlobalValue * GV,MVT VT)579 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
580 // For now 32-bit only.
581 if (VT != MVT::i32) return 0;
582
583 Reloc::Model RelocM = TM.getRelocationModel();
584 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
585 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
586 : &ARM::GPRRegClass;
587 unsigned DestReg = createResultReg(RC);
588
589 // FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
590 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
591 bool IsThreadLocal = GVar && GVar->isThreadLocal();
592 if (!Subtarget->isTargetMachO() && IsThreadLocal) return 0;
593
594 // Use movw+movt when possible, it avoids constant pool entries.
595 // Non-darwin targets only support static movt relocations in FastISel.
596 if (Subtarget->useMovt(*FuncInfo.MF) &&
597 (Subtarget->isTargetMachO() || RelocM == Reloc::Static)) {
598 unsigned Opc;
599 unsigned char TF = 0;
600 if (Subtarget->isTargetMachO())
601 TF = ARMII::MO_NONLAZY;
602
603 switch (RelocM) {
604 case Reloc::PIC_:
605 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
606 break;
607 default:
608 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
609 break;
610 }
611 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
612 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
613 } else {
614 // MachineConstantPool wants an explicit alignment.
615 unsigned Align = DL.getPrefTypeAlignment(GV->getType());
616 if (Align == 0) {
617 // TODO: Figure out if this is correct.
618 Align = DL.getTypeAllocSize(GV->getType());
619 }
620
621 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
622 return ARMLowerPICELF(GV, Align, VT);
623
624 // Grab index.
625 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
626 (Subtarget->isThumb() ? 4 : 8);
627 unsigned Id = AFI->createPICLabelUId();
628 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
629 ARMCP::CPValue,
630 PCAdj);
631 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
632
633 // Load value.
634 MachineInstrBuilder MIB;
635 if (isThumb2) {
636 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
637 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
638 DestReg).addConstantPoolIndex(Idx);
639 if (RelocM == Reloc::PIC_)
640 MIB.addImm(Id);
641 AddOptionalDefs(MIB);
642 } else {
643 // The extra immediate is for addrmode2.
644 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
645 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
646 TII.get(ARM::LDRcp), DestReg)
647 .addConstantPoolIndex(Idx)
648 .addImm(0);
649 AddOptionalDefs(MIB);
650
651 if (RelocM == Reloc::PIC_) {
652 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
653 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
654
655 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
656 DbgLoc, TII.get(Opc), NewDestReg)
657 .addReg(DestReg)
658 .addImm(Id);
659 AddOptionalDefs(MIB);
660 return NewDestReg;
661 }
662 }
663 }
664
665 if (IsIndirect) {
666 MachineInstrBuilder MIB;
667 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
668 if (isThumb2)
669 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
670 TII.get(ARM::t2LDRi12), NewDestReg)
671 .addReg(DestReg)
672 .addImm(0);
673 else
674 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
675 TII.get(ARM::LDRi12), NewDestReg)
676 .addReg(DestReg)
677 .addImm(0);
678 DestReg = NewDestReg;
679 AddOptionalDefs(MIB);
680 }
681
682 return DestReg;
683 }
684
fastMaterializeConstant(const Constant * C)685 unsigned ARMFastISel::fastMaterializeConstant(const Constant *C) {
686 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
687
688 // Only handle simple types.
689 if (!CEVT.isSimple()) return 0;
690 MVT VT = CEVT.getSimpleVT();
691
692 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
693 return ARMMaterializeFP(CFP, VT);
694 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
695 return ARMMaterializeGV(GV, VT);
696 else if (isa<ConstantInt>(C))
697 return ARMMaterializeInt(C, VT);
698
699 return 0;
700 }
701
702 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
703
fastMaterializeAlloca(const AllocaInst * AI)704 unsigned ARMFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
705 // Don't handle dynamic allocas.
706 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
707
708 MVT VT;
709 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
710
711 DenseMap<const AllocaInst*, int>::iterator SI =
712 FuncInfo.StaticAllocaMap.find(AI);
713
714 // This will get lowered later into the correct offsets and registers
715 // via rewriteXFrameIndex.
716 if (SI != FuncInfo.StaticAllocaMap.end()) {
717 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
718 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
719 unsigned ResultReg = createResultReg(RC);
720 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
721
722 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
723 TII.get(Opc), ResultReg)
724 .addFrameIndex(SI->second)
725 .addImm(0));
726 return ResultReg;
727 }
728
729 return 0;
730 }
731
isTypeLegal(Type * Ty,MVT & VT)732 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
733 EVT evt = TLI.getValueType(DL, Ty, true);
734
735 // Only handle simple types.
736 if (evt == MVT::Other || !evt.isSimple()) return false;
737 VT = evt.getSimpleVT();
738
739 // Handle all legal types, i.e. a register that will directly hold this
740 // value.
741 return TLI.isTypeLegal(VT);
742 }
743
isLoadTypeLegal(Type * Ty,MVT & VT)744 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
745 if (isTypeLegal(Ty, VT)) return true;
746
747 // If this is a type than can be sign or zero-extended to a basic operation
748 // go ahead and accept it now.
749 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
750 return true;
751
752 return false;
753 }
754
755 // Computes the address to get to an object.
ARMComputeAddress(const Value * Obj,Address & Addr)756 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
757 // Some boilerplate from the X86 FastISel.
758 const User *U = nullptr;
759 unsigned Opcode = Instruction::UserOp1;
760 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
761 // Don't walk into other basic blocks unless the object is an alloca from
762 // another block, otherwise it may not have a virtual register assigned.
763 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
764 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
765 Opcode = I->getOpcode();
766 U = I;
767 }
768 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
769 Opcode = C->getOpcode();
770 U = C;
771 }
772
773 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
774 if (Ty->getAddressSpace() > 255)
775 // Fast instruction selection doesn't support the special
776 // address spaces.
777 return false;
778
779 switch (Opcode) {
780 default:
781 break;
782 case Instruction::BitCast:
783 // Look through bitcasts.
784 return ARMComputeAddress(U->getOperand(0), Addr);
785 case Instruction::IntToPtr:
786 // Look past no-op inttoptrs.
787 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
788 TLI.getPointerTy(DL))
789 return ARMComputeAddress(U->getOperand(0), Addr);
790 break;
791 case Instruction::PtrToInt:
792 // Look past no-op ptrtoints.
793 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
794 return ARMComputeAddress(U->getOperand(0), Addr);
795 break;
796 case Instruction::GetElementPtr: {
797 Address SavedAddr = Addr;
798 int TmpOffset = Addr.Offset;
799
800 // Iterate through the GEP folding the constants into offsets where
801 // we can.
802 gep_type_iterator GTI = gep_type_begin(U);
803 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
804 i != e; ++i, ++GTI) {
805 const Value *Op = *i;
806 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
807 const StructLayout *SL = DL.getStructLayout(STy);
808 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
809 TmpOffset += SL->getElementOffset(Idx);
810 } else {
811 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
812 for (;;) {
813 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
814 // Constant-offset addressing.
815 TmpOffset += CI->getSExtValue() * S;
816 break;
817 }
818 if (canFoldAddIntoGEP(U, Op)) {
819 // A compatible add with a constant operand. Fold the constant.
820 ConstantInt *CI =
821 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
822 TmpOffset += CI->getSExtValue() * S;
823 // Iterate on the other operand.
824 Op = cast<AddOperator>(Op)->getOperand(0);
825 continue;
826 }
827 // Unsupported
828 goto unsupported_gep;
829 }
830 }
831 }
832
833 // Try to grab the base operand now.
834 Addr.Offset = TmpOffset;
835 if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
836
837 // We failed, restore everything and try the other options.
838 Addr = SavedAddr;
839
840 unsupported_gep:
841 break;
842 }
843 case Instruction::Alloca: {
844 const AllocaInst *AI = cast<AllocaInst>(Obj);
845 DenseMap<const AllocaInst*, int>::iterator SI =
846 FuncInfo.StaticAllocaMap.find(AI);
847 if (SI != FuncInfo.StaticAllocaMap.end()) {
848 Addr.BaseType = Address::FrameIndexBase;
849 Addr.Base.FI = SI->second;
850 return true;
851 }
852 break;
853 }
854 }
855
856 // Try to get this in a register if nothing else has worked.
857 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
858 return Addr.Base.Reg != 0;
859 }
860
ARMSimplifyAddress(Address & Addr,MVT VT,bool useAM3)861 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
862 bool needsLowering = false;
863 switch (VT.SimpleTy) {
864 default: llvm_unreachable("Unhandled load/store type!");
865 case MVT::i1:
866 case MVT::i8:
867 case MVT::i16:
868 case MVT::i32:
869 if (!useAM3) {
870 // Integer loads/stores handle 12-bit offsets.
871 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
872 // Handle negative offsets.
873 if (needsLowering && isThumb2)
874 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
875 Addr.Offset > -256);
876 } else {
877 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
878 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
879 }
880 break;
881 case MVT::f32:
882 case MVT::f64:
883 // Floating point operands handle 8-bit offsets.
884 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
885 break;
886 }
887
888 // If this is a stack pointer and the offset needs to be simplified then
889 // put the alloca address into a register, set the base type back to
890 // register and continue. This should almost never happen.
891 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
892 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
893 : &ARM::GPRRegClass;
894 unsigned ResultReg = createResultReg(RC);
895 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
896 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
897 TII.get(Opc), ResultReg)
898 .addFrameIndex(Addr.Base.FI)
899 .addImm(0));
900 Addr.Base.Reg = ResultReg;
901 Addr.BaseType = Address::RegBase;
902 }
903
904 // Since the offset is too large for the load/store instruction
905 // get the reg+offset into a register.
906 if (needsLowering) {
907 Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
908 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
909 Addr.Offset = 0;
910 }
911 }
912
AddLoadStoreOperands(MVT VT,Address & Addr,const MachineInstrBuilder & MIB,unsigned Flags,bool useAM3)913 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
914 const MachineInstrBuilder &MIB,
915 unsigned Flags, bool useAM3) {
916 // addrmode5 output depends on the selection dag addressing dividing the
917 // offset by 4 that it then later multiplies. Do this here as well.
918 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
919 Addr.Offset /= 4;
920
921 // Frame base works a bit differently. Handle it separately.
922 if (Addr.BaseType == Address::FrameIndexBase) {
923 int FI = Addr.Base.FI;
924 int Offset = Addr.Offset;
925 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
926 MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags,
927 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
928 // Now add the rest of the operands.
929 MIB.addFrameIndex(FI);
930
931 // ARM halfword load/stores and signed byte loads need an additional
932 // operand.
933 if (useAM3) {
934 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
935 MIB.addReg(0);
936 MIB.addImm(Imm);
937 } else {
938 MIB.addImm(Addr.Offset);
939 }
940 MIB.addMemOperand(MMO);
941 } else {
942 // Now add the rest of the operands.
943 MIB.addReg(Addr.Base.Reg);
944
945 // ARM halfword load/stores and signed byte loads need an additional
946 // operand.
947 if (useAM3) {
948 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
949 MIB.addReg(0);
950 MIB.addImm(Imm);
951 } else {
952 MIB.addImm(Addr.Offset);
953 }
954 }
955 AddOptionalDefs(MIB);
956 }
957
ARMEmitLoad(MVT VT,unsigned & ResultReg,Address & Addr,unsigned Alignment,bool isZExt,bool allocReg)958 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
959 unsigned Alignment, bool isZExt, bool allocReg) {
960 unsigned Opc;
961 bool useAM3 = false;
962 bool needVMOV = false;
963 const TargetRegisterClass *RC;
964 switch (VT.SimpleTy) {
965 // This is mostly going to be Neon/vector support.
966 default: return false;
967 case MVT::i1:
968 case MVT::i8:
969 if (isThumb2) {
970 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
971 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
972 else
973 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
974 } else {
975 if (isZExt) {
976 Opc = ARM::LDRBi12;
977 } else {
978 Opc = ARM::LDRSB;
979 useAM3 = true;
980 }
981 }
982 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
983 break;
984 case MVT::i16:
985 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
986 return false;
987
988 if (isThumb2) {
989 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
990 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
991 else
992 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
993 } else {
994 Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
995 useAM3 = true;
996 }
997 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
998 break;
999 case MVT::i32:
1000 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1001 return false;
1002
1003 if (isThumb2) {
1004 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1005 Opc = ARM::t2LDRi8;
1006 else
1007 Opc = ARM::t2LDRi12;
1008 } else {
1009 Opc = ARM::LDRi12;
1010 }
1011 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1012 break;
1013 case MVT::f32:
1014 if (!Subtarget->hasVFP2()) return false;
1015 // Unaligned loads need special handling. Floats require word-alignment.
1016 if (Alignment && Alignment < 4) {
1017 needVMOV = true;
1018 VT = MVT::i32;
1019 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1020 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1021 } else {
1022 Opc = ARM::VLDRS;
1023 RC = TLI.getRegClassFor(VT);
1024 }
1025 break;
1026 case MVT::f64:
1027 if (!Subtarget->hasVFP2()) return false;
1028 // FIXME: Unaligned loads need special handling. Doublewords require
1029 // word-alignment.
1030 if (Alignment && Alignment < 4)
1031 return false;
1032
1033 Opc = ARM::VLDRD;
1034 RC = TLI.getRegClassFor(VT);
1035 break;
1036 }
1037 // Simplify this down to something we can handle.
1038 ARMSimplifyAddress(Addr, VT, useAM3);
1039
1040 // Create the base instruction, then add the operands.
1041 if (allocReg)
1042 ResultReg = createResultReg(RC);
1043 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1044 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1045 TII.get(Opc), ResultReg);
1046 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1047
1048 // If we had an unaligned load of a float we've converted it to an regular
1049 // load. Now we must move from the GRP to the FP register.
1050 if (needVMOV) {
1051 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1052 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1053 TII.get(ARM::VMOVSR), MoveReg)
1054 .addReg(ResultReg));
1055 ResultReg = MoveReg;
1056 }
1057 return true;
1058 }
1059
SelectLoad(const Instruction * I)1060 bool ARMFastISel::SelectLoad(const Instruction *I) {
1061 // Atomic loads need special handling.
1062 if (cast<LoadInst>(I)->isAtomic())
1063 return false;
1064
1065 // Verify we have a legal type before going any further.
1066 MVT VT;
1067 if (!isLoadTypeLegal(I->getType(), VT))
1068 return false;
1069
1070 // See if we can handle this address.
1071 Address Addr;
1072 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1073
1074 unsigned ResultReg;
1075 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1076 return false;
1077 updateValueMap(I, ResultReg);
1078 return true;
1079 }
1080
ARMEmitStore(MVT VT,unsigned SrcReg,Address & Addr,unsigned Alignment)1081 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1082 unsigned Alignment) {
1083 unsigned StrOpc;
1084 bool useAM3 = false;
1085 switch (VT.SimpleTy) {
1086 // This is mostly going to be Neon/vector support.
1087 default: return false;
1088 case MVT::i1: {
1089 unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
1090 : &ARM::GPRRegClass);
1091 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1092 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1093 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1094 TII.get(Opc), Res)
1095 .addReg(SrcReg).addImm(1));
1096 SrcReg = Res;
1097 } // Fallthrough here.
1098 case MVT::i8:
1099 if (isThumb2) {
1100 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1101 StrOpc = ARM::t2STRBi8;
1102 else
1103 StrOpc = ARM::t2STRBi12;
1104 } else {
1105 StrOpc = ARM::STRBi12;
1106 }
1107 break;
1108 case MVT::i16:
1109 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1110 return false;
1111
1112 if (isThumb2) {
1113 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1114 StrOpc = ARM::t2STRHi8;
1115 else
1116 StrOpc = ARM::t2STRHi12;
1117 } else {
1118 StrOpc = ARM::STRH;
1119 useAM3 = true;
1120 }
1121 break;
1122 case MVT::i32:
1123 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1124 return false;
1125
1126 if (isThumb2) {
1127 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1128 StrOpc = ARM::t2STRi8;
1129 else
1130 StrOpc = ARM::t2STRi12;
1131 } else {
1132 StrOpc = ARM::STRi12;
1133 }
1134 break;
1135 case MVT::f32:
1136 if (!Subtarget->hasVFP2()) return false;
1137 // Unaligned stores need special handling. Floats require word-alignment.
1138 if (Alignment && Alignment < 4) {
1139 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1140 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1141 TII.get(ARM::VMOVRS), MoveReg)
1142 .addReg(SrcReg));
1143 SrcReg = MoveReg;
1144 VT = MVT::i32;
1145 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1146 } else {
1147 StrOpc = ARM::VSTRS;
1148 }
1149 break;
1150 case MVT::f64:
1151 if (!Subtarget->hasVFP2()) return false;
1152 // FIXME: Unaligned stores need special handling. Doublewords require
1153 // word-alignment.
1154 if (Alignment && Alignment < 4)
1155 return false;
1156
1157 StrOpc = ARM::VSTRD;
1158 break;
1159 }
1160 // Simplify this down to something we can handle.
1161 ARMSimplifyAddress(Addr, VT, useAM3);
1162
1163 // Create the base instruction, then add the operands.
1164 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1165 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1166 TII.get(StrOpc))
1167 .addReg(SrcReg);
1168 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1169 return true;
1170 }
1171
SelectStore(const Instruction * I)1172 bool ARMFastISel::SelectStore(const Instruction *I) {
1173 Value *Op0 = I->getOperand(0);
1174 unsigned SrcReg = 0;
1175
1176 // Atomic stores need special handling.
1177 if (cast<StoreInst>(I)->isAtomic())
1178 return false;
1179
1180 // Verify we have a legal type before going any further.
1181 MVT VT;
1182 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1183 return false;
1184
1185 // Get the value to be stored into a register.
1186 SrcReg = getRegForValue(Op0);
1187 if (SrcReg == 0) return false;
1188
1189 // See if we can handle this address.
1190 Address Addr;
1191 if (!ARMComputeAddress(I->getOperand(1), Addr))
1192 return false;
1193
1194 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1195 return false;
1196 return true;
1197 }
1198
getComparePred(CmpInst::Predicate Pred)1199 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1200 switch (Pred) {
1201 // Needs two compares...
1202 case CmpInst::FCMP_ONE:
1203 case CmpInst::FCMP_UEQ:
1204 default:
1205 // AL is our "false" for now. The other two need more compares.
1206 return ARMCC::AL;
1207 case CmpInst::ICMP_EQ:
1208 case CmpInst::FCMP_OEQ:
1209 return ARMCC::EQ;
1210 case CmpInst::ICMP_SGT:
1211 case CmpInst::FCMP_OGT:
1212 return ARMCC::GT;
1213 case CmpInst::ICMP_SGE:
1214 case CmpInst::FCMP_OGE:
1215 return ARMCC::GE;
1216 case CmpInst::ICMP_UGT:
1217 case CmpInst::FCMP_UGT:
1218 return ARMCC::HI;
1219 case CmpInst::FCMP_OLT:
1220 return ARMCC::MI;
1221 case CmpInst::ICMP_ULE:
1222 case CmpInst::FCMP_OLE:
1223 return ARMCC::LS;
1224 case CmpInst::FCMP_ORD:
1225 return ARMCC::VC;
1226 case CmpInst::FCMP_UNO:
1227 return ARMCC::VS;
1228 case CmpInst::FCMP_UGE:
1229 return ARMCC::PL;
1230 case CmpInst::ICMP_SLT:
1231 case CmpInst::FCMP_ULT:
1232 return ARMCC::LT;
1233 case CmpInst::ICMP_SLE:
1234 case CmpInst::FCMP_ULE:
1235 return ARMCC::LE;
1236 case CmpInst::FCMP_UNE:
1237 case CmpInst::ICMP_NE:
1238 return ARMCC::NE;
1239 case CmpInst::ICMP_UGE:
1240 return ARMCC::HS;
1241 case CmpInst::ICMP_ULT:
1242 return ARMCC::LO;
1243 }
1244 }
1245
SelectBranch(const Instruction * I)1246 bool ARMFastISel::SelectBranch(const Instruction *I) {
1247 const BranchInst *BI = cast<BranchInst>(I);
1248 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1249 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1250
1251 // Simple branch support.
1252
1253 // If we can, avoid recomputing the compare - redoing it could lead to wonky
1254 // behavior.
1255 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1256 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1257
1258 // Get the compare predicate.
1259 // Try to take advantage of fallthrough opportunities.
1260 CmpInst::Predicate Predicate = CI->getPredicate();
1261 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1262 std::swap(TBB, FBB);
1263 Predicate = CmpInst::getInversePredicate(Predicate);
1264 }
1265
1266 ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1267
1268 // We may not handle every CC for now.
1269 if (ARMPred == ARMCC::AL) return false;
1270
1271 // Emit the compare.
1272 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1273 return false;
1274
1275 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1276 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1277 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1278 finishCondBranch(BI->getParent(), TBB, FBB);
1279 return true;
1280 }
1281 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1282 MVT SourceVT;
1283 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1284 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1285 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1286 unsigned OpReg = getRegForValue(TI->getOperand(0));
1287 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1288 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1289 TII.get(TstOpc))
1290 .addReg(OpReg).addImm(1));
1291
1292 unsigned CCMode = ARMCC::NE;
1293 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1294 std::swap(TBB, FBB);
1295 CCMode = ARMCC::EQ;
1296 }
1297
1298 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1299 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1300 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1301
1302 finishCondBranch(BI->getParent(), TBB, FBB);
1303 return true;
1304 }
1305 } else if (const ConstantInt *CI =
1306 dyn_cast<ConstantInt>(BI->getCondition())) {
1307 uint64_t Imm = CI->getZExtValue();
1308 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1309 fastEmitBranch(Target, DbgLoc);
1310 return true;
1311 }
1312
1313 unsigned CmpReg = getRegForValue(BI->getCondition());
1314 if (CmpReg == 0) return false;
1315
1316 // We've been divorced from our compare! Our block was split, and
1317 // now our compare lives in a predecessor block. We musn't
1318 // re-compare here, as the children of the compare aren't guaranteed
1319 // live across the block boundary (we *could* check for this).
1320 // Regardless, the compare has been done in the predecessor block,
1321 // and it left a value for us in a virtual register. Ergo, we test
1322 // the one-bit value left in the virtual register.
1323 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1324 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1325 AddOptionalDefs(
1326 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1327 .addReg(CmpReg)
1328 .addImm(1));
1329
1330 unsigned CCMode = ARMCC::NE;
1331 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1332 std::swap(TBB, FBB);
1333 CCMode = ARMCC::EQ;
1334 }
1335
1336 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1337 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1338 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1339 finishCondBranch(BI->getParent(), TBB, FBB);
1340 return true;
1341 }
1342
SelectIndirectBr(const Instruction * I)1343 bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1344 unsigned AddrReg = getRegForValue(I->getOperand(0));
1345 if (AddrReg == 0) return false;
1346
1347 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1348 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1349 TII.get(Opc)).addReg(AddrReg));
1350
1351 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1352 for (const BasicBlock *SuccBB : IB->successors())
1353 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1354
1355 return true;
1356 }
1357
ARMEmitCmp(const Value * Src1Value,const Value * Src2Value,bool isZExt)1358 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1359 bool isZExt) {
1360 Type *Ty = Src1Value->getType();
1361 EVT SrcEVT = TLI.getValueType(DL, Ty, true);
1362 if (!SrcEVT.isSimple()) return false;
1363 MVT SrcVT = SrcEVT.getSimpleVT();
1364
1365 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1366 if (isFloat && !Subtarget->hasVFP2())
1367 return false;
1368
1369 // Check to see if the 2nd operand is a constant that we can encode directly
1370 // in the compare.
1371 int Imm = 0;
1372 bool UseImm = false;
1373 bool isNegativeImm = false;
1374 // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1375 // Thus, Src1Value may be a ConstantInt, but we're missing it.
1376 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1377 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1378 SrcVT == MVT::i1) {
1379 const APInt &CIVal = ConstInt->getValue();
1380 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1381 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1382 // then a cmn, because there is no way to represent 2147483648 as a
1383 // signed 32-bit int.
1384 if (Imm < 0 && Imm != (int)0x80000000) {
1385 isNegativeImm = true;
1386 Imm = -Imm;
1387 }
1388 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1389 (ARM_AM::getSOImmVal(Imm) != -1);
1390 }
1391 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1392 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1393 if (ConstFP->isZero() && !ConstFP->isNegative())
1394 UseImm = true;
1395 }
1396
1397 unsigned CmpOpc;
1398 bool isICmp = true;
1399 bool needsExt = false;
1400 switch (SrcVT.SimpleTy) {
1401 default: return false;
1402 // TODO: Verify compares.
1403 case MVT::f32:
1404 isICmp = false;
1405 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1406 break;
1407 case MVT::f64:
1408 isICmp = false;
1409 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1410 break;
1411 case MVT::i1:
1412 case MVT::i8:
1413 case MVT::i16:
1414 needsExt = true;
1415 // Intentional fall-through.
1416 case MVT::i32:
1417 if (isThumb2) {
1418 if (!UseImm)
1419 CmpOpc = ARM::t2CMPrr;
1420 else
1421 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1422 } else {
1423 if (!UseImm)
1424 CmpOpc = ARM::CMPrr;
1425 else
1426 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1427 }
1428 break;
1429 }
1430
1431 unsigned SrcReg1 = getRegForValue(Src1Value);
1432 if (SrcReg1 == 0) return false;
1433
1434 unsigned SrcReg2 = 0;
1435 if (!UseImm) {
1436 SrcReg2 = getRegForValue(Src2Value);
1437 if (SrcReg2 == 0) return false;
1438 }
1439
1440 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1441 if (needsExt) {
1442 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1443 if (SrcReg1 == 0) return false;
1444 if (!UseImm) {
1445 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1446 if (SrcReg2 == 0) return false;
1447 }
1448 }
1449
1450 const MCInstrDesc &II = TII.get(CmpOpc);
1451 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1452 if (!UseImm) {
1453 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1454 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1455 .addReg(SrcReg1).addReg(SrcReg2));
1456 } else {
1457 MachineInstrBuilder MIB;
1458 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1459 .addReg(SrcReg1);
1460
1461 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1462 if (isICmp)
1463 MIB.addImm(Imm);
1464 AddOptionalDefs(MIB);
1465 }
1466
1467 // For floating point we need to move the result to a comparison register
1468 // that we can then use for branches.
1469 if (Ty->isFloatTy() || Ty->isDoubleTy())
1470 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1471 TII.get(ARM::FMSTAT)));
1472 return true;
1473 }
1474
SelectCmp(const Instruction * I)1475 bool ARMFastISel::SelectCmp(const Instruction *I) {
1476 const CmpInst *CI = cast<CmpInst>(I);
1477
1478 // Get the compare predicate.
1479 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1480
1481 // We may not handle every CC for now.
1482 if (ARMPred == ARMCC::AL) return false;
1483
1484 // Emit the compare.
1485 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1486 return false;
1487
1488 // Now set a register based on the comparison. Explicitly set the predicates
1489 // here.
1490 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1491 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1492 : &ARM::GPRRegClass;
1493 unsigned DestReg = createResultReg(RC);
1494 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1495 unsigned ZeroReg = fastMaterializeConstant(Zero);
1496 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1497 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1498 .addReg(ZeroReg).addImm(1)
1499 .addImm(ARMPred).addReg(ARM::CPSR);
1500
1501 updateValueMap(I, DestReg);
1502 return true;
1503 }
1504
SelectFPExt(const Instruction * I)1505 bool ARMFastISel::SelectFPExt(const Instruction *I) {
1506 // Make sure we have VFP and that we're extending float to double.
1507 if (!Subtarget->hasVFP2()) return false;
1508
1509 Value *V = I->getOperand(0);
1510 if (!I->getType()->isDoubleTy() ||
1511 !V->getType()->isFloatTy()) return false;
1512
1513 unsigned Op = getRegForValue(V);
1514 if (Op == 0) return false;
1515
1516 unsigned Result = createResultReg(&ARM::DPRRegClass);
1517 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1518 TII.get(ARM::VCVTDS), Result)
1519 .addReg(Op));
1520 updateValueMap(I, Result);
1521 return true;
1522 }
1523
SelectFPTrunc(const Instruction * I)1524 bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1525 // Make sure we have VFP and that we're truncating double to float.
1526 if (!Subtarget->hasVFP2()) return false;
1527
1528 Value *V = I->getOperand(0);
1529 if (!(I->getType()->isFloatTy() &&
1530 V->getType()->isDoubleTy())) return false;
1531
1532 unsigned Op = getRegForValue(V);
1533 if (Op == 0) return false;
1534
1535 unsigned Result = createResultReg(&ARM::SPRRegClass);
1536 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1537 TII.get(ARM::VCVTSD), Result)
1538 .addReg(Op));
1539 updateValueMap(I, Result);
1540 return true;
1541 }
1542
SelectIToFP(const Instruction * I,bool isSigned)1543 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1544 // Make sure we have VFP.
1545 if (!Subtarget->hasVFP2()) return false;
1546
1547 MVT DstVT;
1548 Type *Ty = I->getType();
1549 if (!isTypeLegal(Ty, DstVT))
1550 return false;
1551
1552 Value *Src = I->getOperand(0);
1553 EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
1554 if (!SrcEVT.isSimple())
1555 return false;
1556 MVT SrcVT = SrcEVT.getSimpleVT();
1557 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1558 return false;
1559
1560 unsigned SrcReg = getRegForValue(Src);
1561 if (SrcReg == 0) return false;
1562
1563 // Handle sign-extension.
1564 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1565 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1566 /*isZExt*/!isSigned);
1567 if (SrcReg == 0) return false;
1568 }
1569
1570 // The conversion routine works on fp-reg to fp-reg and the operand above
1571 // was an integer, move it to the fp registers if possible.
1572 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1573 if (FP == 0) return false;
1574
1575 unsigned Opc;
1576 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1577 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1578 else return false;
1579
1580 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1581 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1582 TII.get(Opc), ResultReg).addReg(FP));
1583 updateValueMap(I, ResultReg);
1584 return true;
1585 }
1586
SelectFPToI(const Instruction * I,bool isSigned)1587 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1588 // Make sure we have VFP.
1589 if (!Subtarget->hasVFP2()) return false;
1590
1591 MVT DstVT;
1592 Type *RetTy = I->getType();
1593 if (!isTypeLegal(RetTy, DstVT))
1594 return false;
1595
1596 unsigned Op = getRegForValue(I->getOperand(0));
1597 if (Op == 0) return false;
1598
1599 unsigned Opc;
1600 Type *OpTy = I->getOperand(0)->getType();
1601 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1602 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1603 else return false;
1604
1605 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1606 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1607 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1608 TII.get(Opc), ResultReg).addReg(Op));
1609
1610 // This result needs to be in an integer register, but the conversion only
1611 // takes place in fp-regs.
1612 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1613 if (IntReg == 0) return false;
1614
1615 updateValueMap(I, IntReg);
1616 return true;
1617 }
1618
SelectSelect(const Instruction * I)1619 bool ARMFastISel::SelectSelect(const Instruction *I) {
1620 MVT VT;
1621 if (!isTypeLegal(I->getType(), VT))
1622 return false;
1623
1624 // Things need to be register sized for register moves.
1625 if (VT != MVT::i32) return false;
1626
1627 unsigned CondReg = getRegForValue(I->getOperand(0));
1628 if (CondReg == 0) return false;
1629 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1630 if (Op1Reg == 0) return false;
1631
1632 // Check to see if we can use an immediate in the conditional move.
1633 int Imm = 0;
1634 bool UseImm = false;
1635 bool isNegativeImm = false;
1636 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1637 assert (VT == MVT::i32 && "Expecting an i32.");
1638 Imm = (int)ConstInt->getValue().getZExtValue();
1639 if (Imm < 0) {
1640 isNegativeImm = true;
1641 Imm = ~Imm;
1642 }
1643 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1644 (ARM_AM::getSOImmVal(Imm) != -1);
1645 }
1646
1647 unsigned Op2Reg = 0;
1648 if (!UseImm) {
1649 Op2Reg = getRegForValue(I->getOperand(2));
1650 if (Op2Reg == 0) return false;
1651 }
1652
1653 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1654 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
1655 AddOptionalDefs(
1656 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1657 .addReg(CondReg)
1658 .addImm(1));
1659
1660 unsigned MovCCOpc;
1661 const TargetRegisterClass *RC;
1662 if (!UseImm) {
1663 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1664 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1665 } else {
1666 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1667 if (!isNegativeImm)
1668 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1669 else
1670 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1671 }
1672 unsigned ResultReg = createResultReg(RC);
1673 if (!UseImm) {
1674 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1675 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1676 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1677 ResultReg)
1678 .addReg(Op2Reg)
1679 .addReg(Op1Reg)
1680 .addImm(ARMCC::NE)
1681 .addReg(ARM::CPSR);
1682 } else {
1683 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1684 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1685 ResultReg)
1686 .addReg(Op1Reg)
1687 .addImm(Imm)
1688 .addImm(ARMCC::EQ)
1689 .addReg(ARM::CPSR);
1690 }
1691 updateValueMap(I, ResultReg);
1692 return true;
1693 }
1694
SelectDiv(const Instruction * I,bool isSigned)1695 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1696 MVT VT;
1697 Type *Ty = I->getType();
1698 if (!isTypeLegal(Ty, VT))
1699 return false;
1700
1701 // If we have integer div support we should have selected this automagically.
1702 // In case we have a real miss go ahead and return false and we'll pick
1703 // it up later.
1704 if (Subtarget->hasDivide()) return false;
1705
1706 // Otherwise emit a libcall.
1707 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1708 if (VT == MVT::i8)
1709 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1710 else if (VT == MVT::i16)
1711 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1712 else if (VT == MVT::i32)
1713 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1714 else if (VT == MVT::i64)
1715 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1716 else if (VT == MVT::i128)
1717 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1718 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1719
1720 return ARMEmitLibcall(I, LC);
1721 }
1722
SelectRem(const Instruction * I,bool isSigned)1723 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1724 MVT VT;
1725 Type *Ty = I->getType();
1726 if (!isTypeLegal(Ty, VT))
1727 return false;
1728
1729 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1730 if (VT == MVT::i8)
1731 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1732 else if (VT == MVT::i16)
1733 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1734 else if (VT == MVT::i32)
1735 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1736 else if (VT == MVT::i64)
1737 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1738 else if (VT == MVT::i128)
1739 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1740 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1741
1742 return ARMEmitLibcall(I, LC);
1743 }
1744
SelectBinaryIntOp(const Instruction * I,unsigned ISDOpcode)1745 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1746 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1747
1748 // We can get here in the case when we have a binary operation on a non-legal
1749 // type and the target independent selector doesn't know how to handle it.
1750 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1751 return false;
1752
1753 unsigned Opc;
1754 switch (ISDOpcode) {
1755 default: return false;
1756 case ISD::ADD:
1757 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1758 break;
1759 case ISD::OR:
1760 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1761 break;
1762 case ISD::SUB:
1763 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1764 break;
1765 }
1766
1767 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1768 if (SrcReg1 == 0) return false;
1769
1770 // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1771 // in the instruction, rather then materializing the value in a register.
1772 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1773 if (SrcReg2 == 0) return false;
1774
1775 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1776 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1777 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1778 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1779 TII.get(Opc), ResultReg)
1780 .addReg(SrcReg1).addReg(SrcReg2));
1781 updateValueMap(I, ResultReg);
1782 return true;
1783 }
1784
SelectBinaryFPOp(const Instruction * I,unsigned ISDOpcode)1785 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1786 EVT FPVT = TLI.getValueType(DL, I->getType(), true);
1787 if (!FPVT.isSimple()) return false;
1788 MVT VT = FPVT.getSimpleVT();
1789
1790 // FIXME: Support vector types where possible.
1791 if (VT.isVector())
1792 return false;
1793
1794 // We can get here in the case when we want to use NEON for our fp
1795 // operations, but can't figure out how to. Just use the vfp instructions
1796 // if we have them.
1797 // FIXME: It'd be nice to use NEON instructions.
1798 Type *Ty = I->getType();
1799 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1800 if (isFloat && !Subtarget->hasVFP2())
1801 return false;
1802
1803 unsigned Opc;
1804 bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1805 switch (ISDOpcode) {
1806 default: return false;
1807 case ISD::FADD:
1808 Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1809 break;
1810 case ISD::FSUB:
1811 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1812 break;
1813 case ISD::FMUL:
1814 Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1815 break;
1816 }
1817 unsigned Op1 = getRegForValue(I->getOperand(0));
1818 if (Op1 == 0) return false;
1819
1820 unsigned Op2 = getRegForValue(I->getOperand(1));
1821 if (Op2 == 0) return false;
1822
1823 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1824 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1825 TII.get(Opc), ResultReg)
1826 .addReg(Op1).addReg(Op2));
1827 updateValueMap(I, ResultReg);
1828 return true;
1829 }
1830
1831 // Call Handling Code
1832
1833 // This is largely taken directly from CCAssignFnForNode
1834 // TODO: We may not support all of this.
CCAssignFnForCall(CallingConv::ID CC,bool Return,bool isVarArg)1835 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1836 bool Return,
1837 bool isVarArg) {
1838 switch (CC) {
1839 default:
1840 llvm_unreachable("Unsupported calling convention");
1841 case CallingConv::Fast:
1842 if (Subtarget->hasVFP2() && !isVarArg) {
1843 if (!Subtarget->isAAPCS_ABI())
1844 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1845 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1846 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1847 }
1848 // Fallthrough
1849 case CallingConv::C:
1850 // Use target triple & subtarget features to do actual dispatch.
1851 if (Subtarget->isAAPCS_ABI()) {
1852 if (Subtarget->hasVFP2() &&
1853 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1854 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1855 else
1856 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1857 } else {
1858 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1859 }
1860 case CallingConv::ARM_AAPCS_VFP:
1861 if (!isVarArg)
1862 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1863 // Fall through to soft float variant, variadic functions don't
1864 // use hard floating point ABI.
1865 case CallingConv::ARM_AAPCS:
1866 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1867 case CallingConv::ARM_APCS:
1868 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1869 case CallingConv::GHC:
1870 if (Return)
1871 llvm_unreachable("Can't return in GHC call convention");
1872 else
1873 return CC_ARM_APCS_GHC;
1874 }
1875 }
1876
ProcessCallArgs(SmallVectorImpl<Value * > & Args,SmallVectorImpl<unsigned> & ArgRegs,SmallVectorImpl<MVT> & ArgVTs,SmallVectorImpl<ISD::ArgFlagsTy> & ArgFlags,SmallVectorImpl<unsigned> & RegArgs,CallingConv::ID CC,unsigned & NumBytes,bool isVarArg)1877 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1878 SmallVectorImpl<unsigned> &ArgRegs,
1879 SmallVectorImpl<MVT> &ArgVTs,
1880 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1881 SmallVectorImpl<unsigned> &RegArgs,
1882 CallingConv::ID CC,
1883 unsigned &NumBytes,
1884 bool isVarArg) {
1885 SmallVector<CCValAssign, 16> ArgLocs;
1886 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, ArgLocs, *Context);
1887 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1888 CCAssignFnForCall(CC, false, isVarArg));
1889
1890 // Check that we can handle all of the arguments. If we can't, then bail out
1891 // now before we add code to the MBB.
1892 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1893 CCValAssign &VA = ArgLocs[i];
1894 MVT ArgVT = ArgVTs[VA.getValNo()];
1895
1896 // We don't handle NEON/vector parameters yet.
1897 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1898 return false;
1899
1900 // Now copy/store arg to correct locations.
1901 if (VA.isRegLoc() && !VA.needsCustom()) {
1902 continue;
1903 } else if (VA.needsCustom()) {
1904 // TODO: We need custom lowering for vector (v2f64) args.
1905 if (VA.getLocVT() != MVT::f64 ||
1906 // TODO: Only handle register args for now.
1907 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1908 return false;
1909 } else {
1910 switch (ArgVT.SimpleTy) {
1911 default:
1912 return false;
1913 case MVT::i1:
1914 case MVT::i8:
1915 case MVT::i16:
1916 case MVT::i32:
1917 break;
1918 case MVT::f32:
1919 if (!Subtarget->hasVFP2())
1920 return false;
1921 break;
1922 case MVT::f64:
1923 if (!Subtarget->hasVFP2())
1924 return false;
1925 break;
1926 }
1927 }
1928 }
1929
1930 // At the point, we are able to handle the call's arguments in fast isel.
1931
1932 // Get a count of how many bytes are to be pushed on the stack.
1933 NumBytes = CCInfo.getNextStackOffset();
1934
1935 // Issue CALLSEQ_START
1936 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1937 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1938 TII.get(AdjStackDown))
1939 .addImm(NumBytes));
1940
1941 // Process the args.
1942 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1943 CCValAssign &VA = ArgLocs[i];
1944 const Value *ArgVal = Args[VA.getValNo()];
1945 unsigned Arg = ArgRegs[VA.getValNo()];
1946 MVT ArgVT = ArgVTs[VA.getValNo()];
1947
1948 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
1949 "We don't handle NEON/vector parameters yet.");
1950
1951 // Handle arg promotion, etc.
1952 switch (VA.getLocInfo()) {
1953 case CCValAssign::Full: break;
1954 case CCValAssign::SExt: {
1955 MVT DestVT = VA.getLocVT();
1956 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1957 assert (Arg != 0 && "Failed to emit a sext");
1958 ArgVT = DestVT;
1959 break;
1960 }
1961 case CCValAssign::AExt:
1962 // Intentional fall-through. Handle AExt and ZExt.
1963 case CCValAssign::ZExt: {
1964 MVT DestVT = VA.getLocVT();
1965 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
1966 assert (Arg != 0 && "Failed to emit a zext");
1967 ArgVT = DestVT;
1968 break;
1969 }
1970 case CCValAssign::BCvt: {
1971 unsigned BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1972 /*TODO: Kill=*/false);
1973 assert(BC != 0 && "Failed to emit a bitcast!");
1974 Arg = BC;
1975 ArgVT = VA.getLocVT();
1976 break;
1977 }
1978 default: llvm_unreachable("Unknown arg promotion!");
1979 }
1980
1981 // Now copy/store arg to correct locations.
1982 if (VA.isRegLoc() && !VA.needsCustom()) {
1983 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1984 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
1985 RegArgs.push_back(VA.getLocReg());
1986 } else if (VA.needsCustom()) {
1987 // TODO: We need custom lowering for vector (v2f64) args.
1988 assert(VA.getLocVT() == MVT::f64 &&
1989 "Custom lowering for v2f64 args not available");
1990
1991 CCValAssign &NextVA = ArgLocs[++i];
1992
1993 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
1994 "We only handle register args!");
1995
1996 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1997 TII.get(ARM::VMOVRRD), VA.getLocReg())
1998 .addReg(NextVA.getLocReg(), RegState::Define)
1999 .addReg(Arg));
2000 RegArgs.push_back(VA.getLocReg());
2001 RegArgs.push_back(NextVA.getLocReg());
2002 } else {
2003 assert(VA.isMemLoc());
2004 // Need to store on the stack.
2005
2006 // Don't emit stores for undef values.
2007 if (isa<UndefValue>(ArgVal))
2008 continue;
2009
2010 Address Addr;
2011 Addr.BaseType = Address::RegBase;
2012 Addr.Base.Reg = ARM::SP;
2013 Addr.Offset = VA.getLocMemOffset();
2014
2015 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2016 assert(EmitRet && "Could not emit a store for argument!");
2017 }
2018 }
2019
2020 return true;
2021 }
2022
FinishCall(MVT RetVT,SmallVectorImpl<unsigned> & UsedRegs,const Instruction * I,CallingConv::ID CC,unsigned & NumBytes,bool isVarArg)2023 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2024 const Instruction *I, CallingConv::ID CC,
2025 unsigned &NumBytes, bool isVarArg) {
2026 // Issue CALLSEQ_END
2027 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2028 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2029 TII.get(AdjStackUp))
2030 .addImm(NumBytes).addImm(0));
2031
2032 // Now the return value.
2033 if (RetVT != MVT::isVoid) {
2034 SmallVector<CCValAssign, 16> RVLocs;
2035 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2036 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2037
2038 // Copy all of the result registers out of their specified physreg.
2039 if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2040 // For this move we copy into two registers and then move into the
2041 // double fp reg we want.
2042 MVT DestVT = RVLocs[0].getValVT();
2043 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2044 unsigned ResultReg = createResultReg(DstRC);
2045 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2046 TII.get(ARM::VMOVDRR), ResultReg)
2047 .addReg(RVLocs[0].getLocReg())
2048 .addReg(RVLocs[1].getLocReg()));
2049
2050 UsedRegs.push_back(RVLocs[0].getLocReg());
2051 UsedRegs.push_back(RVLocs[1].getLocReg());
2052
2053 // Finally update the result.
2054 updateValueMap(I, ResultReg);
2055 } else {
2056 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2057 MVT CopyVT = RVLocs[0].getValVT();
2058
2059 // Special handling for extended integers.
2060 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2061 CopyVT = MVT::i32;
2062
2063 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2064
2065 unsigned ResultReg = createResultReg(DstRC);
2066 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2067 TII.get(TargetOpcode::COPY),
2068 ResultReg).addReg(RVLocs[0].getLocReg());
2069 UsedRegs.push_back(RVLocs[0].getLocReg());
2070
2071 // Finally update the result.
2072 updateValueMap(I, ResultReg);
2073 }
2074 }
2075
2076 return true;
2077 }
2078
SelectRet(const Instruction * I)2079 bool ARMFastISel::SelectRet(const Instruction *I) {
2080 const ReturnInst *Ret = cast<ReturnInst>(I);
2081 const Function &F = *I->getParent()->getParent();
2082
2083 if (!FuncInfo.CanLowerReturn)
2084 return false;
2085
2086 // Build a list of return value registers.
2087 SmallVector<unsigned, 4> RetRegs;
2088
2089 CallingConv::ID CC = F.getCallingConv();
2090 if (Ret->getNumOperands() > 0) {
2091 SmallVector<ISD::OutputArg, 4> Outs;
2092 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
2093
2094 // Analyze operands of the call, assigning locations to each operand.
2095 SmallVector<CCValAssign, 16> ValLocs;
2096 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2097 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2098 F.isVarArg()));
2099
2100 const Value *RV = Ret->getOperand(0);
2101 unsigned Reg = getRegForValue(RV);
2102 if (Reg == 0)
2103 return false;
2104
2105 // Only handle a single return value for now.
2106 if (ValLocs.size() != 1)
2107 return false;
2108
2109 CCValAssign &VA = ValLocs[0];
2110
2111 // Don't bother handling odd stuff for now.
2112 if (VA.getLocInfo() != CCValAssign::Full)
2113 return false;
2114 // Only handle register returns for now.
2115 if (!VA.isRegLoc())
2116 return false;
2117
2118 unsigned SrcReg = Reg + VA.getValNo();
2119 EVT RVEVT = TLI.getValueType(DL, RV->getType());
2120 if (!RVEVT.isSimple()) return false;
2121 MVT RVVT = RVEVT.getSimpleVT();
2122 MVT DestVT = VA.getValVT();
2123 // Special handling for extended integers.
2124 if (RVVT != DestVT) {
2125 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2126 return false;
2127
2128 assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2129
2130 // Perform extension if flagged as either zext or sext. Otherwise, do
2131 // nothing.
2132 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2133 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2134 if (SrcReg == 0) return false;
2135 }
2136 }
2137
2138 // Make the copy.
2139 unsigned DstReg = VA.getLocReg();
2140 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2141 // Avoid a cross-class copy. This is very unlikely.
2142 if (!SrcRC->contains(DstReg))
2143 return false;
2144 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2145 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2146
2147 // Add register to return instruction.
2148 RetRegs.push_back(VA.getLocReg());
2149 }
2150
2151 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2152 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2153 TII.get(RetOpc));
2154 AddOptionalDefs(MIB);
2155 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2156 MIB.addReg(RetRegs[i], RegState::Implicit);
2157 return true;
2158 }
2159
ARMSelectCallOp(bool UseReg)2160 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2161 if (UseReg)
2162 return isThumb2 ? ARM::tBLXr : ARM::BLX;
2163 else
2164 return isThumb2 ? ARM::tBL : ARM::BL;
2165 }
2166
getLibcallReg(const Twine & Name)2167 unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2168 // Manually compute the global's type to avoid building it when unnecessary.
2169 Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2170 EVT LCREVT = TLI.getValueType(DL, GVTy);
2171 if (!LCREVT.isSimple()) return 0;
2172
2173 GlobalValue *GV = new GlobalVariable(M, Type::getInt32Ty(*Context), false,
2174 GlobalValue::ExternalLinkage, nullptr,
2175 Name);
2176 assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2177 return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2178 }
2179
2180 // A quick function that will emit a call for a named libcall in F with the
2181 // vector of passed arguments for the Instruction in I. We can assume that we
2182 // can emit a call for any libcall we can produce. This is an abridged version
2183 // of the full call infrastructure since we won't need to worry about things
2184 // like computed function pointers or strange arguments at call sites.
2185 // TODO: Try to unify this and the normal call bits for ARM, then try to unify
2186 // with X86.
ARMEmitLibcall(const Instruction * I,RTLIB::Libcall Call)2187 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2188 CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2189
2190 // Handle *simple* calls for now.
2191 Type *RetTy = I->getType();
2192 MVT RetVT;
2193 if (RetTy->isVoidTy())
2194 RetVT = MVT::isVoid;
2195 else if (!isTypeLegal(RetTy, RetVT))
2196 return false;
2197
2198 // Can't handle non-double multi-reg retvals.
2199 if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2200 SmallVector<CCValAssign, 16> RVLocs;
2201 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2202 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2203 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2204 return false;
2205 }
2206
2207 // Set up the argument vectors.
2208 SmallVector<Value*, 8> Args;
2209 SmallVector<unsigned, 8> ArgRegs;
2210 SmallVector<MVT, 8> ArgVTs;
2211 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2212 Args.reserve(I->getNumOperands());
2213 ArgRegs.reserve(I->getNumOperands());
2214 ArgVTs.reserve(I->getNumOperands());
2215 ArgFlags.reserve(I->getNumOperands());
2216 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2217 Value *Op = I->getOperand(i);
2218 unsigned Arg = getRegForValue(Op);
2219 if (Arg == 0) return false;
2220
2221 Type *ArgTy = Op->getType();
2222 MVT ArgVT;
2223 if (!isTypeLegal(ArgTy, ArgVT)) return false;
2224
2225 ISD::ArgFlagsTy Flags;
2226 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2227 Flags.setOrigAlign(OriginalAlignment);
2228
2229 Args.push_back(Op);
2230 ArgRegs.push_back(Arg);
2231 ArgVTs.push_back(ArgVT);
2232 ArgFlags.push_back(Flags);
2233 }
2234
2235 // Handle the arguments now that we've gotten them.
2236 SmallVector<unsigned, 4> RegArgs;
2237 unsigned NumBytes;
2238 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2239 RegArgs, CC, NumBytes, false))
2240 return false;
2241
2242 unsigned CalleeReg = 0;
2243 if (Subtarget->genLongCalls()) {
2244 CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2245 if (CalleeReg == 0) return false;
2246 }
2247
2248 // Issue the call.
2249 unsigned CallOpc = ARMSelectCallOp(Subtarget->genLongCalls());
2250 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2251 DbgLoc, TII.get(CallOpc));
2252 // BL / BLX don't take a predicate, but tBL / tBLX do.
2253 if (isThumb2)
2254 AddDefaultPred(MIB);
2255 if (Subtarget->genLongCalls())
2256 MIB.addReg(CalleeReg);
2257 else
2258 MIB.addExternalSymbol(TLI.getLibcallName(Call));
2259
2260 // Add implicit physical register uses to the call.
2261 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2262 MIB.addReg(RegArgs[i], RegState::Implicit);
2263
2264 // Add a register mask with the call-preserved registers.
2265 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2266 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2267
2268 // Finish off the call including any return values.
2269 SmallVector<unsigned, 4> UsedRegs;
2270 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2271
2272 // Set all unused physreg defs as dead.
2273 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2274
2275 return true;
2276 }
2277
SelectCall(const Instruction * I,const char * IntrMemName=nullptr)2278 bool ARMFastISel::SelectCall(const Instruction *I,
2279 const char *IntrMemName = nullptr) {
2280 const CallInst *CI = cast<CallInst>(I);
2281 const Value *Callee = CI->getCalledValue();
2282
2283 // Can't handle inline asm.
2284 if (isa<InlineAsm>(Callee)) return false;
2285
2286 // Allow SelectionDAG isel to handle tail calls.
2287 if (CI->isTailCall()) return false;
2288
2289 // Check the calling convention.
2290 ImmutableCallSite CS(CI);
2291 CallingConv::ID CC = CS.getCallingConv();
2292
2293 // TODO: Avoid some calling conventions?
2294
2295 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2296 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2297 bool isVarArg = FTy->isVarArg();
2298
2299 // Handle *simple* calls for now.
2300 Type *RetTy = I->getType();
2301 MVT RetVT;
2302 if (RetTy->isVoidTy())
2303 RetVT = MVT::isVoid;
2304 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2305 RetVT != MVT::i8 && RetVT != MVT::i1)
2306 return false;
2307
2308 // Can't handle non-double multi-reg retvals.
2309 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2310 RetVT != MVT::i16 && RetVT != MVT::i32) {
2311 SmallVector<CCValAssign, 16> RVLocs;
2312 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context);
2313 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2314 if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2315 return false;
2316 }
2317
2318 // Set up the argument vectors.
2319 SmallVector<Value*, 8> Args;
2320 SmallVector<unsigned, 8> ArgRegs;
2321 SmallVector<MVT, 8> ArgVTs;
2322 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2323 unsigned arg_size = CS.arg_size();
2324 Args.reserve(arg_size);
2325 ArgRegs.reserve(arg_size);
2326 ArgVTs.reserve(arg_size);
2327 ArgFlags.reserve(arg_size);
2328 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2329 i != e; ++i) {
2330 // If we're lowering a memory intrinsic instead of a regular call, skip the
2331 // last two arguments, which shouldn't be passed to the underlying function.
2332 if (IntrMemName && e-i <= 2)
2333 break;
2334
2335 ISD::ArgFlagsTy Flags;
2336 unsigned AttrInd = i - CS.arg_begin() + 1;
2337 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2338 Flags.setSExt();
2339 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2340 Flags.setZExt();
2341
2342 // FIXME: Only handle *easy* calls for now.
2343 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2344 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2345 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2346 CS.paramHasAttr(AttrInd, Attribute::ByVal))
2347 return false;
2348
2349 Type *ArgTy = (*i)->getType();
2350 MVT ArgVT;
2351 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2352 ArgVT != MVT::i1)
2353 return false;
2354
2355 unsigned Arg = getRegForValue(*i);
2356 if (Arg == 0)
2357 return false;
2358
2359 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
2360 Flags.setOrigAlign(OriginalAlignment);
2361
2362 Args.push_back(*i);
2363 ArgRegs.push_back(Arg);
2364 ArgVTs.push_back(ArgVT);
2365 ArgFlags.push_back(Flags);
2366 }
2367
2368 // Handle the arguments now that we've gotten them.
2369 SmallVector<unsigned, 4> RegArgs;
2370 unsigned NumBytes;
2371 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2372 RegArgs, CC, NumBytes, isVarArg))
2373 return false;
2374
2375 bool UseReg = false;
2376 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2377 if (!GV || Subtarget->genLongCalls()) UseReg = true;
2378
2379 unsigned CalleeReg = 0;
2380 if (UseReg) {
2381 if (IntrMemName)
2382 CalleeReg = getLibcallReg(IntrMemName);
2383 else
2384 CalleeReg = getRegForValue(Callee);
2385
2386 if (CalleeReg == 0) return false;
2387 }
2388
2389 // Issue the call.
2390 unsigned CallOpc = ARMSelectCallOp(UseReg);
2391 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2392 DbgLoc, TII.get(CallOpc));
2393
2394 unsigned char OpFlags = 0;
2395
2396 // Add MO_PLT for global address or external symbol in the PIC relocation
2397 // model.
2398 if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2399 OpFlags = ARMII::MO_PLT;
2400
2401 // ARM calls don't take a predicate, but tBL / tBLX do.
2402 if(isThumb2)
2403 AddDefaultPred(MIB);
2404 if (UseReg)
2405 MIB.addReg(CalleeReg);
2406 else if (!IntrMemName)
2407 MIB.addGlobalAddress(GV, 0, OpFlags);
2408 else
2409 MIB.addExternalSymbol(IntrMemName, OpFlags);
2410
2411 // Add implicit physical register uses to the call.
2412 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2413 MIB.addReg(RegArgs[i], RegState::Implicit);
2414
2415 // Add a register mask with the call-preserved registers.
2416 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2417 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
2418
2419 // Finish off the call including any return values.
2420 SmallVector<unsigned, 4> UsedRegs;
2421 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2422 return false;
2423
2424 // Set all unused physreg defs as dead.
2425 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2426
2427 return true;
2428 }
2429
ARMIsMemCpySmall(uint64_t Len)2430 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2431 return Len <= 16;
2432 }
2433
ARMTryEmitSmallMemCpy(Address Dest,Address Src,uint64_t Len,unsigned Alignment)2434 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2435 uint64_t Len, unsigned Alignment) {
2436 // Make sure we don't bloat code by inlining very large memcpy's.
2437 if (!ARMIsMemCpySmall(Len))
2438 return false;
2439
2440 while (Len) {
2441 MVT VT;
2442 if (!Alignment || Alignment >= 4) {
2443 if (Len >= 4)
2444 VT = MVT::i32;
2445 else if (Len >= 2)
2446 VT = MVT::i16;
2447 else {
2448 assert (Len == 1 && "Expected a length of 1!");
2449 VT = MVT::i8;
2450 }
2451 } else {
2452 // Bound based on alignment.
2453 if (Len >= 2 && Alignment == 2)
2454 VT = MVT::i16;
2455 else {
2456 VT = MVT::i8;
2457 }
2458 }
2459
2460 bool RV;
2461 unsigned ResultReg;
2462 RV = ARMEmitLoad(VT, ResultReg, Src);
2463 assert (RV == true && "Should be able to handle this load.");
2464 RV = ARMEmitStore(VT, ResultReg, Dest);
2465 assert (RV == true && "Should be able to handle this store.");
2466 (void)RV;
2467
2468 unsigned Size = VT.getSizeInBits()/8;
2469 Len -= Size;
2470 Dest.Offset += Size;
2471 Src.Offset += Size;
2472 }
2473
2474 return true;
2475 }
2476
SelectIntrinsicCall(const IntrinsicInst & I)2477 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2478 // FIXME: Handle more intrinsics.
2479 switch (I.getIntrinsicID()) {
2480 default: return false;
2481 case Intrinsic::frameaddress: {
2482 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2483 MFI->setFrameAddressIsTaken(true);
2484
2485 unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
2486 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2487 : &ARM::GPRRegClass;
2488
2489 const ARMBaseRegisterInfo *RegInfo =
2490 static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
2491 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2492 unsigned SrcReg = FramePtr;
2493
2494 // Recursively load frame address
2495 // ldr r0 [fp]
2496 // ldr r0 [r0]
2497 // ldr r0 [r0]
2498 // ...
2499 unsigned DestReg;
2500 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2501 while (Depth--) {
2502 DestReg = createResultReg(RC);
2503 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2504 TII.get(LdrOpc), DestReg)
2505 .addReg(SrcReg).addImm(0));
2506 SrcReg = DestReg;
2507 }
2508 updateValueMap(&I, SrcReg);
2509 return true;
2510 }
2511 case Intrinsic::memcpy:
2512 case Intrinsic::memmove: {
2513 const MemTransferInst &MTI = cast<MemTransferInst>(I);
2514 // Don't handle volatile.
2515 if (MTI.isVolatile())
2516 return false;
2517
2518 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2519 // we would emit dead code because we don't currently handle memmoves.
2520 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2521 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2522 // Small memcpy's are common enough that we want to do them without a call
2523 // if possible.
2524 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2525 if (ARMIsMemCpySmall(Len)) {
2526 Address Dest, Src;
2527 if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2528 !ARMComputeAddress(MTI.getRawSource(), Src))
2529 return false;
2530 unsigned Alignment = MTI.getAlignment();
2531 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2532 return true;
2533 }
2534 }
2535
2536 if (!MTI.getLength()->getType()->isIntegerTy(32))
2537 return false;
2538
2539 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2540 return false;
2541
2542 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2543 return SelectCall(&I, IntrMemName);
2544 }
2545 case Intrinsic::memset: {
2546 const MemSetInst &MSI = cast<MemSetInst>(I);
2547 // Don't handle volatile.
2548 if (MSI.isVolatile())
2549 return false;
2550
2551 if (!MSI.getLength()->getType()->isIntegerTy(32))
2552 return false;
2553
2554 if (MSI.getDestAddressSpace() > 255)
2555 return false;
2556
2557 return SelectCall(&I, "memset");
2558 }
2559 case Intrinsic::trap: {
2560 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
2561 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2562 return true;
2563 }
2564 }
2565 }
2566
SelectTrunc(const Instruction * I)2567 bool ARMFastISel::SelectTrunc(const Instruction *I) {
2568 // The high bits for a type smaller than the register size are assumed to be
2569 // undefined.
2570 Value *Op = I->getOperand(0);
2571
2572 EVT SrcVT, DestVT;
2573 SrcVT = TLI.getValueType(DL, Op->getType(), true);
2574 DestVT = TLI.getValueType(DL, I->getType(), true);
2575
2576 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2577 return false;
2578 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2579 return false;
2580
2581 unsigned SrcReg = getRegForValue(Op);
2582 if (!SrcReg) return false;
2583
2584 // Because the high bits are undefined, a truncate doesn't generate
2585 // any code.
2586 updateValueMap(I, SrcReg);
2587 return true;
2588 }
2589
ARMEmitIntExt(MVT SrcVT,unsigned SrcReg,MVT DestVT,bool isZExt)2590 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2591 bool isZExt) {
2592 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2593 return 0;
2594 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2595 return 0;
2596
2597 // Table of which combinations can be emitted as a single instruction,
2598 // and which will require two.
2599 static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2600 // ARM Thumb
2601 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2602 // ext: s z s z s z s z
2603 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2604 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2605 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2606 };
2607
2608 // Target registers for:
2609 // - For ARM can never be PC.
2610 // - For 16-bit Thumb are restricted to lower 8 registers.
2611 // - For 32-bit Thumb are restricted to non-SP and non-PC.
2612 static const TargetRegisterClass *RCTbl[2][2] = {
2613 // Instructions: Two Single
2614 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2615 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass }
2616 };
2617
2618 // Table governing the instruction(s) to be emitted.
2619 static const struct InstructionTable {
2620 uint32_t Opc : 16;
2621 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0.
2622 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi.
2623 uint32_t Imm : 8; // All instructions have either a shift or a mask.
2624 } IT[2][2][3][2] = {
2625 { // Two instructions (first is left shift, second is in this table).
2626 { // ARM Opc S Shift Imm
2627 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 },
2628 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } },
2629 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 },
2630 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } },
2631 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 },
2632 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } }
2633 },
2634 { // Thumb Opc S Shift Imm
2635 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 },
2636 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } },
2637 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 },
2638 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } },
2639 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 },
2640 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } }
2641 }
2642 },
2643 { // Single instruction.
2644 { // ARM Opc S Shift Imm
2645 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2646 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2647 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2648 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2649 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 },
2650 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2651 },
2652 { // Thumb Opc S Shift Imm
2653 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 },
2654 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } },
2655 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 },
2656 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2657 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 },
2658 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } }
2659 }
2660 }
2661 };
2662
2663 unsigned SrcBits = SrcVT.getSizeInBits();
2664 unsigned DestBits = DestVT.getSizeInBits();
2665 (void) DestBits;
2666 assert((SrcBits < DestBits) && "can only extend to larger types");
2667 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2668 "other sizes unimplemented");
2669 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2670 "other sizes unimplemented");
2671
2672 bool hasV6Ops = Subtarget->hasV6Ops();
2673 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2}
2674 assert((Bitness < 3) && "sanity-check table bounds");
2675
2676 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2677 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2678 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2679 unsigned Opc = ITP->Opc;
2680 assert(ARM::KILL != Opc && "Invalid table entry");
2681 unsigned hasS = ITP->hasS;
2682 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2683 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2684 "only MOVsi has shift operand addressing mode");
2685 unsigned Imm = ITP->Imm;
2686
2687 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2688 bool setsCPSR = &ARM::tGPRRegClass == RC;
2689 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2690 unsigned ResultReg;
2691 // MOVsi encodes shift and immediate in shift operand addressing mode.
2692 // The following condition has the same value when emitting two
2693 // instruction sequences: both are shifts.
2694 bool ImmIsSO = (Shift != ARM_AM::no_shift);
2695
2696 // Either one or two instructions are emitted.
2697 // They're always of the form:
2698 // dst = in OP imm
2699 // CPSR is set only by 16-bit Thumb instructions.
2700 // Predicate, if any, is AL.
2701 // S bit, if available, is always 0.
2702 // When two are emitted the first's result will feed as the second's input,
2703 // that value is then dead.
2704 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2705 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2706 ResultReg = createResultReg(RC);
2707 bool isLsl = (0 == Instr) && !isSingleInstr;
2708 unsigned Opcode = isLsl ? LSLOpc : Opc;
2709 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2710 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2711 bool isKill = 1 == Instr;
2712 MachineInstrBuilder MIB = BuildMI(
2713 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2714 if (setsCPSR)
2715 MIB.addReg(ARM::CPSR, RegState::Define);
2716 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2717 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2718 if (hasS)
2719 AddDefaultCC(MIB);
2720 // Second instruction consumes the first's result.
2721 SrcReg = ResultReg;
2722 }
2723
2724 return ResultReg;
2725 }
2726
SelectIntExt(const Instruction * I)2727 bool ARMFastISel::SelectIntExt(const Instruction *I) {
2728 // On ARM, in general, integer casts don't involve legal types; this code
2729 // handles promotable integers.
2730 Type *DestTy = I->getType();
2731 Value *Src = I->getOperand(0);
2732 Type *SrcTy = Src->getType();
2733
2734 bool isZExt = isa<ZExtInst>(I);
2735 unsigned SrcReg = getRegForValue(Src);
2736 if (!SrcReg) return false;
2737
2738 EVT SrcEVT, DestEVT;
2739 SrcEVT = TLI.getValueType(DL, SrcTy, true);
2740 DestEVT = TLI.getValueType(DL, DestTy, true);
2741 if (!SrcEVT.isSimple()) return false;
2742 if (!DestEVT.isSimple()) return false;
2743
2744 MVT SrcVT = SrcEVT.getSimpleVT();
2745 MVT DestVT = DestEVT.getSimpleVT();
2746 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2747 if (ResultReg == 0) return false;
2748 updateValueMap(I, ResultReg);
2749 return true;
2750 }
2751
SelectShift(const Instruction * I,ARM_AM::ShiftOpc ShiftTy)2752 bool ARMFastISel::SelectShift(const Instruction *I,
2753 ARM_AM::ShiftOpc ShiftTy) {
2754 // We handle thumb2 mode by target independent selector
2755 // or SelectionDAG ISel.
2756 if (isThumb2)
2757 return false;
2758
2759 // Only handle i32 now.
2760 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
2761 if (DestVT != MVT::i32)
2762 return false;
2763
2764 unsigned Opc = ARM::MOVsr;
2765 unsigned ShiftImm;
2766 Value *Src2Value = I->getOperand(1);
2767 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2768 ShiftImm = CI->getZExtValue();
2769
2770 // Fall back to selection DAG isel if the shift amount
2771 // is zero or greater than the width of the value type.
2772 if (ShiftImm == 0 || ShiftImm >=32)
2773 return false;
2774
2775 Opc = ARM::MOVsi;
2776 }
2777
2778 Value *Src1Value = I->getOperand(0);
2779 unsigned Reg1 = getRegForValue(Src1Value);
2780 if (Reg1 == 0) return false;
2781
2782 unsigned Reg2 = 0;
2783 if (Opc == ARM::MOVsr) {
2784 Reg2 = getRegForValue(Src2Value);
2785 if (Reg2 == 0) return false;
2786 }
2787
2788 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2789 if(ResultReg == 0) return false;
2790
2791 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2792 TII.get(Opc), ResultReg)
2793 .addReg(Reg1);
2794
2795 if (Opc == ARM::MOVsi)
2796 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2797 else if (Opc == ARM::MOVsr) {
2798 MIB.addReg(Reg2);
2799 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2800 }
2801
2802 AddOptionalDefs(MIB);
2803 updateValueMap(I, ResultReg);
2804 return true;
2805 }
2806
2807 // TODO: SoftFP support.
fastSelectInstruction(const Instruction * I)2808 bool ARMFastISel::fastSelectInstruction(const Instruction *I) {
2809
2810 switch (I->getOpcode()) {
2811 case Instruction::Load:
2812 return SelectLoad(I);
2813 case Instruction::Store:
2814 return SelectStore(I);
2815 case Instruction::Br:
2816 return SelectBranch(I);
2817 case Instruction::IndirectBr:
2818 return SelectIndirectBr(I);
2819 case Instruction::ICmp:
2820 case Instruction::FCmp:
2821 return SelectCmp(I);
2822 case Instruction::FPExt:
2823 return SelectFPExt(I);
2824 case Instruction::FPTrunc:
2825 return SelectFPTrunc(I);
2826 case Instruction::SIToFP:
2827 return SelectIToFP(I, /*isSigned*/ true);
2828 case Instruction::UIToFP:
2829 return SelectIToFP(I, /*isSigned*/ false);
2830 case Instruction::FPToSI:
2831 return SelectFPToI(I, /*isSigned*/ true);
2832 case Instruction::FPToUI:
2833 return SelectFPToI(I, /*isSigned*/ false);
2834 case Instruction::Add:
2835 return SelectBinaryIntOp(I, ISD::ADD);
2836 case Instruction::Or:
2837 return SelectBinaryIntOp(I, ISD::OR);
2838 case Instruction::Sub:
2839 return SelectBinaryIntOp(I, ISD::SUB);
2840 case Instruction::FAdd:
2841 return SelectBinaryFPOp(I, ISD::FADD);
2842 case Instruction::FSub:
2843 return SelectBinaryFPOp(I, ISD::FSUB);
2844 case Instruction::FMul:
2845 return SelectBinaryFPOp(I, ISD::FMUL);
2846 case Instruction::SDiv:
2847 return SelectDiv(I, /*isSigned*/ true);
2848 case Instruction::UDiv:
2849 return SelectDiv(I, /*isSigned*/ false);
2850 case Instruction::SRem:
2851 return SelectRem(I, /*isSigned*/ true);
2852 case Instruction::URem:
2853 return SelectRem(I, /*isSigned*/ false);
2854 case Instruction::Call:
2855 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2856 return SelectIntrinsicCall(*II);
2857 return SelectCall(I);
2858 case Instruction::Select:
2859 return SelectSelect(I);
2860 case Instruction::Ret:
2861 return SelectRet(I);
2862 case Instruction::Trunc:
2863 return SelectTrunc(I);
2864 case Instruction::ZExt:
2865 case Instruction::SExt:
2866 return SelectIntExt(I);
2867 case Instruction::Shl:
2868 return SelectShift(I, ARM_AM::lsl);
2869 case Instruction::LShr:
2870 return SelectShift(I, ARM_AM::lsr);
2871 case Instruction::AShr:
2872 return SelectShift(I, ARM_AM::asr);
2873 default: break;
2874 }
2875 return false;
2876 }
2877
2878 namespace {
2879 // This table describes sign- and zero-extend instructions which can be
2880 // folded into a preceding load. All of these extends have an immediate
2881 // (sometimes a mask and sometimes a shift) that's applied after
2882 // extension.
2883 const struct FoldableLoadExtendsStruct {
2884 uint16_t Opc[2]; // ARM, Thumb.
2885 uint8_t ExpectedImm;
2886 uint8_t isZExt : 1;
2887 uint8_t ExpectedVT : 7;
2888 } FoldableLoadExtends[] = {
2889 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
2890 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
2891 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
2892 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
2893 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
2894 };
2895 }
2896
2897 /// \brief The specified machine instr operand is a vreg, and that
2898 /// vreg is being provided by the specified load instruction. If possible,
2899 /// try to fold the load as an operand to the instruction, returning true if
2900 /// successful.
tryToFoldLoadIntoMI(MachineInstr * MI,unsigned OpNo,const LoadInst * LI)2901 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2902 const LoadInst *LI) {
2903 // Verify we have a legal type before going any further.
2904 MVT VT;
2905 if (!isLoadTypeLegal(LI->getType(), VT))
2906 return false;
2907
2908 // Combine load followed by zero- or sign-extend.
2909 // ldrb r1, [r0] ldrb r1, [r0]
2910 // uxtb r2, r1 =>
2911 // mov r3, r2 mov r3, r1
2912 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2913 return false;
2914 const uint64_t Imm = MI->getOperand(2).getImm();
2915
2916 bool Found = false;
2917 bool isZExt;
2918 for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
2919 i != e; ++i) {
2920 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
2921 (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
2922 MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
2923 Found = true;
2924 isZExt = FoldableLoadExtends[i].isZExt;
2925 }
2926 }
2927 if (!Found) return false;
2928
2929 // See if we can handle this address.
2930 Address Addr;
2931 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
2932
2933 unsigned ResultReg = MI->getOperand(0).getReg();
2934 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
2935 return false;
2936 MI->eraseFromParent();
2937 return true;
2938 }
2939
ARMLowerPICELF(const GlobalValue * GV,unsigned Align,MVT VT)2940 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
2941 unsigned Align, MVT VT) {
2942 bool UseGOT_PREL =
2943 !(GV->hasHiddenVisibility() || GV->hasLocalLinkage());
2944
2945 LLVMContext *Context = &MF->getFunction()->getContext();
2946 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2947 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2948 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
2949 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj,
2950 UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
2951 /*AddCurrentAddress=*/UseGOT_PREL);
2952
2953 unsigned ConstAlign =
2954 MF->getDataLayout().getPrefTypeAlignment(Type::getInt32PtrTy(*Context));
2955 unsigned Idx = MF->getConstantPool()->getConstantPoolIndex(CPV, ConstAlign);
2956
2957 unsigned TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
2958 unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;
2959 MachineInstrBuilder MIB =
2960 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg)
2961 .addConstantPoolIndex(Idx);
2962 if (Opc == ARM::LDRcp)
2963 MIB.addImm(0);
2964 AddDefaultPred(MIB);
2965
2966 // Fix the address by adding pc.
2967 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
2968 Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR
2969 : ARM::PICADD;
2970 DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);
2971 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2972 .addReg(TempReg)
2973 .addImm(ARMPCLabelIndex);
2974 if (!Subtarget->isThumb())
2975 AddDefaultPred(MIB);
2976
2977 if (UseGOT_PREL && Subtarget->isThumb()) {
2978 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
2979 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2980 TII.get(ARM::t2LDRi12), NewDestReg)
2981 .addReg(DestReg)
2982 .addImm(0);
2983 DestReg = NewDestReg;
2984 AddOptionalDefs(MIB);
2985 }
2986 return DestReg;
2987 }
2988
fastLowerArguments()2989 bool ARMFastISel::fastLowerArguments() {
2990 if (!FuncInfo.CanLowerReturn)
2991 return false;
2992
2993 const Function *F = FuncInfo.Fn;
2994 if (F->isVarArg())
2995 return false;
2996
2997 CallingConv::ID CC = F->getCallingConv();
2998 switch (CC) {
2999 default:
3000 return false;
3001 case CallingConv::Fast:
3002 case CallingConv::C:
3003 case CallingConv::ARM_AAPCS_VFP:
3004 case CallingConv::ARM_AAPCS:
3005 case CallingConv::ARM_APCS:
3006 break;
3007 }
3008
3009 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3010 // which are passed in r0 - r3.
3011 unsigned Idx = 1;
3012 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3013 I != E; ++I, ++Idx) {
3014 if (Idx > 4)
3015 return false;
3016
3017 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3018 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
3019 F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
3020 return false;
3021
3022 Type *ArgTy = I->getType();
3023 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3024 return false;
3025
3026 EVT ArgVT = TLI.getValueType(DL, ArgTy);
3027 if (!ArgVT.isSimple()) return false;
3028 switch (ArgVT.getSimpleVT().SimpleTy) {
3029 case MVT::i8:
3030 case MVT::i16:
3031 case MVT::i32:
3032 break;
3033 default:
3034 return false;
3035 }
3036 }
3037
3038
3039 static const MCPhysReg GPRArgRegs[] = {
3040 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3041 };
3042
3043 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3044 Idx = 0;
3045 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3046 I != E; ++I, ++Idx) {
3047 unsigned SrcReg = GPRArgRegs[Idx];
3048 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3049 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3050 // Without this, EmitLiveInCopies may eliminate the livein if its only
3051 // use is a bitcast (which isn't turned into an instruction).
3052 unsigned ResultReg = createResultReg(RC);
3053 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3054 TII.get(TargetOpcode::COPY),
3055 ResultReg).addReg(DstReg, getKillRegState(true));
3056 updateValueMap(&*I, ResultReg);
3057 }
3058
3059 return true;
3060 }
3061
3062 namespace llvm {
createFastISel(FunctionLoweringInfo & funcInfo,const TargetLibraryInfo * libInfo)3063 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3064 const TargetLibraryInfo *libInfo) {
3065 if (funcInfo.MF->getSubtarget<ARMSubtarget>().useFastISel())
3066 return new ARMFastISel(funcInfo, libInfo);
3067
3068 return nullptr;
3069 }
3070 }
3071