Searched refs:BFM (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 265 BFM, // Insert a range of bits into a 32-bit word. enumerator
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| D | AMDGPUInstrInfo.td | 192 def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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| D | SIInstructions.td | 3204 multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
3207 (BFM $a, $b)
3212 (BFM $a, (MOV 0))
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| D | AMDGPUISelLowering.cpp | 1035 return DAG.getNode(AMDGPUISD::BFM, DL, VT, in LowerINTRINSIC_WO_CHAIN()
2701 NODE_NAME_CASE(BFM) in getTargetNodeName()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | bitfield-insert.ll | 200 ; Bitfield insert where the second or operand is a better match to be folded into the BFM
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 580 BFM = BFM_w, enumerator
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| D | assembler-arm64.cc | 1288 Emit(SF(rd) | BFM | N | in bfm()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 168 // ASRV,LSLV,LSRV,RORV,BFM,SBFM,UBFM
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| D | AArch64SchedA57.td | 156 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
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| D | AArch64ISelDAGToDAG.cpp | 1676 SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64); in SelectBitfieldExtractOp() local
1680 SDValue(BFM, 0), SubReg); in SelectBitfieldExtractOp()
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| D | AArch64InstrInfo.td | 956 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 607 BFM = BFM_w, enumerator
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| D | assembler-a64.cc | 1093 Emit(SF(rd) | BFM | N | in bfm()
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| /external/vixl/doc/ |
| D | supported-instructions.md | 146 ### BFM ### subsection
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