| /external/llvm/test/Transforms/MergeFunc/ |
| D | self-referential-global.ll | 4 %LL = type { %S, %LL* }
8 …LL] [%LL { %S { void (%S*, i32)* @B }, %LL* getelementptr inbounds ([3 x %LL], [3 x %LL]* @Table, …
|
| /external/libcxx/include/ |
| D | ratio | 127 static const intmax_t min = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1)) + 1;
145 static const intmax_t min = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1)) + 1;
159 static const intmax_t min = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1)) + 1;
177 static const intmax_t min = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1)) + 1;
188 static const intmax_t nan = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1));
224 static const intmax_t nan = (1LL << (sizeof(intmax_t) * CHAR_BIT - 1));
259 typedef ratio<1LL, 1000000000000000000LL> atto;
260 typedef ratio<1LL, 1000000000000000LL> femto;
261 typedef ratio<1LL, 1000000000000LL> pico;
262 typedef ratio<1LL, 1000000000LL> nano;
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 545 const IFListType &LL = I->second; in dump_map() local
546 for (unsigned i = 0, n = LL.size(); i < n; ++i) in dump_map()
547 dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", " in dump_map()
548 << PrintRegSet(LL[i].second, HRI) << '\n'; in dump_map()
829 const RSListType &LL = I->second; in findRecordInsertForms() local
830 for (unsigned i = 0, n = LL.size(); i < n; ++i) in findRecordInsertForms()
831 dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@" in findRecordInsertForms()
832 << LL[i].second << ')'; in findRecordInsertForms()
862 RSListType &LL = F->second; in findRecordInsertForms() local
863 for (unsigned i = 0, n = LL.size(); i < n; ++i) { in findRecordInsertForms()
[all …]
|
| /external/valgrind/callgrind/ |
| D | sim.c | 94 static cache_t2 I1, D1, LL; variable
319 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit; in cachesim_I1_ref()
327 if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit; in cachesim_D1_ref()
427 switch( cachesim_ref_wb( &LL, Read, a, size) ) { in cachesim_I1_Read()
439 switch( cachesim_ref_wb( &LL, Read, a, size) ) { in cachesim_D1_Read()
455 cachesim_ref_wb( &LL, Write, a, size); in cachesim_D1_Write()
458 switch( cachesim_ref_wb( &LL, Write, a, size) ) { in cachesim_D1_Write()
497 UInt block = ( a >> LL.line_size_bits); in prefetch_LL_doref()
509 cachesim_ref(&LL, a + 5 * LL.line_size,1); in prefetch_LL_doref()
519 cachesim_ref(&LL, a - 5 * LL.line_size,1); in prefetch_LL_doref()
[all …]
|
| /external/antlr/antlr-3.4/runtime/ObjC/Framework/test/runtime/sets/ |
| D | ANTLRBitSetTest.m | 18 static const unsigned long long bitData[] = {3LL, 1LL};
79 static const unsigned long long bitData[] = {3LL, 1LL};
89 static const unsigned long long bitData[] = {3LL, 1LL};
92 static const unsigned long long otherData[] = {5LL, 3LL, 1LL};
|
| /external/valgrind/cachegrind/ |
| D | cg_sim.c | 166 static cache_t2 LL; variable
174 cachesim_initcache(LLc, &LL); in cachesim_initcaches()
183 if (cachesim_ref_is_miss(&LL, a, size)) in cachesim_I1_doref_Gen()
198 UInt LL_set = block & LL.sets_min_1; in cachesim_I1_doref_NoX()
201 if (cachesim_setref_is_miss(&LL, LL_set, block)) in cachesim_I1_doref_NoX()
212 if (cachesim_ref_is_miss(&LL, a, size)) in cachesim_D1_doref()
228 if (I1.line_size_bits != LL.line_size_bits) return False; in cachesim_is_IrNoX()
|
| /external/valgrind/cachegrind/tests/ |
| D | notpower2.stderr.exp | 15 LL refs:
16 LL misses:
17 LL miss rate:
|
| D | chdir.stderr.exp | 15 LL refs:
16 LL misses:
17 LL miss rate:
|
| D | wrap5.stderr.exp | 15 LL refs:
16 LL misses:
17 LL miss rate:
|
| D | dlclose.stderr.exp | 15 LL refs:
16 LL misses:
17 LL miss rate:
|
| /external/valgrind/cachegrind/tests/x86/ |
| D | fpu-28-108.stderr.exp | 15 LL refs:
16 LL misses:
17 LL miss rate:
|
| /external/valgrind/callgrind/tests/ |
| D | notpower2-hwpref.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | simwork1.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | simwork-cache.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | notpower2.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | simwork2.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | notpower2-wb.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | simwork3.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | notpower2-use.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | threads-use.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| D | simwork-both.stderr.exp | 18 LL refs:
19 LL misses:
20 LL miss rate:
|
| /external/clang/test/Analysis/ |
| D | additive-folding-range-constraints.c | 106 clang_analyzer_eval((a - 5) > 0LL); // expected-warning{{UNKNOWN}} in mixedComparisons4()
108 if ((a - 5) > 0LL) { in mixedComparisons4()
117 clang_analyzer_eval((a + 5) == 0LL); // expected-warning{{UNKNOWN}} in mixedComparisons5()
119 if ((a + 5) == 0LL) { in mixedComparisons5()
154 clang_analyzer_eval((a + 5) < 0LL); // expected-warning{{UNKNOWN}} in mixedComparisons8()
156 if ((a + 5) < 0LL) { in mixedComparisons8()
|
| /external/clang/test/ARCMT/ |
| D | objcmt-numeric-literals.m | 67 [NSNumber numberWithChar:2LL];
97 [NSNumber numberWithUnsignedChar:2LL];
127 [NSNumber numberWithShort:2LL];
156 [NSNumber numberWithUnsignedShort:2LL];
185 [NSNumber numberWithInt:2LL];
220 [NSNumber numberWithUnsignedInt:2LL];
249 [NSNumber numberWithLong:2LL];
278 [NSNumber numberWithUnsignedLong:2LL];
307 [NSNumber numberWithLongLong:2LL];
336 [NSNumber numberWithUnsignedLongLong:2LL];
[all …]
|
| D | objcmt-numeric-literals.m.result | 67 [NSNumber numberWithChar:2LL];
97 [NSNumber numberWithUnsignedChar:2LL];
127 [NSNumber numberWithShort:2LL];
156 [NSNumber numberWithUnsignedShort:2LL];
302 @2LL;
303 @2LL;
305 @2LL;
307 @2LL;
319 @04LL;
320 @0LL;
[all …]
|
| /external/clang/test/Sema/ |
| D | arm64-inline-asm.c | 4 asm volatile("USE(%0)" :: "z"(0LL)); in foo()
5 asm volatile("USE(%x0)" :: "z"(0LL)); in foo()
|