| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 318 MULHU, MULHS, enumerator
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| D | SelectionDAG.h | 1088 case ISD::MULHS:
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 309 case ISD::MULHS: in selectNode()
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| D | MipsSEISelLowering.cpp | 116 setOperationAction(ISD::MULHS, MVT::i32, Custom); in MipsSETargetLowering()
127 setOperationAction(ISD::MULHS, MVT::i64, Custom); in MipsSETargetLowering()
161 setOperationAction(ISD::MULHS, MVT::i32, Legal); in MipsSETargetLowering()
208 setOperationAction(ISD::MULHS, MVT::i64, Legal); in MipsSETargetLowering()
367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); in LowerOperation()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 176 setOperationAction(ISD::MULHS, MVT::i64, Expand); in InitAMDILLowering()
177 setOperationAction(ISD::MULHS, MVT::v2i64, Expand); in InitAMDILLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 367 case ISD::MULHS: { in Select()
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| D | SparcISelLowering.cpp | 1657 setOperationAction(ISD::MULHS, MVT::i64, Expand); in SparcTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 284 X86_INTRINSIC_DATA(avx2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
1119 X86_INTRINSIC_DATA(avx512_mask_pmulh_w_128, INTR_TYPE_2OP_MASK, ISD::MULHS, 0),
1120 X86_INTRINSIC_DATA(avx512_mask_pmulh_w_256, INTR_TYPE_2OP_MASK, ISD::MULHS, 0),
1121 X86_INTRINSIC_DATA(avx512_mask_pmulh_w_512, INTR_TYPE_2OP_MASK, ISD::MULHS, 0),
1697 X86_INTRINSIC_DATA(sse2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
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| D | X86ISelLowering.cpp | 280 setOperationAction(ISD::MULHS, VT, Expand); in X86TargetLowering()
719 setOperationAction(ISD::MULHS, VT, Expand); in X86TargetLowering()
783 setOperationAction(ISD::MULHS, MMXTy, Expand); in X86TargetLowering()
832 setOperationAction(ISD::MULHS, MVT::v8i16, Legal); in X86TargetLowering()
1191 setOperationAction(ISD::MULHS, MVT::v16i16, Legal); in X86TargetLowering()
1634 setOperationAction(ISD::MULHS, MVT::v32i16, Legal); in X86TargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2765 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : in BuildSDIV()
2766 isOperationLegalOrCustom(ISD::MULHS, VT)) in BuildSDIV()
2767 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), in BuildSDIV()
2898 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT); in expandMUL()
2951 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL); in expandMUL()
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| D | SelectionDAGDumper.cpp | 179 case ISD::MULHS: return "mulhs"; in getOperationName()
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| D | LegalizeDAG.cpp | 3484 case ISD::MULHS: { in ExpandNode()
3506 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); in ExpandNode()
3604 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; in ExpandNode()
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| D | LegalizeVectorTypes.cpp | 2029 case ISD::MULHS: in WidenVectorResult()
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| D | DAGCombiner.cpp | 1373 case ISD::MULHS: return visitMULHS(N); in visit()
2603 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS)) in visitSMUL_LOHI()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 152 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 140 setOperationAction(ISD::MULHS, MVT::i8, Expand); in MSP430TargetLowering()
145 setOperationAction(ISD::MULHS, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 123 setOperationAction(ISD::MULHS, MVT::i64, Expand); in BPFTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 365 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 103 setOperationAction(ISD::MULHS, MVT::i32, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1687 setOperationAction(ISD::MULHS, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 271 setOperationAction(ISD::MULHS, MVT::i64, Expand); in AMDGPUTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3579 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
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| D | AArch64ISelLowering.cpp | 600 setOperationAction(ISD::MULHS, VT, Expand); in AArch64TargetLowering()
1629 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 452 setOperationAction(ISD::MULHS, VT, Expand); in ARMTargetLowering()
731 setOperationAction(ISD::MULHS, MVT::i32, Expand); in ARMTargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 192 setOperationAction(ISD::MULHS, VT, Expand); in SystemZTargetLowering()
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