| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 199 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
211 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
224 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
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| D | AMDILISelLowering.cpp | 174 setOperationAction(ISD::MULHU, MVT::i64, Expand); in InitAMDILLowering()
175 setOperationAction(ISD::MULHU, MVT::v2i64, Expand); in InitAMDILLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 310 case ISD::MULHU: { in selectNode()
311 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); in selectNode()
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| D | MipsSEISelLowering.cpp | 117 setOperationAction(ISD::MULHU, MVT::i32, Custom); in MipsSETargetLowering()
128 setOperationAction(ISD::MULHU, MVT::i64, Custom); in MipsSETargetLowering()
162 setOperationAction(ISD::MULHU, MVT::i32, Legal); in MipsSETargetLowering()
209 setOperationAction(ISD::MULHU, MVT::i64, Legal); in MipsSETargetLowering()
368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 366 case ISD::MULHU: in Select()
371 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; in Select()
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| D | SparcISelLowering.cpp | 1656 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 318 MULHU, MULHS, enumerator
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| D | SelectionDAG.h | 1087 case ISD::MULHU:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2843 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : in BuildUDIV()
2844 isOperationLegalOrCustom(ISD::MULHU, VT)) in BuildUDIV()
2845 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT)); in BuildUDIV()
2899 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT); in expandMUL()
2935 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL); in expandMUL()
2985 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL); in expandMUL()
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| D | SelectionDAGDumper.cpp | 178 case ISD::MULHU: return "mulhu"; in getOperationName()
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| D | LegalizeDAG.cpp | 3483 case ISD::MULHU: in ExpandNode()
3485 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : in ExpandNode()
3507 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); in ExpandNode()
3603 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in ExpandNode()
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| D | LegalizeVectorTypes.cpp | 2030 case ISD::MULHU: in WidenVectorResult()
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| D | DAGCombiner.cpp | 1372 case ISD::MULHU: return visitMULHU(N); in visit()
2634 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU)) in visitUMUL_LOHI()
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| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 285 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
1122 X86_INTRINSIC_DATA(avx512_mask_pmulhu_w_128, INTR_TYPE_2OP_MASK, ISD::MULHU, 0),
1123 X86_INTRINSIC_DATA(avx512_mask_pmulhu_w_256, INTR_TYPE_2OP_MASK, ISD::MULHU, 0),
1124 X86_INTRINSIC_DATA(avx512_mask_pmulhu_w_512, INTR_TYPE_2OP_MASK, ISD::MULHU, 0),
1698 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
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| D | X86ISelLowering.cpp | 281 setOperationAction(ISD::MULHU, VT, Expand); in X86TargetLowering()
721 setOperationAction(ISD::MULHU, VT, Expand); in X86TargetLowering()
831 setOperationAction(ISD::MULHU, MVT::v8i16, Legal); in X86TargetLowering()
1190 setOperationAction(ISD::MULHU, MVT::v16i16, Legal); in X86TargetLowering()
1635 setOperationAction(ISD::MULHU, MVT::v32i16, Legal); in X86TargetLowering()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 152 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 141 setOperationAction(ISD::MULHU, MVT::i8, Expand); in MSP430TargetLowering()
146 setOperationAction(ISD::MULHU, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 122 setOperationAction(ISD::MULHU, MVT::i64, Expand); in BPFTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 270 setOperationAction(ISD::MULHU, MVT::i64, Expand); in AMDGPUTargetLowering()
1752 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
1764 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
1777 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 366 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 104 setOperationAction(ISD::MULHU, MVT::i32, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3611 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
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| D | AArch64ISelLowering.cpp | 602 setOperationAction(ISD::MULHU, VT, Expand); in AArch64TargetLowering()
1638 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 454 setOperationAction(ISD::MULHU, VT, Expand); in ARMTargetLowering()
724 setOperationAction(ISD::MULHU, MVT::i32, Expand); in ARMTargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 193 setOperationAction(ISD::MULHU, VT, Expand); in SystemZTargetLowering()
|