Home
last modified time | relevance | path

Searched refs:Operands (Results 1 – 25 of 97) sorted by relevance

1234

/external/llvm/utils/TableGen/
DFastISelEmitter.cpp118 SmallVector<OpKind, 3> Operands; member
121 return Operands < O.Operands; in operator <()
124 return Operands == O.Operands; in operator ==()
127 bool empty() const { return Operands.empty(); } in empty()
130 for (unsigned i = 0, e = Operands.size(); i != e; ++i) in hasAnyImmediateCodes()
131 if (Operands[i].isImm() && Operands[i].getImmCode() != 0) in hasAnyImmediateCodes()
140 for (unsigned i = 0, e = Operands.size(); i != e; ++i) in getWithoutImmCodes()
141 if (!Operands[i].isImm()) in getWithoutImmCodes()
142 Result.Operands.push_back(Operands[i]); in getWithoutImmCodes()
144 Result.Operands.push_back(OpKind::getImm(0)); in getWithoutImmCodes()
[all …]
DPseudoLoweringEmitter.cpp93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) in addDagOperandMapping()
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); in addDagOperandMapping()
101 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) in addDagOperandMapping()
103 OpsAdded += Insn.Operands[i].MINumOperands; in addDagOperandMapping()
146 if (Insn.Operands.size() != Dag->getNumArgs()) in evaluateExpansion()
151 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) in evaluateExpansion()
152 NumMIOperands += Insn.Operands[i].MINumOperands; in evaluateExpansion()
170 for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i) in evaluateExpansion()
171 SourceOperands[SourceInsn.Operands[i].Name] = i; in evaluateExpansion()
174 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) { in evaluateExpansion()
[all …]
DAsmWriterInst.cpp166 Operands.emplace_back("PrintSpecial", ~0U, ~0U, Modifier, in AsmWriterInst()
170 unsigned OpNo = CGI.Operands.getOperandNamed(VarName); in AsmWriterInst()
171 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo]; in AsmWriterInst()
174 Operands.emplace_back(OpInfo.PrinterMethodName, OpNo, MIOp, Modifier, in AsmWriterInst()
181 Operands.emplace_back("return;", AsmWriterOperand::isLiteralStatementOperand); in AsmWriterInst()
189 if (Operands.size() != Other.Operands.size()) return ~1; in MatchesAllButOneOp()
192 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { in MatchesAllButOneOp()
193 if (Operands[i] != Other.Operands[i]) { in MatchesAllButOneOp()
DInstrInfoEmitter.cpp64 std::map<std::string, unsigned> &Operands,
91 for (auto &Op : Inst.Operands) { in GetOperandInfo()
203 std::map<std::string, unsigned> &Operands, in initOperandMapData() argument
211 for (const auto &Info : Inst->Operands) { in initOperandMapData()
212 StrUintMapIter I = Operands.find(Info.Name); in initOperandMapData()
214 if (I == Operands.end()) { in initOperandMapData()
215 I = Operands.insert(Operands.begin(), in initOperandMapData()
243 std::map<std::string, unsigned> Operands; in emitOperandNameMappings() local
246 initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap); in emitOperandNameMappings()
254 for (const auto &Op : Operands) in emitOperandNameMappings()
[all …]
DCodeEmitterGen.cpp88 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in AddCodeToMergeInOperand()
90 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in AddCodeToMergeInOperand()
91 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && in AddCodeToMergeInOperand()
94 unsigned NumberOps = CGI.Operands.size(); in AddCodeToMergeInOperand()
98 (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) || in AddCodeToMergeInOperand()
100 CGI.Operands.getSubOperandNumber(NumberedOp).first)))) { in AddCodeToMergeInOperand()
103 if (NumberedOp >= CGI.Operands.back().MIOperandNo + in AddCodeToMergeInOperand()
104 CGI.Operands.back().MINumOperands) { in AddCodeToMergeInOperand()
117 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in AddCodeToMergeInOperand()
118 std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName; in AddCodeToMergeInOperand()
[all …]
DAsmWriterInst.h93 std::vector<AsmWriterOperand> Operands;
108 if (!Operands.empty() && in AddLiteralString()
109 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand) in AddLiteralString()
110 Operands.back().Str.append(Str); in AddLiteralString()
112 Operands.push_back(AsmWriterOperand(Str)); in AddLiteralString()
DAsmWriterEmitter.cpp115 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { in EmitInstructions()
118 O << " " << FirstInst.Operands[i].getCode(); in EmitInstructions()
126 FirstInst.Operands[i])); in EmitInstructions()
132 AWI.Operands[i])); in EmitInstructions()
163 if (Inst->Operands.empty()) in FindUniqueOperandCommands()
166 Command = " " + Inst->Operands[0].getCode() + "\n"; in FindUniqueOperandCommands()
205 if (!FirstInst || FirstInst->Operands.size() == Op) in FindUniqueOperandCommands()
220 if (!OtherInst || OtherInst->Operands.size() == Op || in FindUniqueOperandCommands()
221 OtherInst->Operands[Op] != FirstInst->Operands[Op]) { in FindUniqueOperandCommands()
230 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n"; in FindUniqueOperandCommands()
[all …]
DFixedLenDecoderEmitter.cpp315 const std::map<unsigned, std::vector<OperandInfo> > &Operands; member in __anon60e3a3c10711::FilterChooser
345 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(), in FilterChooser()
356 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), in FilterChooser()
556 Owner->Operands, BitValueArray, *Owner))); in recurse()
583 Owner->Operands, BitValueArray, *Owner))); in recurse()
1094 for (const auto &Op : Operands.find(Opc)->second) { in emitDecoder()
1719 std::map<unsigned, std::vector<OperandInfo> > &Operands){ in populateInstruction()
1736 Operands[Opc] = InsnOperands; in populateInstruction()
1758 for (unsigned i = 0; i < CGI.Operands.size(); ++i) { in populateInstruction()
1759 int tiedTo = CGI.Operands[i].getTiedRegister(); in populateInstruction()
[all …]
DCodeGenInstruction.cpp296 : TheDef(R), Operands(R), InferredFrom(nullptr) { in CodeGenInstruction()
310 isPredicable = Operands.isPredicable || R->getValueAsBit("isPredicable"); in CodeGenInstruction()
342 ParseConstraints(R->getValueAsString("Constraints"), Operands); in CodeGenInstruction()
345 Operands.ProcessDisableEncoding(R->getValueAsString("DisableEncoding")); in CodeGenInstruction()
610 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { in CodeGenInstAlias()
615 if (ResultInst->Operands[i].MINumOperands == 1 && in CodeGenInstAlias()
616 ResultInst->Operands[i].getTiedRegister() != -1) in CodeGenInstAlias()
622 Record *InstOpRec = ResultInst->Operands[i].Rec; in CodeGenInstAlias()
623 unsigned NumSubOps = ResultInst->Operands[i].MINumOperands; in CodeGenInstAlias()
639 DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo; in CodeGenInstAlias()
[all …]
/external/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp418 OperandVector &Operands, MCStreamer &Out,
422 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
424 SMLoc NameLoc, OperandVector &Operands) override;
429 OperandVector &Operands,
432 OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands,
437 OperandVector &Operands);
440 void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
441 void cvtDS(MCInst &Inst, const OperandVector &Operands);
442 OperandMatchResultTy parseDSOptionalOps(OperandVector &Operands);
443 OperandMatchResultTy parseDSOff01OptionalOps(OperandVector &Operands);
[all …]
/external/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp370 OperandMatchResultTy parseRegister(OperandVector &Operands,
378 OperandMatchResultTy parseAddress(OperandVector &Operands,
382 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
385 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
402 SMLoc NameLoc, OperandVector &Operands) override;
404 OperandVector &Operands, MCStreamer &Out,
409 OperandMatchResultTy parseGR32(OperandVector &Operands) { in parseGR32() argument
410 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg); in parseGR32()
412 OperandMatchResultTy parseGRH32(OperandVector &Operands) { in parseGRH32() argument
413 return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg); in parseGRH32()
[all …]
/external/llvm/include/llvm/MC/
DMCInst.h153 SmallVector<MCOperand, 8> Operands;
164 const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
165 MCOperand &getOperand(unsigned i) { return Operands[i]; }
166 unsigned getNumOperands() const { return Operands.size(); }
168 void addOperand(const MCOperand &Op) { Operands.push_back(Op); }
172 void clear() { Operands.clear(); }
173 void erase(iterator I) { Operands.erase(I); }
174 size_t size() const { return Operands.size(); }
175 iterator begin() { return Operands.begin(); }
176 const_iterator begin() const { return Operands.begin(); }
[all …]
DMCTargetAsmParser.h156 SMLoc NameLoc, OperandVector &Operands) = 0;
158 AsmToken Token, OperandVector &Operands) { in ParseInstruction() argument
159 return ParseInstruction(Info, Name, Token.getLoc(), Operands); in ParseInstruction()
185 OperandVector &Operands, MCStreamer &Out,
208 const OperandVector &Operands) = 0;
/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp57 bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
59 bool parseCondCode(OperandVector &Operands, bool invertCondCode);
63 bool parseRegister(OperandVector &Operands);
65 bool parseVectorList(OperandVector &Operands);
66 bool parseOperand(OperandVector &Operands, bool isCondCode,
86 OperandVector &Operands, MCStreamer &Out,
97 OperandMatchResultTy tryParseOptionalShiftExtend(OperandVector &Operands);
98 OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
99 OperandMatchResultTy tryParseMRSSystemRegister(OperandVector &Operands);
100 OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
[all …]
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp688 OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
726 void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
729 OperandVector &Operands, MCStreamer &Out,
733 void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
740 OperandVector &Operands, MCStreamer &Out,
745 OperandVector &Operands, MCStreamer &Out,
759 bool HandleAVX512Operand(OperandVector &Operands,
820 SMLoc NameLoc, OperandVector &Operands) override;
1030 OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src, in AddDefaultSrcDestOperands() argument
1033 Operands.push_back(std::move(Dst)); in AddDefaultSrcDestOperands()
[all …]
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp114 OperandVector &Operands, MCStreamer &Out,
119 int processInstruction(MCInst &Inst, OperandVector const &Operands,
153 bool mustExtend(OperandVector &Operands);
154 bool splitIdentifier(OperandVector &Operands);
155 bool parseOperand(OperandVector &Operands);
156 bool parseInstruction(OperandVector &Operands);
157 bool implicitExpressionLocation(OperandVector &Operands);
158 bool parseExpressionOrOperand(OperandVector &Operands);
161 SMLoc NameLoc, OperandVector &Operands) override in ParseInstruction() argument
166 AsmToken ID, OperandVector &Operands) override;
[all …]
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp192 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
194 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
246 OperandVector &Operands);
337 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
338 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
372 SMLoc NameLoc, OperandVector &Operands) override;
380 OperandVector &Operands, MCStreamer &Out,
2971 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { in tryParseShiftRegister() argument
2997 (ARMOperand *)Operands.pop_back_val().release()); in tryParseShiftRegister()
3057 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, in tryParseShiftRegister()
[all …]
/external/llvm/include/llvm/Analysis/
DScalarEvolutionExpressions.h141 const SCEV *const *Operands;
146 : SCEV(ID, T), Operands(O), NumOperands(N) {} in SCEVNAryExpr()
152 return Operands[i]; in getOperand()
157 op_iterator op_begin() const { return Operands; } in op_begin()
158 op_iterator op_end() const { return Operands + NumOperands; } in op_end()
299 const SCEV *getStart() const { return Operands[0]; } in getStart()
585 SmallVector<const SCEV *, 2> Operands; in visitAddExpr() local
587 Operands.push_back(((SC*)this)->visit(Expr->getOperand(i))); in visitAddExpr()
588 return SE.getAddExpr(Operands); in visitAddExpr()
592 SmallVector<const SCEV *, 2> Operands; in visitMulExpr() local
[all …]
DTargetTransformInfoImpl.h106 ArrayRef<const Value *> Operands) { in getGEPCost() argument
109 for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx) in getGEPCost()
110 if (!isa<Constant>(Operands[Idx])) in getGEPCost()
401 ArrayRef<const Value *> Operands) { in getGEPCost() argument
417 auto GTI = gep_type_begin(PointerType::get(PointeeType, AS), Operands); in getGEPCost()
418 for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) { in getGEPCost()
/external/llvm/lib/Analysis/
DScalarEvolutionNormalization.cpp109 SmallVector<const SCEV *, 8> Operands; in TransformImpl() local
116 Operands.push_back(TransformSubExpr(*I, LUser, nullptr)); in TransformImpl()
119 const SCEV *Result = SE.getAddRecExpr(Operands, L, SCEV::FlagAnyWrap); in TransformImpl()
191 SmallVector<const SCEV *, 8> Operands; in TransformImpl() local
199 Operands.push_back(N); in TransformImpl()
204 case scAddExpr: return SE.getAddExpr(Operands); in TransformImpl()
205 case scMulExpr: return SE.getMulExpr(Operands); in TransformImpl()
206 case scSMaxExpr: return SE.getSMaxExpr(Operands); in TransformImpl()
207 case scUMaxExpr: return SE.getUMaxExpr(Operands); in TransformImpl()
/external/llvm/lib/IR/
DConstantsContext.h369 ArrayRef<Constant *> Operands;
370 ConstantAggrKeyType(ArrayRef<Constant *> Operands) : Operands(Operands) {}
371 ConstantAggrKeyType(ArrayRef<Constant *> Operands, const ConstantClass *)
372 : Operands(Operands) {}
378 Operands = Storage;
382 return Operands == X.Operands;
385 if (Operands.size() != C->getNumOperands())
387 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
388 if (Operands[I] != C->getOperand(I))
393 return hash_combine_range(Operands.begin(), Operands.end());
[all …]
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp134 OperandVector &Operands, MCStreamer &Out,
141 bool parseParenSuffix(StringRef Name, OperandVector &Operands);
143 bool parseBracketSuffix(StringRef Name, OperandVector &Operands);
146 SMLoc NameLoc, OperandVector &Operands) override;
150 OperandMatchResultTy parseMemOperand(OperandVector &Operands);
152 matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
154 OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
156 OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
157 OperandMatchResultTy parseImm(OperandVector &Operands);
158 OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
[all …]
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp50 OperandVector &Operands, MCStreamer &Out,
55 SMLoc NameLoc, OperandVector &Operands) override;
62 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
64 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
70 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
509 OperandVector &Operands, in MatchAndEmitInstruction() argument
515 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, in MatchAndEmitInstruction()
542 if (ErrorInfo >= Operands.size()) in MatchAndEmitInstruction()
545 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc(); in MatchAndEmitInstruction()
582 OperandVector &Operands) { in ParseInstruction() argument
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCBoolRetToInt.cpp133 const auto &Operands = P->operands(); in getPromotablePHINodes() local
135 !std::all_of(Operands.begin(), Operands.end(), IsValidOperand)) in getPromotablePHINodes()
152 const auto &Operands = P->operands(); in getPromotablePHINodes() local
154 !std::all_of(Operands.begin(), Operands.end(), IsPromotable)) in getPromotablePHINodes()
/external/llvm/lib/Transforms/IPO/
DArgumentPromotion.cpp503 IndicesVector Operands; in isSafeToPromoteArgument() local
506 Operands.clear(); in isSafeToPromoteArgument()
512 Operands.push_back(0); in isSafeToPromoteArgument()
528 Operands.push_back(C->getSExtValue()); in isSafeToPromoteArgument()
548 if (!PrefixIn(Operands, SafeToUnconditionallyLoad)) in isSafeToPromoteArgument()
554 if (ToPromote.find(Operands) == ToPromote.end()) { in isSafeToPromoteArgument()
563 ToPromote.insert(std::move(Operands)); in isSafeToPromoteArgument()
962 IndicesVector Operands; in DoPromotion() local
963 Operands.reserve(GEP->getNumIndices()); in DoPromotion()
966 Operands.push_back(cast<ConstantInt>(*II)->getSExtValue()); in DoPromotion()
[all …]

1234