| /external/llvm/test/CodeGen/ARM/ |
| D | rotate.ll | 4 ;; select ROTL. Make sure if generates the basic VSHL/VSHR.
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | rotate.ll | 4 ;; select ROTL. Make sure if generates the basic ushr/shl.
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 181 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, in addIPMSequence() local
183 return ROTL; in addIPMSequence()
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| D | SystemZISelDAGToDAG.cpp | 792 case ISD::ROTL: { in expandRxSBG()
1209 case ISD::ROTL: in Select()
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| /external/boringssl/src/decrepit/cast/ |
| D | cast.c | 85 #define ROTL(a, n) (_lrotl(a, n)) macro
87 #define ROTL(a, n) ((((a) << (n)) | ((a) >> ((-(n))&31))) & 0xffffffffL) macro
94 t = ROTL(t, (key[n * 2 + 1])); \
|
| /external/dbus/dbus/ |
| D | dbus-sha.c | 125 #define ROTL(n,X) ( ( ( X ) << n ) | ( ( X ) >> ( 32 - n ) ) ) macro
141 #define expand(W,i) ( W[ i & 15 ] = ROTL( 1, ( W[ i & 15 ] ^ W[ (i - 14) & 15 ] ^ \
159 ( e += ROTL( 5, a ) + f( b, c, d ) + k + data, b = ROTL( 30, b ) )
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 336 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | R600ISelLowering.cpp | 43 setOperationAction(ISD::ROTL, MVT::i32, Custom); in R600TargetLowering()
250 case ISD::ROTL: return LowerROTL(Op, DAG); in LowerOperation()
|
| /external/vboot_reference/firmware/2lib/ |
| D | 2sha256.c | 44 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| D | 2sha512.c | 44 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| /external/vboot_reference/firmware/lib/cryptolib/ |
| D | sha256.c | 45 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| D | sha512.c | 45 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 194 case ISD::ROTL: return "rotl"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 281 case ISD::ROTL: in LegalizeOp()
|
| D | DAGCombiner.cpp | 1389 case ISD::ROTL: return visitRotate(N); in visit()
3565 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) in MatchBSwapHWord()
3566 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt); in MatchBSwapHWord()
3977 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); in MatchRotate()
4019 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate()
4067 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL); in MatchRotate()
4072 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL); in MatchRotate()
4222 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0.getOpcode() == ISD::SHL in visitXOR()
4225 return DAG.getNode(ISD::ROTL, DL, VT, DAG.getConstant(~1, DL, VT), in visitXOR()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 151 {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI, in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 175 setOperationAction(ISD::ROTL, MVT::i64, Legal); in NVPTXTargetLowering()
178 setOperationAction(ISD::ROTL, MVT::i64, Expand); in NVPTXTargetLowering()
182 setOperationAction(ISD::ROTL, MVT::i32, Legal); in NVPTXTargetLowering()
185 setOperationAction(ISD::ROTL, MVT::i32, Expand); in NVPTXTargetLowering()
189 setOperationAction(ISD::ROTL, MVT::i16, Expand); in NVPTXTargetLowering()
191 setOperationAction(ISD::ROTL, MVT::i8, Expand); in NVPTXTargetLowering()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 97 setOperationAction(ISD::ROTL, MVT::i8, Expand); in MSP430TargetLowering()
99 setOperationAction(ISD::ROTL, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 133 setOperationAction(ISD::ROTL, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/mmc-utils/3rdparty/hmac_sha/ |
| D | sha2.c | 48 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 502 } else if (Opcode == ISD::ROTL) { in isRotateAndMask()
925 case ISD::ROTL: in getValueBits()
1973 case ISD::ROTL: in SelectBitPermutation()
2596 N->getOperand(0).getOpcode() != ISD::ROTL) { in Select()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 265 setOperationAction(ISD::ROTL, MVT::i32, Expand); in AMDGPUTargetLowering()
266 setOperationAction(ISD::ROTL, MVT::i64, Expand); in AMDGPUTargetLowering()
306 setOperationAction(ISD::ROTL, VT, Expand); in AMDGPUTargetLowering()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 852 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
857 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
|
| /external/valgrind/VEX/priv/ |
| D | guest_ppc_toIR.c | 1640 static IRExpr* /* :: Ity_I32/64 */ ROTL ( IRExpr* src, in ROTL() function
4772 r = ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) ); in dis_int_rot()
4784 r = ROTL(mkexpr(rS), mkU8(sh_imm)); in dis_int_rot()
4806 r = ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) ); in dis_int_rot()
4836 ROTL(mkexpr(rS), mkU8(sh_imm)), in dis_int_rot()
4854 r = ROTL( unop(Iop_64to32, mkexpr(rS)), in dis_int_rot()
4864 ROTL(mkexpr(rS), in dis_int_rot()
4882 r = ROTL( mkexpr(rS), unop(Iop_64to8, mkexpr(rB)) ); in dis_int_rot()
4903 r = ROTL(mkexpr(rS), mkU8(sh_imm)); in dis_int_rot()
4926 r = ROTL(mkexpr(rS), mkU8(sh_imm)); in dis_int_rot()
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1691 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1753 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
|