Searched refs:Reg64 (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 487 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
495 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {
513 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
519 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
525 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
531 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {
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| D | AArch64FastISel.cpp | 1832 unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass); in emitLoad() local
1834 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emitLoad()
1838 ResultReg = Reg64; in emitLoad()
3816 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in emiti1Ext() local
3818 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emiti1Ext()
3822 ResultReg = Reg64; in emiti1Ext()
4355 unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass); in optimizeIntExtLoad() local
4357 TII.get(AArch64::SUBREG_TO_REG), Reg64) in optimizeIntExtLoad()
4361 Reg = Reg64; in optimizeIntExtLoad()
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