| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 270 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
271 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
274 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12)); in getAddSubImmOpValue()
556 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
557 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
558 return ShiftVal == 8 ? 0 : 1; in getMoveVecShifterOpValue()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64TargetTransformInfo.cpp | 55 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
56 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
|
| D | AArch64FastISel.cpp | 1191 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1197 RHSIsKill, AArch64_AM::LSL, ShiftVal, SetFlags, in emitAddSub()
1215 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1222 RHSIsKill, ShiftType, ShiftVal, SetFlags, in emitAddSub()
1569 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp() local
1576 RHSIsKill, ShiftVal); in emitLogicalOp()
1586 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
1592 RHSIsKill, ShiftVal); in emitLogicalOp()
4490 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4519 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
[all …]
|
| D | AArch64ISelDAGToDAG.cpp | 563 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
570 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
571 if (ShiftVal > 4) in SelectArithExtendedRegister()
594 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
795 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
797 if (ShiftVal != 0 && ShiftVal != LegalShiftVal) in SelectExtendedSHL()
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1043 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
1055 if (ShiftVal != 0) in printArithExtend()
1056 O << ", lsl #" << ShiftVal; in printArithExtend()
1061 if (ShiftVal != 0) in printArithExtend()
1062 O << " #" << ShiftVal; in printArithExtend()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 1317 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1324 ShiftVal, WidthVal); in SelectS_BFE()
1338 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1339 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
1345 ShiftVal, WidthVal); in SelectS_BFE()
|
| D | AMDGPUISelLowering.cpp | 2552 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); in PerformDAGCombine() local
2554 BitsFrom, ShiftVal); in PerformDAGCombine()
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | ScalarReplAggregates.cpp | 2386 Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); in RewriteStoreUserOfWholeAlloca() local
2387 EltVal = Builder.CreateLShr(EltVal, ShiftVal, "sroa.store.elt"); in RewriteStoreUserOfWholeAlloca()
2432 Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); in RewriteStoreUserOfWholeAlloca() local
2433 EltVal = Builder.CreateLShr(EltVal, ShiftVal, "sroa.store.elt"); in RewriteStoreUserOfWholeAlloca()
2534 Value *ShiftVal = ConstantInt::get(SrcField->getType(), Shift); in RewriteLoadUserOfWholeAlloca() local
2535 SrcField = BinaryOperator::CreateShl(SrcField, ShiftVal, "", LI); in RewriteLoadUserOfWholeAlloca()
|
| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 1169 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
1170 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
|
| D | X86ISelLowering.cpp | 5303 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy); in getVShift() local
5304 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal)); in getVShift()
|
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCasts.cpp | 447 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
450 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
457 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 1807 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
1816 ShiftVal = Amount; in isSimpleShift()
1964 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
1967 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
1969 MaskVal >> ShiftVal, in adjustForTestUnderMask()
1970 CmpVal >> ShiftVal, in adjustForTestUnderMask()
1973 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
1976 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
1978 MaskVal << ShiftVal, in adjustForTestUnderMask()
1979 CmpVal << ShiftVal, in adjustForTestUnderMask()
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1723 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
1739 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
|
| /external/llvm/lib/Analysis/ |
| D | ValueTracking.cpp | 1980 auto ShiftVal = Shift->getLimitedValue(BitWidth - 1); in isKnownNonZero() local
1982 if (KnownOne.countLeadingZeros() < BitWidth - ShiftVal) in isKnownNonZero()
1985 if (KnownZero.countTrailingOnes() >= ShiftVal) in isKnownNonZero()
|
| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 6334 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue(); in EmitX86BuiltinExpr() local
6344 if (ShiftVal >= (2 * NumLaneElts)) in EmitX86BuiltinExpr()
6349 if (ShiftVal > NumLaneElts) { in EmitX86BuiltinExpr()
6350 ShiftVal -= NumLaneElts; in EmitX86BuiltinExpr()
6359 unsigned Idx = ShiftVal + i; in EmitX86BuiltinExpr()
|