/external/llvm/lib/CodeGen/ |
D | LiveRegMatrix.cpp | 97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument 98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign() 100 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); in assign() 101 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign() 103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in assign() 106 Matrix[Unit].unify(VirtReg, Range); in assign() 114 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign() argument 115 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign() 116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign() 118 VRM->clearVirt(VirtReg.reg); in unassign() [all …]
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D | RegAllocBase.cpp | 88 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local 89 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); in allocatePhysRegs() 92 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs() 93 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); in allocatePhysRegs() 94 aboutToRemoveInterval(*VirtReg); in allocatePhysRegs() 95 LIS->removeInterval(VirtReg->reg); in allocatePhysRegs() 106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs() 107 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); in allocatePhysRegs() 110 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); in allocatePhysRegs() 117 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); in allocatePhysRegs() [all …]
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D | RegAllocGreedy.cpp | 210 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage() 211 return ExtraRegInfo[VirtReg.reg].Stage; in getStage() 214 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument 216 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage() 355 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg); 360 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, 371 unsigned calculateRegionSplitCost(LiveInterval &VirtReg, 376 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, 381 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order, 492 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg() argument [all …]
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D | RegAllocFast.cpp | 72 unsigned VirtReg; // Virtual register number. member 78 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){} in LiveReg() 81 return TargetRegisterInfo::virtReg2Index(VirtReg); in getSparseSetIndex() 167 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); 172 void killVirtReg(unsigned VirtReg); 174 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); 180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg() argument 181 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg() 183 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const { in findLiveVirtReg() 184 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg() [all …]
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D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify() argument 40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify() 50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify() 52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify() 56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract() argument 67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); in extract() 104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { in isSeenInterference() 106 std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg); in isSeenInterference() 130 if (VirtReg->empty() || LiveUnion->empty()) { in collectInterferingVRegs() 136 VirtRegI = VirtReg->begin(); in collectInterferingVRegs() [all …]
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D | RegAllocBasic.cpp | 102 unsigned selectOrSplit(LiveInterval &VirtReg, 111 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences() argument 174 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in spillInterferences() 180 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) in spillInterferences() 186 " interferences with " << VirtReg << "\n"); in spillInterferences() 220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit() argument 226 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in selectOrSplit() 229 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit() 248 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) in selectOrSplit() [all …]
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D | VirtRegMap.cpp | 84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys() argument 85 unsigned Hint = MRI->getSimpleHint(VirtReg); in hasPreferredPhys() 90 return getPhys(VirtReg) == Hint; in hasPreferredPhys() 93 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { in hasKnownPreference() argument 94 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); in hasKnownPreference() 288 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local 289 if (MRI->reg_nodbg_empty(VirtReg)) in addMBBLiveIns() 291 LiveInterval &LI = LIS->getInterval(VirtReg); in addMBBLiveIns() 296 unsigned PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns() 371 unsigned VirtReg = MO.getReg(); in rewrite() local [all …]
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D | AllocationOrder.cpp | 30 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder() argument 37 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder() 38 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in AllocationOrder()
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D | RegisterCoalescer.h | 66 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair() argument 68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
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D | LiveDebugVariables.cpp | 308 UserValue *lookupVirtReg(unsigned VirtReg); 346 void mapVirtReg(unsigned VirtReg, UserValue *EC); 476 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { in mapVirtReg() argument 477 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs"); in mapVirtReg() 478 UserValue *&Leader = virtRegToEqClass[VirtReg]; in mapVirtReg() 482 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { in lookupVirtReg() argument 483 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg)) in lookupVirtReg() 916 unsigned VirtReg = Loc.getReg(); in rewriteLocations() local 917 if (VRM.isAssignedReg(VirtReg) && in rewriteLocations() 918 TargetRegisterInfo::isPhysicalRegister(VRM.getPhys(VirtReg))) { in rewriteLocations() [all …]
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D | AllocationOrder.h | 39 AllocationOrder(unsigned VirtReg,
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D | RegAllocBase.h | 93 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
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D | InlineSpiller.cpp | 856 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, in reMaterializeFor() argument 862 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops); in reMaterializeFor() 868 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor() 874 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) in reMaterializeFor() 890 markValueUsed(&VirtReg, ParentVNI); in reMaterializeFor() 898 markValueUsed(&VirtReg, ParentVNI); in reMaterializeFor() 925 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { in reMaterializeFor()
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D | MachineBasicBlock.cpp | 391 unsigned VirtReg = I->getOperand(0).getReg(); in addLiveIn() local 392 if (!MRI.constrainRegClass(VirtReg, RC)) in addLiveIn() 394 return VirtReg; in addLiveIn() 398 unsigned VirtReg = MRI.createVirtualRegister(RC); in addLiveIn() local 399 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg) in addLiveIn() 403 return VirtReg; in addLiveIn()
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D | TargetRegisterInfo.cpp | 337 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints() argument 344 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); in getRegAllocationHints()
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D | PHIElimination.cpp | 203 static bool isImplicitlyDefined(unsigned VirtReg, in isImplicitlyDefined() argument 205 for (MachineInstr &DI : MRI->def_instructions(VirtReg)) in isImplicitlyDefined()
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D | MachineTraceMetrics.cpp | 610 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp) in DataDep() 612 assert(TargetRegisterInfo::isVirtualRegister(VirtReg)); in DataDep() 613 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg); in DataDep()
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/external/llvm/include/llvm/CodeGen/ |
D | LiveIntervalUnion.h | 87 void unify(LiveInterval &VirtReg, const LiveRange &Range); 88 void unify(LiveInterval &VirtReg) { in unify() argument 89 unify(VirtReg, VirtReg); in unify() 93 void extract(LiveInterval &VirtReg, const LiveRange &Range); 94 void extract(LiveInterval &VirtReg) { in extract() argument 95 extract(VirtReg, VirtReg); in extract() 113 LiveInterval *VirtReg; variable 123 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {} in Query() 126 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), in Query() 132 VirtReg = nullptr; in clear() [all …]
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D | LiveRegMatrix.h | 103 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg); 108 void assign(LiveInterval &VirtReg, unsigned PhysReg); 113 void unassign(LiveInterval &VirtReg); 128 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0); 133 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg); 139 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned RegUnit);
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D | VirtRegMap.h | 130 bool hasPreferredPhys(unsigned VirtReg); 135 bool hasKnownPreference(unsigned VirtReg); 151 unsigned getOriginal(unsigned VirtReg) const { in getOriginal() argument 152 unsigned Orig = getPreSplitReg(VirtReg); in getOriginal() 153 return Orig ? Orig : VirtReg; in getOriginal()
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D | ScheduleDAGInstrs.h | 34 unsigned VirtReg; member 39 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit() 42 return TargetRegisterInfo::virtReg2Index(VirtReg); in getSparseSetIndex()
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D | RegisterPressure.h | 430 bool hasUntiedDef(unsigned VirtReg) const { 431 return UntiedDefs.count(VirtReg);
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonFrameLowering.cpp | 1097 unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in replacePredRegPseudoSpillCode() local 1108 VirtReg).addReg(SrcReg, getKillRegState(IsOrigSrcRegKilled)); in replacePredRegPseudoSpillCode() 1113 MI->getOperand(2).setReg(VirtReg); in replacePredRegPseudoSpillCode() 1124 unsigned VirtReg = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in replacePredRegPseudoSpillCode() local 1134 MI->getOperand(0).setReg(VirtReg); in replacePredRegPseudoSpillCode() 1140 .addReg(VirtReg, getKillRegState(true)); in replacePredRegPseudoSpillCode()
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/external/llvm/lib/Target/ARM/ |
D | ARMBaseRegisterInfo.h | 125 void getRegAllocationHints(unsigned VirtReg,
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D | ARMBaseRegisterInfo.cpp | 224 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints() argument 231 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); in getRegAllocationHints() 242 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); in getRegAllocationHints()
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