Searched refs:ZIP1 (Results 1 – 10 of 10) sorted by relevance
| /external/libhevc/decoder/arm64/ |
| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 244 ZIP1 v27.8b, v14.8b, v15.8b
247 ZIP1 v27.8b, v16.8b, v17.8b
251 ZIP1 v27.8b, v20.8b, v21.8b
254 ZIP1 v27.8b, v22.8b, v23.8b
263 ZIP1 v27.8h, v14.8h, v16.8h
266 ZIP1 v25.8h, v20.8h, v22.8h
269 ZIP1 v14.4s, v27.4s, v25.4s
272 ZIP1 v16.4s, v26.4s, v19.4s
310 ZIP1 v27.8b, v14.8b, v15.8b
313 ZIP1 v27.8b, v16.8b, v17.8b
[all …]
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| /external/libhevc/common/arm64/ |
| D | ihevc_sao_edge_offset_class1_chroma.s | 211 ZIP1 v27.8b, v5.8b, v17.8b
236 ZIP1 v27.8b, v24.8b, v25.8b
289 ZIP1 v27.8b, v24.8b, v25.8b
377 ZIP1 v27.8b, v5.8b, v17.8b
399 ZIP1 v27.8b, v24.8b, v25.8b
439 ZIP1 v27.8b, v24.8b, v25.8b
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| D | ihevc_sao_band_offset_chroma.s | 386 ZIP1 v28.8b, v5.8b, v6.8b
394 ZIP1 v28.8b, v13.8b, v14.8b
405 ZIP1 v28.8b, v17.8b, v18.8b
411 ZIP1 v28.8b, v21.8b, v22.8b
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| D | ihevc_sao_edge_offset_class0_chroma.s | 246 ZIP1 v1.8b, v16.8b, v17.8b
275 ZIP1 v1.8b, v26.8b, v27.8b
428 ZIP1 v1.8b, v16.8b, v17.8b
455 ZIP1 v1.8b, v26.8b, v27.8b
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| D | ihevc_sao_edge_offset_class3_chroma.s | 451 ZIP1 v31.8b, v22.8b, v23.8b
586 ZIP1 v31.8b, v24.8b, v25.8b
616 ZIP1 v31.8b, v22.8b, v23.8b
714 ZIP1 v31.8b, v22.8b, v23.8b
901 ZIP1 v31.8b, v24.8b, v25.8b
1084 ZIP1 v31.8b, v24.8b, v25.8b
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| D | ihevc_sao_edge_offset_class2_chroma.s | 468 ZIP1 v31.8b, v22.8b, v23.8b
596 ZIP1 v31.8b, v24.8b, v25.8b
633 ZIP1 v31.8b, v22.8b, v23.8b
724 ZIP1 v31.8b, v24.8b, v25.8b
890 ZIP1 v31.8b, v24.8b, v25.8b
1049 ZIP1 v31.8b, v24.8b, v25.8b
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 101 ZIP1, enumerator
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| D | AArch64ISelLowering.cpp | 878 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1"; in getTargetNodeName()
5393 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
5558 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; in LowerVECTOR_SHUFFLE()
5571 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; in LowerVECTOR_SHUFFLE()
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| D | AArch64InstrInfo.td | 199 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
3621 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
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| /external/vixl/doc/ |
| D | supported-instructions.md | 4641 ### ZIP1 ### subsection
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