/external/llvm/lib/Target/AMDGPU/ |
D | R600ClauseMergePass.cpp | 77 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm(); in getCFAluSize() 83 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm(); in isCFAluEnabled() 124 if (LatrCFAlu->getOperand(Mode0Idx).getImm() && in mergeIfPossible() 125 RootCFAlu->getOperand(Mode0Idx).getImm() && in mergeIfPossible() 126 (LatrCFAlu->getOperand(KBank0Idx).getImm() != in mergeIfPossible() 127 RootCFAlu->getOperand(KBank0Idx).getImm() || in mergeIfPossible() 128 LatrCFAlu->getOperand(KBank0LineIdx).getImm() != in mergeIfPossible() 129 RootCFAlu->getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible() 140 if (LatrCFAlu->getOperand(Mode1Idx).getImm() && in mergeIfPossible() 141 RootCFAlu->getOperand(Mode1Idx).getImm() && in mergeIfPossible() [all …]
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/external/llvm/lib/Target/AMDGPU/InstPrinter/ |
D | AMDGPUInstPrinter.cpp | 32 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand() 37 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmOperand() 42 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand() 47 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand() 52 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand() 57 if (MI->getOperand(OpNo).getImm()) in printOffen() 63 if (MI->getOperand(OpNo).getImm()) in printIdxen() 69 if (MI->getOperand(OpNo).getImm()) in printAddr64() 75 if (MI->getOperand(OpNo).getImm()) { in printMBUFOffset() 83 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printDSOffset() [all …]
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/external/llvm/lib/Target/ARM/InstPrinter/ |
D | ARMInstPrinter.cpp | 79 switch (MI->getOperand(0).getImm()) { in printInst() 120 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst() 131 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst() 142 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst() 151 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst() 157 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst() 180 MI->getOperand(3).getImm() == -4) { in printInst() 209 MI->getOperand(4).getImm() == 4) { in printInst() 304 MI->getOperand(0).getImm() == 0 && in printInst() 326 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">"); in printOperand() [all …]
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
D | AArch64MCCodeEmitter.cpp | 211 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue() 222 ImmVal = static_cast<uint32_t>(MO.getImm()); in getLdStUImm12OpValue() 243 return MO.getImm(); in getAdrLabelOpValue() 268 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue() 270 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() 274 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << 12)); in getAddSubImmOpValue() 296 return MO.getImm(); in getCondBranchTargetOpValue() 318 return MO.getImm(); in getLoadLiteralOpValue() 334 unsigned SignExtend = MI.getOperand(OpIdx).getImm(); in getMemExtendOpValue() 335 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm(); in getMemExtendOpValue() [all …]
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/external/llvm/lib/Target/PowerPC/InstPrinter/ |
D | PPCInstPrinter.cpp | 60 unsigned char SH = MI->getOperand(2).getImm(); in printInst() 61 unsigned char MB = MI->getOperand(3).getImm(); in printInst() 62 unsigned char ME = MI->getOperand(4).getImm(); in printInst() 93 unsigned char SH = MI->getOperand(2).getImm(); in printInst() 94 unsigned char ME = MI->getOperand(3).getImm(); in printInst() 116 unsigned char TH = MI->getOperand(0).getImm(); in printInst() 159 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand() 255 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand() 262 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU2ImmOperand() 269 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU3ImmOperand() [all …]
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
D | R600MCCodeEmitter.cpp | 100 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset in encodeInstruction() 109 int64_t Sampler = MI.getOperand(14).getImm(); in encodeInstruction() 112 MI.getOperand(2).getImm(), in encodeInstruction() 113 MI.getOperand(3).getImm(), in encodeInstruction() 114 MI.getOperand(4).getImm(), in encodeInstruction() 115 MI.getOperand(5).getImm() in encodeInstruction() 118 MI.getOperand(6).getImm() & 0x1F, in encodeInstruction() 119 MI.getOperand(7).getImm() & 0x1F, in encodeInstruction() 120 MI.getOperand(8).getImm() & 0x1F in encodeInstruction() 176 return MO.getImm(); in getMachineOpValue()
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/external/llvm/lib/Target/X86/InstPrinter/ |
D | X86ATTInstPrinter.cpp | 74 int64_t Imm = MI->getOperand(Op).getImm(); in printSSEAVXCC() 114 int64_t Imm = MI->getOperand(Op).getImm(); in printXOPCC() 130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; in printRoundingControl() 146 O << formatImm(Op.getImm()); in printPCRelImm() 169 O << markup("<imm:") << '$' << formatImm((int64_t)Op.getImm()) in printOperand() 176 (Op.getImm() > 255 || Op.getImm() < -256)) in printOperand() 177 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm()); in printOperand() 203 int64_t DispVal = DispSpec.getImm(); in printMemReference() 219 unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm(); in printMemReference() 275 O << formatImm(DispSpec.getImm()); in printMemOffset() [all …]
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D | X86IntelInstPrinter.cpp | 56 int64_t Imm = MI->getOperand(Op).getImm(); in printSSEAVXCC() 96 int64_t Imm = MI->getOperand(Op).getImm(); in printXOPCC() 112 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; in printRoundingControl() 127 O << formatImm(Op.getImm()); in printPCRelImm() 150 O << formatImm((int64_t)Op.getImm()); in printOperand() 160 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); in printMemReference() 192 int64_t DispVal = DispSpec.getImm(); in printMemReference() 245 O << formatImm(DispSpec.getImm()); in printMemOffset() 256 O << formatImm(MI->getOperand(Op).getImm() & 0xff); in printU8Imm()
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D | X86InstComments.cpp | 228 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments() 244 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments() 260 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments() 274 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments() 289 DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments() 342 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments() 353 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments() 369 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments() 384 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments() 399 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments() [all …]
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMMCCodeEmitter.cpp | 194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue() 294 unsigned SoImm = MO.getImm(); in getSOImmOpValue() 326 return MO.getImm(); in getModImmOpValue() 333 unsigned SoImm = MI.getOperand(Op).getImm(); in getT2SOImmOpValue() 366 return 64 - MI.getOperand(Op).getImm(); in getNEONVcvtImm32OpValue() 547 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue() 566 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues() 594 if (MO.isImm()) return MO.getImm(); in getBranchTargetOpValue() 632 return encodeThumbBLOffset(MO.getImm()); in getThumbBLTargetOpValue() 645 return encodeThumbBLOffset(MO.getImm()); in getThumbBLXTargetOpValue() [all …]
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D | ARMMCTargetDesc.cpp | 38 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo() 39 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo() 42 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo() 43 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo() 44 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo() 51 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo() 58 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo() 59 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo() 70 MI.getOperand(1).getImm() != 8) { in getITDeprecationInfo() 256 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) in isUnconditionalBranch() [all …]
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
D | AArch64InstPrinter.cpp | 73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst() 76 switch (Op3.getImm()) { in printInst() 112 int64_t immr = Op2.getImm(); in printInst() 113 int64_t imms = Op3.getImm(); in printInst() 143 if (Op2.getImm() > Op3.getImm()) { in printInst() 146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst() 154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst() 162 int ImmR = MI->getOperand(3).getImm(); in printInst() 163 int ImmS = MI->getOperand(4).getImm(); in printInst() 653 O << '[' << MI->getOperand(OpNum++).getImm() << ']'; in printInst() [all …]
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/external/llvm/lib/Target/SystemZ/InstPrinter/ |
D | SystemZInstPrinter.cpp | 45 O << MO.getImm(); in printOperand() 65 int64_t Value = MI->getOperand(OpNum).getImm(); in printUImmOperand() 72 int64_t Value = MI->getOperand(OpNum).getImm(); in printSImmOperand() 139 uint64_t Value = MI->getOperand(OpNum).getImm(); in printAccessRegOperand() 149 O.write_hex(MO.getImm()); in printPCRelOperand() 185 MI->getOperand(OpNum + 1).getImm(), 0, O); in printBDAddrOperand() 191 MI->getOperand(OpNum + 1).getImm(), in printBDXAddrOperand() 198 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); in printBDLAddrOperand() 199 uint64_t Length = MI->getOperand(OpNum + 2).getImm(); in printBDLAddrOperand() 209 MI->getOperand(OpNum + 1).getImm(), in printBDVAddrOperand() [all …]
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZAsmPrinter.cpp | 35 .addImm(MI->getOperand(1).getImm()); in lowerRILow() 40 .addImm(MI->getOperand(2).getImm()); in lowerRILow() 49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh() 54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh() 64 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow() 65 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow() 66 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow() 89 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad() 99 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore() 156 .addImm(MI->getOperand(2).getImm()); in EmitInstruction() [all …]
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D | SystemZInstrInfo.cpp | 70 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8); in splitMove() 78 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove() 79 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove() 95 OffsetMO.getImm()); in splitAdjDynAlloc() 115 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm())); in expandRIPseudo() 148 MI->getOperand(2).getImm()); in expandRXYPseudo() 204 MI->getOperand(2).getImm() == 0 && in isSimpleMove() 229 MI->getOperand(1).getImm() != 0 || in isStackSlotCopy() 231 MI->getOperand(4).getImm() != 0) in isStackSlotCopy() 235 int64_t Length = MI->getOperand(2).getImm(); in isStackSlotCopy() [all …]
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
D | PPCAsmParser.cpp | 390 int64_t getImm() const { in getImm() function 447 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } in isU1Imm() 448 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } in isU2Imm() 449 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } in isU3Imm() 450 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } in isU4Imm() 451 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } in isU5Imm() 452 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } in isS5Imm() 453 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } in isU6Imm() 455 isUInt<6>(getImm()) && in isU6ImmX2() 456 (getImm() & 1) == 0; } in isU6ImmX2() [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonCopyToCombine.cpp | 145 bool NotExt = Op1.isImm() && isInt<8>(Op1.getImm()); in isCombinableInstType() 162 return !Op.isImm() || !isInt<N>(Op.getImm()); in isGreaterThanNBitTFRI() 554 .addImm(LoOperand.getImm()); in emitCombineII() 559 .addImm(HiOperand.getImm()) in emitCombineII() 570 .addImm(LoOperand.getImm()); in emitCombineII() 575 .addImm(HiOperand.getImm()) in emitCombineII() 585 .addImm(LoOperand.getImm()); in emitCombineII() 590 .addImm(HiOperand.getImm()) in emitCombineII() 600 .addImm(LoOperand.getImm()); in emitCombineII() 605 .addImm(HiOperand.getImm()) in emitCombineII() [all …]
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D | HexagonInstrInfo.cpp | 243 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { in isLoadFromStackSlot() 267 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { in isStoreToStackSlot() 492 BccOpc = Cond[0].getImm(); in InsertBranch() 513 } else if (isEndLoopN(Cond[0].getImm())) { in InsertBranch() 514 int EndLoopOp = Cond[0].getImm(); in InsertBranch() 524 } else if (isNewValueJump(Cond[0].getImm())) { in InsertBranch() 537 addImm(Cond[2].getImm()).addMBB(TBB); in InsertBranch() 550 assert((!isNewValueJump(Cond[0].getImm())) && in InsertBranch() 553 if (isEndLoopN(Cond[0].getImm())) { in InsertBranch() 554 int EndLoopOp = Cond[0].getImm(); in InsertBranch() [all …]
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/external/llvm/lib/Target/MSP430/InstPrinter/ |
D | MSP430InstPrinter.cpp | 39 O << Op.getImm(); in printPCRelImmOperand() 53 O << '#' << Op.getImm(); in printOperand() 82 O << Disp.getImm(); in printSrcMemOperand() 92 unsigned CC = MI->getOperand(OpNo).getImm(); in printCCOperand()
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/external/llvm/lib/Target/AArch64/AsmParser/ |
D | AArch64AsmParser.cpp | 337 const MCExpr *getImm() const { in getImm() function in __anonc0bd67f90211::AArch64Operand 442 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm()); in isSImm9() 451 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm()); in isSImm7s4() 460 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm()); in isSImm7s8() 469 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm()); in isSImm7s16() 513 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm()); in isUImm12Offset() 515 return isSymbolicUImm12Offset(getImm(), Scale); in isUImm12Offset() 524 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm()); in isImm0_1() 533 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm()); in isImm0_7() 542 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm()); in isImm1_8() [all …]
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
D | MipsMCCodeEmitter.cpp | 57 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift() 96 int64_t pos = InstIn.getOperand(2).getImm(); in LowerDextDins() 98 int64_t size = InstIn.getOperand(3).getImm(); in LowerDextDins() 228 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTargetOpValue() 251 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTarget7OpValueMM() 273 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMMPC10() 295 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMM() 318 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTarget21OpValue() 341 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTarget26OpValue() 364 return MO.getImm() >> 1; in getBranchTarget26OpValueMM() [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMOptimizeBarriersPass.cpp | 66 if (MI.getOperand(0).getImm() == DMBType) { in runOnMachineFunction() 71 DMBType = MI.getOperand(0).getImm(); in runOnMachineFunction() 76 DMBType = MI.getOperand(0).getImm(); in runOnMachineFunction()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ConditionOptimizer.cpp | 158 unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm()); in findSuitableCompare() 162 } else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) { in findSuitableCompare() 238 const int OldImm = (int)CmpMI->getOperand(2).getImm(); in adjustCmp() 289 if (Cond[0].getImm() != -1) { in parseCond() 291 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond() 365 const int HeadImm = (int)HeadCmpMI->getOperand(2).getImm(); in runOnMachineFunction() 366 const int TrueImm = (int)TrueCmpMI->getOperand(2).getImm(); in runOnMachineFunction()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrInfo.cpp | 280 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && in isLoadFromStackSlot() 309 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && in isStoreToStackSlot() 335 if (MI->getOperand(3).getImm() != 0) in commuteInstructionImpl() 368 unsigned MB = MI->getOperand(4).getImm(); in commuteInstructionImpl() 369 unsigned ME = MI->getOperand(5).getImm(); in commuteInstructionImpl() 653 BuildMI(&MBB, DL, get(Cond[0].getImm() ? in InsertBranch() 656 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in InsertBranch() 658 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in InsertBranch() 662 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB); in InsertBranch() 668 BuildMI(&MBB, DL, get(Cond[0].getImm() ? in InsertBranch() [all …]
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/external/llvm/lib/Target/NVPTX/InstPrinter/ |
D | NVPTXInstPrinter.cpp | 85 O << markup("<imm:") << formatImm(Op.getImm()) << markup(">"); in printOperand() 95 int64_t Imm = MO.getImm(); in printCvtMode() 145 int64_t Imm = MO.getImm(); in printCmpMode() 219 int Imm = (int) MO.getImm(); in printLdStCode() 272 MI->getOperand(OpNum + 1).getImm() == 0) in printMemOperand()
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