| /external/clang/tools/libclang/ |
| D | CXCursor.h | 173 bool isPseudo() const { return C.data[1] != nullptr; } in isPseudo() function
175 assert(isPseudo()); in getAsMacroDefinition()
179 assert(!isPseudo()); in getAsMacroExpansion()
183 assert(isPseudo()); in getPseudoLoc()
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| D | CXCursor.cpp | 814 if (isPseudo()) in getName()
820 if (isPseudo()) in getDefinition()
825 if (isPseudo()) in getSourceRange()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64A53Fix835769.cpp | 155 if (!I.isPseudo()) in getLastNonPseudo()
214 if (!CurrInstr->isPseudo()) in runOnBasicBlock()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCShuffler.cpp | 36 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
60 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFInstrFormats.td | 32 let isPseudo = 1;
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstructions.td | 94 let isCodeGenOnly = 1, isPseudo = 1, usesCustomInserter = 1 in {
117 } // End isCodeGenOnly = 1, isPseudo = 1, hasCustomInserter = 1
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| D | AMDILInstrInfo.td | 172 let isPseudo = 1;
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| D | R600Instructions.td | 125 let isTerminator = 1, isBranch = 1, isPseudo = 1 in {
1100 let usesCustomInserter = 1, isPseudo = 1 in {
1137 } // End usesCustomInserter = 1, isPseudo = 1
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600Instructions.td | 744 let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in {
753 } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1
956 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1012 let isPseudo = 1;
1287 let isPseudo = 1 in {
1353 } // End isPseudo = 1
1361 let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU" in {
1372 } // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = "AMDGPU"
1493 let isPseudo = 1;
1604 let isPseudo = 1 in {
[all …]
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| D | SIInstrInfo.td | 652 let isPseudo = 1, isCodeGenOnly = 1 in {
668 let isPseudo = 1;
748 let isPseudo = 1;
815 let isPseudo = 1;
905 let isPseudo = 1;
1348 let isPseudo = 1;
1390 let isPseudo = 1;
1454 let isPseudo = 1;
1594 let isPseudo = 1, isCodeGenOnly = 1 in {
1757 let isPseudo = 1;
[all …]
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| D | AMDGPUInstructions.td | 448 let isCodeGenOnly = 1, isPseudo = 1 in {
499 } // End isCodeGenOnly = 1, isPseudo = 1
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonIntrinsicsV60.td | 25 let isPseudo = 1 in
31 let isPseudo = 1 in
38 let isPseudo = 1 in
44 let isPseudo = 1 in
50 let isPseudo = 1 in
56 let isPseudo = 1 in
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| D | HexagonInstrFormats.td | 357 let isCodeGenOnly = 1, isPseudo = 1 in
363 let isCodeGenOnly = 1, isPseudo = 1 in
369 let isCodeGenOnly = 1, isPseudo = 1 in
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| D | HexagonInstrInfoV5.td | 101 isCodeGenOnly = 1, isPseudo = 1 in
108 validSubTargets = HasV5SubT, isCodeGenOnly = 1, isPseudo = 1 in
115 hasSideEffects = 0, validSubTargets = HasV5SubT, isPseudo = 1 in
750 isPseudo = 1, InputType = "imm" in
758 isPseudo = 1, InputType = "imm" in
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| D | HexagonInstrInfoV60.td | 759 let isPseudo = 1, validSubTargets = HasV60SubT in
819 let isPseudo = 1, validSubTargets = HasV60SubT in
874 isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
902 opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
927 isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
941 isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
956 opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
970 opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
988 let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
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| D | HexagonInstrInfo.td | 722 let isCodeGenOnly = 1, isPseudo = 1 in
1011 let isPseudo = 1 in {
2009 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
2166 let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in
2286 let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0, isPseudo = 1 in
3650 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
3754 let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in
3919 let isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0, isPseudo = 1 in
4557 isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
4862 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
[all …]
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| D | HexagonInstrInfoVector.td | 289 let isPseudo = 1 in
295 let isPseudo = 1 in
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 208 bool isPseudo() const { return Flags & (1 << MCID::Pseudo); } in isPseudo() function
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| /external/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 200 if (!MI->isPseudo()) in runOnMachineFunction()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 255 bool isPseudo : 1; variable
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| D | PseudoLoweringEmitter.cpp | 142 if (Insn.isCodeGenOnly || Insn.isPseudo) in evaluateExpansion()
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| D | InstrInfoEmitter.cpp | 480 if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)"; in emitRecord()
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| /external/llvm/include/llvm/Target/ |
| D | Target.td | 391 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
411 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
415 // the printer/emitter, we can remove this attribute and just use isPseudo.
418 // isPseudo: Does not have encoding information and should be expanded,
496 bit isPseudo = 1;
758 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
898 bit isPseudo = 1;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFormats.td | 121 let isPseudo = 1;
136 let isPseudo = 1;
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreInstrFormats.td | 29 let isPseudo = 1;
|