1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// opcode - operation code. 16// rs - src reg. 17// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18// rd - dst reg, only used on 3 regs instr. 19// shamt - only used on shift instructions, contains the shift amount. 20// funct - combined with opcode field give us an operation code. 21// 22//===----------------------------------------------------------------------===// 23 24// Format specifies the encoding used by the instruction. This is part of the 25// ad-hoc solution used to emit machine instruction encodings by our machine 26// code emitter. 27class Format<bits<4> val> { 28 bits<4> Value = val; 29} 30 31def Pseudo : Format<0>; 32def FrmR : Format<1>; 33def FrmI : Format<2>; 34def FrmJ : Format<3>; 35def FrmFR : Format<4>; 36def FrmFI : Format<5>; 37def FrmOther : Format<6>; // Instruction w/ a custom format 38 39class MMRel; 40 41def Std2MicroMips : InstrMapping { 42 let FilterClass = "MMRel"; 43 // Instructions with the same BaseOpcode and isNVStore values form a row. 44 let RowFields = ["BaseOpcode"]; 45 // Instructions with the same predicate sense form a column. 46 let ColFields = ["Arch"]; 47 // The key column is the unpredicated instructions. 48 let KeyCol = ["se"]; 49 // Value columns are PredSense=true and PredSense=false 50 let ValueCols = [["se"], ["micromips"]]; 51} 52 53class StdMMR6Rel; 54 55def Std2MicroMipsR6 : InstrMapping { 56 let FilterClass = "StdMMR6Rel"; 57 // Instructions with the same BaseOpcode and isNVStore values form a row. 58 let RowFields = ["BaseOpcode"]; 59 // Instructions with the same predicate sense form a column. 60 let ColFields = ["Arch"]; 61 // The key column is the unpredicated instructions. 62 let KeyCol = ["se"]; 63 // Value columns are PredSense=true and PredSense=false 64 let ValueCols = [["se"], ["micromipsr6"]]; 65} 66 67class StdArch { 68 string Arch = "se"; 69} 70 71// Generic Mips Format 72class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 73 InstrItinClass itin, Format f>: Instruction 74{ 75 field bits<32> Inst; 76 Format Form = f; 77 78 let Namespace = "Mips"; 79 80 let Size = 4; 81 82 bits<6> Opcode = 0; 83 84 // Top 6 bits are the 'opcode' field 85 let Inst{31-26} = Opcode; 86 87 let OutOperandList = outs; 88 let InOperandList = ins; 89 90 let AsmString = asmstr; 91 let Pattern = pattern; 92 let Itinerary = itin; 93 94 // 95 // Attributes specific to Mips instructions... 96 // 97 bits<4> FormBits = Form.Value; 98 99 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 100 let TSFlags{3-0} = FormBits; 101 102 let DecoderNamespace = "Mips"; 103 104 field bits<32> SoftFail = 0; 105} 106 107// Mips32/64 Instruction Format 108class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 109 InstrItinClass itin, Format f, string opstr = ""> : 110 MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl { 111 let EncodingPredicates = [HasStdEnc]; 112 string BaseOpcode = opstr; 113 string Arch; 114} 115 116// Mips Pseudo Instructions Format 117class MipsPseudo<dag outs, dag ins, list<dag> pattern, 118 InstrItinClass itin = IIPseudo> : 119 MipsInst<outs, ins, "", pattern, itin, Pseudo> { 120 let isCodeGenOnly = 1; 121 let isPseudo = 1; 122} 123 124// Mips32/64 Pseudo Instruction Format 125class PseudoSE<dag outs, dag ins, list<dag> pattern, 126 InstrItinClass itin = IIPseudo> : 127 MipsPseudo<outs, ins, pattern, itin>, PredicateControl { 128 let EncodingPredicates = [HasStdEnc]; 129} 130 131// Pseudo-instructions for alternate assembly syntax (never used by codegen). 132// These are aliases that require C++ handling to convert to the target 133// instruction, while InstAliases can be handled directly by tblgen. 134class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 135 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl { 136 let isPseudo = 1; 137 let Pattern = []; 138} 139//===----------------------------------------------------------------------===// 140// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 141//===----------------------------------------------------------------------===// 142 143class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 144 list<dag> pattern, InstrItinClass itin>: 145 InstSE<outs, ins, asmstr, pattern, itin, FrmR> 146{ 147 bits<5> rd; 148 bits<5> rs; 149 bits<5> rt; 150 bits<5> shamt; 151 bits<6> funct; 152 153 let Opcode = op; 154 let funct = _funct; 155 156 let Inst{25-21} = rs; 157 let Inst{20-16} = rt; 158 let Inst{15-11} = rd; 159 let Inst{10-6} = shamt; 160 let Inst{5-0} = funct; 161} 162 163//===----------------------------------------------------------------------===// 164// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 165//===----------------------------------------------------------------------===// 166 167class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 168 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 169{ 170 bits<5> rt; 171 bits<5> rs; 172 bits<16> imm16; 173 174 let Opcode = op; 175 176 let Inst{25-21} = rs; 177 let Inst{20-16} = rt; 178 let Inst{15-0} = imm16; 179} 180 181class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 182 list<dag> pattern, InstrItinClass itin>: 183 InstSE<outs, ins, asmstr, pattern, itin, FrmI> 184{ 185 bits<5> rs; 186 bits<5> rt; 187 bits<16> imm16; 188 189 let Opcode = op; 190 191 let Inst{25-21} = rs; 192 let Inst{20-16} = rt; 193 let Inst{15-0} = imm16; 194} 195 196//===----------------------------------------------------------------------===// 197// Format J instruction class in Mips : <|opcode|address|> 198//===----------------------------------------------------------------------===// 199 200class FJ<bits<6> op> : StdArch 201{ 202 bits<26> target; 203 204 bits<32> Inst; 205 206 let Inst{31-26} = op; 207 let Inst{25-0} = target; 208} 209 210//===----------------------------------------------------------------------===// 211// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 212//===----------------------------------------------------------------------===// 213class MFC3OP_FM<bits<6> op, bits<5> mfmt> 214{ 215 bits<5> rt; 216 bits<5> rd; 217 bits<3> sel; 218 219 bits<32> Inst; 220 221 let Inst{31-26} = op; 222 let Inst{25-21} = mfmt; 223 let Inst{20-16} = rt; 224 let Inst{15-11} = rd; 225 let Inst{10-3} = 0; 226 let Inst{2-0} = sel; 227} 228 229class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch { 230 bits<5> rt; 231 bits<16> imm16; 232 233 bits<32> Inst; 234 235 let Inst{31-26} = op; 236 let Inst{25-21} = mfmt; 237 let Inst{20-16} = rt; 238 let Inst{15-0} = imm16; 239} 240 241class ADD_FM<bits<6> op, bits<6> funct> : StdArch { 242 bits<5> rd; 243 bits<5> rs; 244 bits<5> rt; 245 246 bits<32> Inst; 247 248 let Inst{31-26} = op; 249 let Inst{25-21} = rs; 250 let Inst{20-16} = rt; 251 let Inst{15-11} = rd; 252 let Inst{10-6} = 0; 253 let Inst{5-0} = funct; 254} 255 256class ADDI_FM<bits<6> op> : StdArch { 257 bits<5> rs; 258 bits<5> rt; 259 bits<16> imm16; 260 261 bits<32> Inst; 262 263 let Inst{31-26} = op; 264 let Inst{25-21} = rs; 265 let Inst{20-16} = rt; 266 let Inst{15-0} = imm16; 267} 268 269class SRA_FM<bits<6> funct, bit rotate> : StdArch { 270 bits<5> rd; 271 bits<5> rt; 272 bits<5> shamt; 273 274 bits<32> Inst; 275 276 let Inst{31-26} = 0; 277 let Inst{25-22} = 0; 278 let Inst{21} = rotate; 279 let Inst{20-16} = rt; 280 let Inst{15-11} = rd; 281 let Inst{10-6} = shamt; 282 let Inst{5-0} = funct; 283} 284 285class SRLV_FM<bits<6> funct, bit rotate> : StdArch { 286 bits<5> rd; 287 bits<5> rt; 288 bits<5> rs; 289 290 bits<32> Inst; 291 292 let Inst{31-26} = 0; 293 let Inst{25-21} = rs; 294 let Inst{20-16} = rt; 295 let Inst{15-11} = rd; 296 let Inst{10-7} = 0; 297 let Inst{6} = rotate; 298 let Inst{5-0} = funct; 299} 300 301class BEQ_FM<bits<6> op> : StdArch { 302 bits<5> rs; 303 bits<5> rt; 304 bits<16> offset; 305 306 bits<32> Inst; 307 308 let Inst{31-26} = op; 309 let Inst{25-21} = rs; 310 let Inst{20-16} = rt; 311 let Inst{15-0} = offset; 312} 313 314class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch { 315 bits<5> rs; 316 bits<16> offset; 317 318 bits<32> Inst; 319 320 let Inst{31-26} = op; 321 let Inst{25-21} = rs; 322 let Inst{20-16} = funct; 323 let Inst{15-0} = offset; 324} 325 326class BBIT_FM<bits<6> op> : StdArch { 327 bits<5> rs; 328 bits<5> p; 329 bits<16> offset; 330 331 bits<32> Inst; 332 333 let Inst{31-26} = op; 334 let Inst{25-21} = rs; 335 let Inst{20-16} = p; 336 let Inst{15-0} = offset; 337} 338 339class SLTI_FM<bits<6> op> : StdArch { 340 bits<5> rt; 341 bits<5> rs; 342 bits<16> imm16; 343 344 bits<32> Inst; 345 346 let Inst{31-26} = op; 347 let Inst{25-21} = rs; 348 let Inst{20-16} = rt; 349 let Inst{15-0} = imm16; 350} 351 352class MFLO_FM<bits<6> funct> : StdArch { 353 bits<5> rd; 354 355 bits<32> Inst; 356 357 let Inst{31-26} = 0; 358 let Inst{25-16} = 0; 359 let Inst{15-11} = rd; 360 let Inst{10-6} = 0; 361 let Inst{5-0} = funct; 362} 363 364class MTLO_FM<bits<6> funct> : StdArch { 365 bits<5> rs; 366 367 bits<32> Inst; 368 369 let Inst{31-26} = 0; 370 let Inst{25-21} = rs; 371 let Inst{20-6} = 0; 372 let Inst{5-0} = funct; 373} 374 375class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch { 376 bits<5> rd; 377 bits<5> rt; 378 379 bits<32> Inst; 380 381 let Inst{31-26} = 0x1f; 382 let Inst{25-21} = 0; 383 let Inst{20-16} = rt; 384 let Inst{15-11} = rd; 385 let Inst{10-6} = funct; 386 let Inst{5-0} = funct2; 387} 388 389class CLO_FM<bits<6> funct> : StdArch { 390 bits<5> rd; 391 bits<5> rs; 392 bits<5> rt; 393 394 bits<32> Inst; 395 396 let Inst{31-26} = 0x1c; 397 let Inst{25-21} = rs; 398 let Inst{20-16} = rt; 399 let Inst{15-11} = rd; 400 let Inst{10-6} = 0; 401 let Inst{5-0} = funct; 402 let rt = rd; 403} 404 405class LUI_FM : StdArch { 406 bits<5> rt; 407 bits<16> imm16; 408 409 bits<32> Inst; 410 411 let Inst{31-26} = 0xf; 412 let Inst{25-21} = 0; 413 let Inst{20-16} = rt; 414 let Inst{15-0} = imm16; 415} 416 417class JALR_FM { 418 bits<5> rd; 419 bits<5> rs; 420 421 bits<32> Inst; 422 423 let Inst{31-26} = 0; 424 let Inst{25-21} = rs; 425 let Inst{20-16} = 0; 426 let Inst{15-11} = rd; 427 let Inst{10-6} = 0; 428 let Inst{5-0} = 9; 429} 430 431class BGEZAL_FM<bits<5> funct> : StdArch { 432 bits<5> rs; 433 bits<16> offset; 434 435 bits<32> Inst; 436 437 let Inst{31-26} = 1; 438 let Inst{25-21} = rs; 439 let Inst{20-16} = funct; 440 let Inst{15-0} = offset; 441} 442 443class SYNC_FM : StdArch { 444 bits<5> stype; 445 446 bits<32> Inst; 447 448 let Inst{31-26} = 0; 449 let Inst{10-6} = stype; 450 let Inst{5-0} = 0xf; 451} 452 453class SYNCI_FM : StdArch { 454 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding). 455 bits<21> addr; 456 bits<5> rs = addr{20-16}; 457 bits<16> offset = addr{15-0}; 458 459 bits<32> Inst; 460 461 let Inst{31-26} = 0b000001; 462 let Inst{25-21} = rs; 463 let Inst{20-16} = 0b11111; 464 let Inst{15-0} = offset; 465} 466 467class MULT_FM<bits<6> op, bits<6> funct> : StdArch { 468 bits<5> rs; 469 bits<5> rt; 470 471 bits<32> Inst; 472 473 let Inst{31-26} = op; 474 let Inst{25-21} = rs; 475 let Inst{20-16} = rt; 476 let Inst{15-6} = 0; 477 let Inst{5-0} = funct; 478} 479 480class EXT_FM<bits<6> funct> : StdArch { 481 bits<5> rt; 482 bits<5> rs; 483 bits<5> pos; 484 bits<5> size; 485 486 bits<32> Inst; 487 488 let Inst{31-26} = 0x1f; 489 let Inst{25-21} = rs; 490 let Inst{20-16} = rt; 491 let Inst{15-11} = size; 492 let Inst{10-6} = pos; 493 let Inst{5-0} = funct; 494} 495 496class RDHWR_FM : StdArch { 497 bits<5> rt; 498 bits<5> rd; 499 500 bits<32> Inst; 501 502 let Inst{31-26} = 0x1f; 503 let Inst{25-21} = 0; 504 let Inst{20-16} = rt; 505 let Inst{15-11} = rd; 506 let Inst{10-6} = 0; 507 let Inst{5-0} = 0x3b; 508} 509 510class TEQ_FM<bits<6> funct> : StdArch { 511 bits<5> rs; 512 bits<5> rt; 513 bits<10> code_; 514 515 bits<32> Inst; 516 517 let Inst{31-26} = 0; 518 let Inst{25-21} = rs; 519 let Inst{20-16} = rt; 520 let Inst{15-6} = code_; 521 let Inst{5-0} = funct; 522} 523 524class TEQI_FM<bits<5> funct> : StdArch { 525 bits<5> rs; 526 bits<16> imm16; 527 528 bits<32> Inst; 529 530 let Inst{31-26} = 1; 531 let Inst{25-21} = rs; 532 let Inst{20-16} = funct; 533 let Inst{15-0} = imm16; 534} 535 536class WAIT_FM : StdArch { 537 bits<32> Inst; 538 539 let Inst{31-26} = 0x10; 540 let Inst{25} = 1; 541 let Inst{24-6} = 0; 542 let Inst{5-0} = 0x20; 543} 544 545class EXTS_FM<bits<6> funct> : StdArch { 546 bits<5> rt; 547 bits<5> rs; 548 bits<5> pos; 549 bits<5> lenm1; 550 551 bits<32> Inst; 552 553 let Inst{31-26} = 0x1c; 554 let Inst{25-21} = rs; 555 let Inst{20-16} = rt; 556 let Inst{15-11} = lenm1; 557 let Inst{10-6} = pos; 558 let Inst{5-0} = funct; 559} 560 561class MTMR_FM<bits<6> funct> : StdArch { 562 bits<5> rs; 563 564 bits<32> Inst; 565 566 let Inst{31-26} = 0x1c; 567 let Inst{25-21} = rs; 568 let Inst{20-6} = 0; 569 let Inst{5-0} = funct; 570} 571 572class POP_FM<bits<6> funct> : StdArch { 573 bits<5> rd; 574 bits<5> rs; 575 576 bits<32> Inst; 577 578 let Inst{31-26} = 0x1c; 579 let Inst{25-21} = rs; 580 let Inst{20-16} = 0; 581 let Inst{15-11} = rd; 582 let Inst{10-6} = 0; 583 let Inst{5-0} = funct; 584} 585 586class SEQ_FM<bits<6> funct> : StdArch { 587 bits<5> rd; 588 bits<5> rs; 589 bits<5> rt; 590 591 bits<32> Inst; 592 593 let Inst{31-26} = 0x1c; 594 let Inst{25-21} = rs; 595 let Inst{20-16} = rt; 596 let Inst{15-11} = rd; 597 let Inst{10-6} = 0; 598 let Inst{5-0} = funct; 599} 600 601class SEQI_FM<bits<6> funct> : StdArch { 602 bits<5> rs; 603 bits<5> rt; 604 bits<10> imm10; 605 606 bits<32> Inst; 607 608 let Inst{31-26} = 0x1c; 609 let Inst{25-21} = rs; 610 let Inst{20-16} = rt; 611 let Inst{15-6} = imm10; 612 let Inst{5-0} = funct; 613} 614 615//===----------------------------------------------------------------------===// 616// System calls format <op|code_|funct> 617//===----------------------------------------------------------------------===// 618 619class SYS_FM<bits<6> funct> : StdArch 620{ 621 bits<20> code_; 622 bits<32> Inst; 623 let Inst{31-26} = 0x0; 624 let Inst{25-6} = code_; 625 let Inst{5-0} = funct; 626} 627 628//===----------------------------------------------------------------------===// 629// Break instruction format <op|code_1|funct> 630//===----------------------------------------------------------------------===// 631 632class BRK_FM<bits<6> funct> : StdArch 633{ 634 bits<10> code_1; 635 bits<10> code_2; 636 bits<32> Inst; 637 let Inst{31-26} = 0x0; 638 let Inst{25-16} = code_1; 639 let Inst{15-6} = code_2; 640 let Inst{5-0} = funct; 641} 642 643//===----------------------------------------------------------------------===// 644// Exception return format <Cop0|1|0|funct> 645//===----------------------------------------------------------------------===// 646 647class ER_FM<bits<6> funct, bit LLBit> : StdArch 648{ 649 bits<32> Inst; 650 let Inst{31-26} = 0x10; 651 let Inst{25} = 1; 652 let Inst{24-7} = 0; 653 let Inst{6} = LLBit; 654 let Inst{5-0} = funct; 655} 656 657//===----------------------------------------------------------------------===// 658// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0> 659//===----------------------------------------------------------------------===// 660 661class EI_FM<bits<1> sc> : StdArch 662{ 663 bits<32> Inst; 664 bits<5> rt; 665 let Inst{31-26} = 0x10; 666 let Inst{25-21} = 0xb; 667 let Inst{20-16} = rt; 668 let Inst{15-11} = 0xc; 669 let Inst{10-6} = 0; 670 let Inst{5} = sc; 671 let Inst{4-0} = 0; 672} 673 674//===----------------------------------------------------------------------===// 675// 676// FLOATING POINT INSTRUCTION FORMATS 677// 678// opcode - operation code. 679// fs - src reg. 680// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 681// fd - dst reg, only used on 3 regs instr. 682// fmt - double or single precision. 683// funct - combined with opcode field give us an operation code. 684// 685//===----------------------------------------------------------------------===// 686 687//===----------------------------------------------------------------------===// 688// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 689//===----------------------------------------------------------------------===// 690 691class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 692 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 693{ 694 bits<5> ft; 695 bits<5> base; 696 bits<16> imm16; 697 698 let Opcode = op; 699 700 let Inst{25-21} = base; 701 let Inst{20-16} = ft; 702 let Inst{15-0} = imm16; 703} 704 705class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch { 706 bits<5> fd; 707 bits<5> fs; 708 bits<5> ft; 709 710 bits<32> Inst; 711 712 let Inst{31-26} = 0x11; 713 let Inst{25-21} = fmt; 714 let Inst{20-16} = ft; 715 let Inst{15-11} = fs; 716 let Inst{10-6} = fd; 717 let Inst{5-0} = funct; 718} 719 720class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch { 721 bits<5> fd; 722 bits<5> fs; 723 724 bits<32> Inst; 725 726 let Inst{31-26} = 0x11; 727 let Inst{25-21} = fmt; 728 let Inst{20-16} = 0; 729 let Inst{15-11} = fs; 730 let Inst{10-6} = fd; 731 let Inst{5-0} = funct; 732} 733 734class MFC1_FM<bits<5> funct> : StdArch { 735 bits<5> rt; 736 bits<5> fs; 737 738 bits<32> Inst; 739 740 let Inst{31-26} = 0x11; 741 let Inst{25-21} = funct; 742 let Inst{20-16} = rt; 743 let Inst{15-11} = fs; 744 let Inst{10-0} = 0; 745} 746 747class LW_FM<bits<6> op> : StdArch { 748 bits<5> rt; 749 bits<21> addr; 750 751 bits<32> Inst; 752 753 let Inst{31-26} = op; 754 let Inst{25-21} = addr{20-16}; 755 let Inst{20-16} = rt; 756 let Inst{15-0} = addr{15-0}; 757} 758 759class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch { 760 bits<5> fd; 761 bits<5> fr; 762 bits<5> fs; 763 bits<5> ft; 764 765 bits<32> Inst; 766 767 let Inst{31-26} = 0x13; 768 let Inst{25-21} = fr; 769 let Inst{20-16} = ft; 770 let Inst{15-11} = fs; 771 let Inst{10-6} = fd; 772 let Inst{5-3} = funct; 773 let Inst{2-0} = fmt; 774} 775 776class LWXC1_FM<bits<6> funct> : StdArch { 777 bits<5> fd; 778 bits<5> base; 779 bits<5> index; 780 781 bits<32> Inst; 782 783 let Inst{31-26} = 0x13; 784 let Inst{25-21} = base; 785 let Inst{20-16} = index; 786 let Inst{15-11} = 0; 787 let Inst{10-6} = fd; 788 let Inst{5-0} = funct; 789} 790 791class SWXC1_FM<bits<6> funct> : StdArch { 792 bits<5> fs; 793 bits<5> base; 794 bits<5> index; 795 796 bits<32> Inst; 797 798 let Inst{31-26} = 0x13; 799 let Inst{25-21} = base; 800 let Inst{20-16} = index; 801 let Inst{15-11} = fs; 802 let Inst{10-6} = 0; 803 let Inst{5-0} = funct; 804} 805 806class BC1F_FM<bit nd, bit tf> : StdArch { 807 bits<3> fcc; 808 bits<16> offset; 809 810 bits<32> Inst; 811 812 let Inst{31-26} = 0x11; 813 let Inst{25-21} = 0x8; 814 let Inst{20-18} = fcc; 815 let Inst{17} = nd; 816 let Inst{16} = tf; 817 let Inst{15-0} = offset; 818} 819 820class CEQS_FM<bits<5> fmt> : StdArch { 821 bits<5> fs; 822 bits<5> ft; 823 bits<4> cond; 824 825 bits<32> Inst; 826 827 let Inst{31-26} = 0x11; 828 let Inst{25-21} = fmt; 829 let Inst{20-16} = ft; 830 let Inst{15-11} = fs; 831 let Inst{10-8} = 0; // cc 832 let Inst{7-4} = 0x3; 833 let Inst{3-0} = cond; 834} 835 836class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { 837 let cond = c; 838} 839 840class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch { 841 bits<5> fd; 842 bits<5> fs; 843 bits<5> rt; 844 845 bits<32> Inst; 846 847 let Inst{31-26} = 0x11; 848 let Inst{25-21} = fmt; 849 let Inst{20-16} = rt; 850 let Inst{15-11} = fs; 851 let Inst{10-6} = fd; 852 let Inst{5-0} = funct; 853} 854 855class CMov_F_I_FM<bit tf> : StdArch { 856 bits<5> rd; 857 bits<5> rs; 858 bits<3> fcc; 859 860 bits<32> Inst; 861 862 let Inst{31-26} = 0; 863 let Inst{25-21} = rs; 864 let Inst{20-18} = fcc; 865 let Inst{17} = 0; 866 let Inst{16} = tf; 867 let Inst{15-11} = rd; 868 let Inst{10-6} = 0; 869 let Inst{5-0} = 1; 870} 871 872class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch { 873 bits<5> fd; 874 bits<5> fs; 875 bits<3> fcc; 876 877 bits<32> Inst; 878 879 let Inst{31-26} = 0x11; 880 let Inst{25-21} = fmt; 881 let Inst{20-18} = fcc; 882 let Inst{17} = 0; 883 let Inst{16} = tf; 884 let Inst{15-11} = fs; 885 let Inst{10-6} = fd; 886 let Inst{5-0} = 0x11; 887} 888 889class BARRIER_FM<bits<5> op> : StdArch { 890 bits<32> Inst; 891 892 let Inst{31-26} = 0; // SPECIAL 893 let Inst{25-21} = 0; 894 let Inst{20-16} = 0; // rt = 0 895 let Inst{15-11} = 0; // rd = 0 896 let Inst{10-6} = op; // Operation 897 let Inst{5-0} = 0; // SLL 898} 899 900class SDBBP_FM : StdArch { 901 bits<20> code_; 902 903 bits<32> Inst; 904 905 let Inst{31-26} = 0b011100; // SPECIAL2 906 let Inst{25-6} = code_; 907 let Inst{5-0} = 0b111111; // SDBBP 908} 909 910class JR_HB_FM<bits<6> op> : StdArch{ 911 bits<5> rs; 912 913 bits<32> Inst; 914 915 let Inst{31-26} = 0; // SPECIAL 916 let Inst{25-21} = rs; 917 let Inst{20-11} = 0; 918 let Inst{10} = 1; 919 let Inst{9-6} = 0; 920 let Inst{5-0} = op; 921} 922 923class JALR_HB_FM<bits<6> op> : StdArch { 924 bits<5> rd; 925 bits<5> rs; 926 927 bits<32> Inst; 928 929 let Inst{31-26} = 0; // SPECIAL 930 let Inst{25-21} = rs; 931 let Inst{20-16} = 0; 932 let Inst{15-11} = rd; 933 let Inst{10} = 1; 934 let Inst{9-6} = 0; 935 let Inst{5-0} = op; 936} 937 938class COP0_TLB_FM<bits<6> op> : StdArch { 939 bits<32> Inst; 940 941 let Inst{31-26} = 0x10; // COP0 942 let Inst{25} = 1; // CO 943 let Inst{24-6} = 0; 944 let Inst{5-0} = op; // Operation 945} 946 947class CACHEOP_FM<bits<6> op> : StdArch { 948 bits<21> addr; 949 bits<5> hint; 950 bits<5> base = addr{20-16}; 951 bits<16> offset = addr{15-0}; 952 953 bits<32> Inst; 954 955 let Inst{31-26} = op; 956 let Inst{25-21} = base; 957 let Inst{20-16} = hint; 958 let Inst{15-0} = offset; 959} 960