| /external/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 72 if (MO.isReg() && MO.isUse() && MO.readsReg()) in canTurnIntoImplicitDef()
112 if (MO.isUse()) in processImplicitDef()
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| D | ExpandPostRAPseudos.cpp | 74 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) in TransferImplicitDefs()
84 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
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| D | MachineInstr.cpp | 349 if (isUndef() && isUse()) { in print()
814 if (NewMO->isUse()) { in addOperand()
1099 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1183 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
1215 if (MO.isUse()) in readsWritesVirtualRegister()
1295 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1327 if (MO.isUse()) in findTiedOperandIdx()
1332 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1375 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1539 if (!MO.isReg() || MO.isUse()) in allDefsAreDead()
[all …]
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| D | RegisterScavenging.cpp | 133 if (MO.isUse()) { in determineKillsAndDefs()
204 if (MO.isUse()) { in forward()
376 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) && in scavengeRegister()
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| D | MachineSink.cpp | 374 if (!MO.isReg() || !MO.isUse()) in isWorthBreakingCriticalEdge()
607 if (MO.isUse()) { in FindSuccToSinkTo()
619 if (MO.isUse()) continue; in FindSuccToSinkTo()
808 if (MO.isReg() && MO.isUse()) in SinkInstruction()
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| D | TwoAddressInstructionPass.cpp | 207 if (MO.isUse() && MOReg != SavedReg) in sink3AddrInstruction()
367 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
478 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
1057 if (MO.isUse()) { in rescheduleKillAboveMI()
1097 if (MO.isUse()) { in rescheduleKillAboveMI()
1347 if (MO.isUse()) { in tryInstructionTransform()
1426 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1539 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
1565 MO.isUse()) { in processTiedPairs()
1601 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
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| D | RegAllocFast.cpp | 236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
610 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) in defineVirtReg()
642 if (MO.isUse()) in reloadVirtReg()
742 if (MO.isUse()) { in handleThroughOperands()
931 if (MO.isUse()) { in AllocateBasicBlock()
943 if (MO.isUse()) { in AllocateBasicBlock()
979 if (MO.isUse()) { in AllocateBasicBlock()
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| D | CriticalAntiDepBreaker.cpp | 227 if (MO.isUse() && Special) { in PrescanInstruction()
291 if (!MO.isUse()) continue; in ScanInstruction()
602 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
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| D | MachineCSE.cpp | 127 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY()
197 if (MO.isUse()) in isPhysDefTriviallyDead()
403 if (MO.isReg() && MO.isUse() && in isProfitableToCSE()
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| D | DeadMachineInstructionElim.cpp | 159 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
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| D | LivePhysRegs.cpp | 88 assert(O->isUse()); in stepForward()
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| D | LiveIntervalAnalysis.cpp | 767 if (MO.isUse()) { in addKillFlags()
841 LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
846 return (isDef + isUse) * (Freq.getFrequency() * Scale); in getSpillWeight()
967 if (MO.isUse()) in updateAllRanges()
1062 if (MO->isReg() && MO->isUse()) in handleMoveDown()
1359 } else if (MO.isUse()) { in repairOldRegInRange()
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| D | BranchFolding.cpp | 174 if (!MO.isReg() || !MO.isUse()) in OptimizeImpDefsBlock()
1648 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1679 if (!MO.isReg() || MO.isUse()) in findHoistingInsertPosAndDeps()
1713 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1842 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) in HoistCommonCodeInSuccs()
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| D | InlineSpiller.cpp | 874 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) in reMaterializeFor()
925 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { in reMaterializeFor()
1138 if (MO->isUse()) in foldMemoryOperand()
1307 if (MO.isUse()) { in spillAroundUses()
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| /external/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 265 if (MO.isUse()) { in delayHasHazard()
290 assert(Reg.isUse() && "CALL first operand is not a use."); in insertCallDefsUses()
297 assert(RegOrImm.isUse() && "CALLrr second operand is not a use."); in insertCallDefsUses()
318 if (MO.isUse()) { in insertDefsUses()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 767 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
782 if (Op->isUse()) in advance()
869 if ((!ReturnUses && op->isUse()) || in defusechain_instr_iterator()
884 if (Op->isUse()) in advance()
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| D | MachineOperand.h | 277 bool isUse() const { in isUse() function
336 return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); in readsReg()
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| D | LiveIntervalAnalysis.h | 106 static float getSpillWeight(bool isDef, bool isUse,
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInsertWaits.cpp | 230 if (I->isReg() && I->isUse()) in isOpRelevant()
314 if (Op.isUse()) in pushInstruction()
420 if (Op.isUse()) in handleOperands()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonNewValueJump.cpp | 153 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
605 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
612 if (localMO.isReg() && localMO.isUse() && in runOnMachineFunction()
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| D | HexagonGenPredicate.cpp | 240 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
336 if (Mo->isReg() && Mo->isUse()) in isScalarPred()
358 if (!MO.isReg() || !MO.isUse()) in convertToPredForm()
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| D | HexagonExpandCondsets.cpp | 277 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) in makeDefined()
366 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) in updateKillFlags()
514 if (!Op.isReg() || !Op.isUse() || Op.isImplicit() || Op.isUndef()) in addInstrToLiveness()
631 if (!Op.isReg() || !Op.isUse()) in removeInstrFromLiveness()
1115 if (MO.isReg() && MO.isUse() && MO.isImplicit()) in removeImplicitUses()
1142 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.isUndef()) { in postprocessUndefImplicitUses()
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| D | HexagonVLIWPacketizer.cpp | 283 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) in isCallDependent()
461 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
682 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg) in canPromoteToNewValueStore()
827 if (Op.isReg() && Op.getReg() && Op.isUse() && in getPredicatedRegister()
1537 if (Op.isReg() && Op.isUse() && Op.getReg() == DstReg) in isDependent()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegColoring.cpp | 68 weight += LiveIntervals::getSpillWeight(MO.isDef(), MO.isUse(), MBFI, in computeWeight()
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| D | WebAssemblyRegStackify.cpp | 153 if (!Op.isReg() || Op.isImplicit() || !Op.isUse()) in runOnMachineFunction()
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