| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7); in idct32x8_row_even_process_store()
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
66 DOTP_CONST_PAIR(reg0, reg7, cospi_30_64, cospi_2_64, reg0, reg7); in idct32x8_row_even_process_store()
77 reg5 = reg7 + reg3; in idct32x8_row_even_process_store()
78 reg7 = reg7 - reg3; in idct32x8_row_even_process_store()
87 DOTP_CONST_PAIR(reg7, reg0, cospi_24_64, cospi_8_64, reg0, reg7); in idct32x8_row_even_process_store()
92 vec1 = reg7 - reg1; in idct32x8_row_even_process_store()
[all …]
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| D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vpx_idct16_1d_rows_msa()
24 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
41 DOTP_CONST_PAIR(reg9, reg7, cospi_14_64, cospi_18_64, loc2, loc3); in vpx_idct16_1d_rows_msa()
45 reg7 = reg15 - loc3; in vpx_idct16_1d_rows_msa()
65 DOTP_CONST_PAIR(reg7, reg9, cospi_24_64, cospi_8_64, reg7, reg9); in vpx_idct16_1d_rows_msa()
73 loc0 = reg7 + reg11; in vpx_idct16_1d_rows_msa()
74 reg11 = reg7 - reg11; in vpx_idct16_1d_rows_msa()
86 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vpx_idct16_1d_rows_msa()
[all …]
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | pv.ll | 6 …float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) #0 {
32 %24 = extractelement <4 x float> %reg7, i32 0
33 %25 = extractelement <4 x float> %reg7, i32 1
34 %26 = extractelement <4 x float> %reg7, i32 2
35 %27 = extractelement <4 x float> %reg7, i32 3
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| D | big_alu.ll | 6 …eg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg …
50 %42 = extractelement <4 x float> %reg7, i32 0
51 %43 = extractelement <4 x float> %reg7, i32 1
52 %44 = extractelement <4 x float> %reg7, i32 2
53 %45 = extractelement <4 x float> %reg7, i32 3
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| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 212 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument
219 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
249 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument
257 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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| D | assembler-arm64.h | 353 const CPURegister& reg7 = NoReg,
366 const CPURegister& reg7 = NoCPUReg,
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| /external/elfutils/tests/ |
| D | run-addrcfi.sh | 40 integer reg7 (%edi): same_value
87 integer reg7 (%edi): same_value
139 integer reg7 (%rsp): location expression: call_frame_cfa stack_value
205 integer reg7 (%rsp): location expression: call_frame_cfa stack_value
309 integer reg7 (r7): undefined
1331 integer reg7 (r7): undefined
2359 integer reg7 (r7): undefined
3385 integer reg7 (%r7): same_value
3462 integer reg7 (%r7): same_value
3540 integer reg7 (r7): same_value
[all …]
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| /external/llvm/include/llvm/Support/ |
| D | Dwarf.def | 203 HANDLE_DW_OP(0x57, reg7)
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| /external/v8/src/x87/ |
| D | macro-assembler-x87.cc | 2701 Register reg7, in AreAliased() argument
2705 reg7.is_valid() + reg8.is_valid(); in AreAliased()
2714 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-x87.h | 49 Register reg6 = no_reg, Register reg7 = no_reg,
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| /external/v8/src/ia32/ |
| D | macro-assembler-ia32.cc | 2829 Register reg7, in AreAliased() argument
2833 reg7.is_valid() + reg8.is_valid(); in AreAliased()
2842 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-ia32.h | 49 Register reg6 = no_reg, Register reg7 = no_reg,
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| /external/v8/src/arm/ |
| D | macro-assembler-arm.cc | 3537 Register reg7, in AreAliased() argument
3541 reg7.is_valid() + reg8.is_valid(); in AreAliased()
3550 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-arm.h | 78 Register reg7 = no_reg,
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| /external/elfutils/libdw/ |
| D | known-dwarf.h | 527 DWARF_ONE_KNOWN_DW_OP (reg7, DW_OP_reg7) \
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| /external/v8/src/ppc/ |
| D | macro-assembler-ppc.cc | 4241 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
4245 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased()
4255 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-ppc.h | 68 Register reg6 = no_reg, Register reg7 = no_reg,
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.cc | 5403 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument
5410 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
5438 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument
5446 match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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| D | assembler-a64.h | 416 const CPURegister& reg7 = NoReg,
430 const CPURegister& reg7 = NoCPUReg,
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| /external/v8/src/x64/ |
| D | macro-assembler-x64.cc | 5237 Register reg7, in AreAliased() argument
5241 reg7.is_valid() + reg8.is_valid(); in AreAliased()
5250 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-x64.h | 69 Register reg7 = no_reg,
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| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 5705 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
5709 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased()
5719 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-mips.h | 104 Register reg6 = no_reg, Register reg7 = no_reg,
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| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.cc | 6423 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
6427 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased()
6437 if (reg7.is_valid()) regs |= reg7.bit(); in AreAliased()
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| D | macro-assembler-mips64.h | 110 Register reg6 = no_reg, Register reg7 = no_reg,
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