| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct16x16_msa.c | 15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
21 LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
25 TRANSPOSE8x8_SH_SH(reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15, in vpx_idct16_1d_rows_msa()
26 reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
31 DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8); in vpx_idct16_1d_rows_msa()
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
35 reg8); in vpx_idct16_1d_rows_msa()
80 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vpx_idct16_1d_rows_msa()
86 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vpx_idct16_1d_rows_msa()
96 TRANSPOSE8x8_SH_SH(reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14, in vpx_idct16_1d_rows_msa()
[all …]
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| /external/llvm/test/DebugInfo/ |
| D | dwarfdump-debug-frame-simple.test | 10 ; FRAMES-NEXT: DW_CFA_offset: reg8 -4
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| /external/elfutils/tests/ |
| D | run-addrcfi.sh | 31 return address in reg8
41 integer reg8 (%eip): location expression: call_frame_cfa plus_uconst(-4)
78 return address in reg8
88 integer reg8 (%eip): location expression: call_frame_cfa plus_uconst(-4)
140 integer reg8 (%r8): undefined
206 integer reg8 (%r8): undefined
310 integer reg8 (r8): undefined
1332 integer reg8 (r8): undefined
2360 integer reg8 (r8): undefined
3386 integer reg8 (%r8): same_value
[all …]
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | big_alu.ll | 6 …eg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg …
14 %6 = extractelement <4 x float> %reg8, i32 0
19 %11 = extractelement <4 x float> %reg8, i32 0
24 %16 = extractelement <4 x float> %reg8, i32 0
29 %21 = extractelement <4 x float> %reg8, i32 0
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| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 212 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument
219 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
249 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument
258 match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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| D | assembler-arm64.h | 354 const CPURegister& reg8 = NoReg);
367 const CPURegister& reg8 = NoCPUReg);
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| /external/llvm/include/llvm/Support/ |
| D | Dwarf.def | 204 HANDLE_DW_OP(0x58, reg8)
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| /external/v8/src/x87/ |
| D | macro-assembler-x87.cc | 2702 Register reg8) { in AreAliased() argument
2705 reg7.is_valid() + reg8.is_valid(); in AreAliased()
2715 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-x87.h | 50 Register reg8 = no_reg);
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| /external/v8/src/ia32/ |
| D | macro-assembler-ia32.cc | 2830 Register reg8) { in AreAliased() argument
2833 reg7.is_valid() + reg8.is_valid(); in AreAliased()
2843 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-ia32.h | 50 Register reg8 = no_reg);
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| /external/v8/src/arm/ |
| D | macro-assembler-arm.cc | 3538 Register reg8) { in AreAliased() argument
3541 reg7.is_valid() + reg8.is_valid(); in AreAliased()
3551 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-arm.h | 79 Register reg8 = no_reg);
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| /external/elfutils/libdw/ |
| D | known-dwarf.h | 528 DWARF_ONE_KNOWN_DW_OP (reg8, DW_OP_reg8) \
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| /external/v8/src/ppc/ |
| D | macro-assembler-ppc.cc | 4241 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
4245 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased()
4256 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-ppc.h | 69 Register reg8 = no_reg, Register reg9 = no_reg,
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.cc | 5403 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased() argument
5410 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
5438 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType() argument
5447 match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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| D | assembler-a64.h | 417 const CPURegister& reg8 = NoReg);
431 const CPURegister& reg8 = NoCPUReg);
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| /external/v8/src/x64/ |
| D | macro-assembler-x64.cc | 5238 Register reg8) { in AreAliased() argument
5241 reg7.is_valid() + reg8.is_valid(); in AreAliased()
5251 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-x64.h | 70 Register reg8 = no_reg);
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| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 5705 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
5709 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased()
5720 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-mips.h | 105 Register reg8 = no_reg, Register reg9 = no_reg,
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| /external/v8/src/mips64/ |
| D | macro-assembler-mips64.cc | 6423 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
6427 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + in AreAliased()
6438 if (reg8.is_valid()) regs |= reg8.bit(); in AreAliased()
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| D | macro-assembler-mips64.h | 111 Register reg8 = no_reg, Register reg9 = no_reg,
|