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/external/valgrind/none/tests/arm/
Dv6media.stdout.exp2 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[…
3 mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[…
4 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[…
5 mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[…
6 mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[…
7 mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[…
9 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x…
10 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x…
11 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x…
12 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x…
[all …]
Dv6intARM.stdout.exp25 adds r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
26 adds r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x00000000
27 adds r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000
28 adds r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000
29 adds r0, r1, r2 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x80000000 N
30 adds r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0xffffffff, carryin 0, cpsr 0x60000000 ZC
31 adds r0, r1, r2 :: rd 0x80000000 rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x90000000 N V
32 adds r0, r1, r2 :: rd 0x7fffffff rm 0x80000000, rn 0xffffffff, carryin 0, cpsr 0x30000000 CV
33 adds r0, r1, r2 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, carryin 0, cpsr 0x80000000 N
35 adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000 Z
[all …]
Dv6intThumb.stdout.exp2 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
3 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
4 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
5 cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
6 cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
7 cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
8 cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
9 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
10 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
11 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
[all …]
/external/valgrind/none/tests/arm64/
Dinteger.stdout.exp2 add x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000…
3 add w3, w4, w5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000…
4 adc x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000…
5 adc x3, x4, x5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 2000000…
6 adc x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 0000000…
7 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 2000000…
8 adc x3, x4, x5 :: rd 5859704f00000000 rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 0000000…
9 adc x3, x4, x5 :: rd 5859704f00000001 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 2000000…
10 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 0000000…
11 adc x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 2000000…
[all …]
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc1297 unsigned rn = instr->Rn(); in VisitLoadStoreExclusive() local
1309 uint64_t address = reg<uint64_t>(rn, Reg31IsStackPointer); in VisitLoadStoreExclusive()
1320 if ((rn == 31) && (AlignDown(address, 16) != address)) { in VisitLoadStoreExclusive()
1653 int32_t rn = wreg(instr->Rn()); in VisitDataProcessing2Source() local
1655 if ((rn == kWMinInt) && (rm == -1)) { in VisitDataProcessing2Source()
1661 result = rn / rm; in VisitDataProcessing2Source()
1666 int64_t rn = xreg(instr->Rn()); in VisitDataProcessing2Source() local
1668 if ((rn == kXMinInt) && (rm == -1)) { in VisitDataProcessing2Source()
1674 result = rn / rm; in VisitDataProcessing2Source()
1679 uint32_t rn = static_cast<uint32_t>(wreg(instr->Rn())); in VisitDataProcessing2Source() local
[all …]
Dmacro-assembler-a64.h607 const Register& rn,
610 const Register& rn,
613 const Register& rn,
616 const Register& rn,
619 const Register& rn,
622 const Register& rn,
625 const Register& rn,
628 const Register& rn,
630 void Tst(const Register& rn, const Operand& operand);
632 const Register& rn,
[all …]
Dmacro-assembler-a64.cc634 const Register& rn, in And() argument
637 LogicalMacro(rd, rn, operand, AND); in And()
642 const Register& rn, in Ands() argument
645 LogicalMacro(rd, rn, operand, ANDS); in Ands()
649 void MacroAssembler::Tst(const Register& rn, in Tst() argument
652 Ands(AppropriateZeroRegFor(rn), rn, operand); in Tst()
657 const Register& rn, in Bic() argument
660 LogicalMacro(rd, rn, operand, BIC); in Bic()
665 const Register& rn, in Bics() argument
668 LogicalMacro(rd, rn, operand, BICS); in Bics()
[all …]
Dassembler-a64.cc895 const Register& rn, in add() argument
897 AddSub(rd, rn, operand, LeaveFlags, ADD); in add()
902 const Register& rn, in adds() argument
904 AddSub(rd, rn, operand, SetFlags, ADD); in adds()
908 void Assembler::cmn(const Register& rn, in cmn() argument
910 Register zr = AppropriateZeroRegFor(rn); in cmn()
911 adds(zr, rn, operand); in cmn()
916 const Register& rn, in sub() argument
918 AddSub(rd, rn, operand, LeaveFlags, SUB); in sub()
923 const Register& rn, in subs() argument
[all …]
Dassembler-a64.h1312 const Register& rn,
1317 const Register& rn,
1321 void cmn(const Register& rn, const Operand& operand);
1325 const Register& rn,
1330 const Register& rn,
1334 void cmp(const Register& rn, const Operand& operand);
1346 const Register& rn,
1351 const Register& rn,
1356 const Register& rn,
1361 const Register& rn,
[all …]
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h47 const Register& rn, in And() argument
51 LogicalMacro(rd, rn, operand, AND); in And()
56 const Register& rn, in Ands() argument
60 LogicalMacro(rd, rn, operand, ANDS); in Ands()
64 void MacroAssembler::Tst(const Register& rn, in Tst() argument
67 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS); in Tst()
72 const Register& rn, in Bic() argument
76 LogicalMacro(rd, rn, operand, BIC); in Bic()
81 const Register& rn, in Bics() argument
85 LogicalMacro(rd, rn, operand, BICS); in Bics()
[all …]
Dassembler-arm64.cc1092 const Register& rn, in add() argument
1094 AddSub(rd, rn, operand, LeaveFlags, ADD); in add()
1099 const Register& rn, in adds() argument
1101 AddSub(rd, rn, operand, SetFlags, ADD); in adds()
1105 void Assembler::cmn(const Register& rn, in cmn() argument
1107 Register zr = AppropriateZeroRegFor(rn); in cmn()
1108 adds(zr, rn, operand); in cmn()
1113 const Register& rn, in sub() argument
1115 AddSub(rd, rn, operand, LeaveFlags, SUB); in sub()
1120 const Register& rn, in subs() argument
[all …]
Dassembler-arm64.h1012 const Register& rn,
1017 const Register& rn,
1021 void cmn(const Register& rn, const Operand& operand);
1025 const Register& rn,
1030 const Register& rn,
1034 void cmp(const Register& rn, const Operand& operand);
1046 const Register& rn,
1051 const Register& rn,
1056 const Register& rn,
1061 const Register& rn,
[all …]
Dmacro-assembler-arm64.h157 const Register& rn,
160 const Register& rn,
163 const Register& rn,
166 const Register& rn,
169 const Register& rn,
172 const Register& rn,
175 const Register& rn,
178 const Register& rn,
180 inline void Tst(const Register& rn, const Operand& operand);
182 const Register& rn,
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dconvert-fp.ll49 ; CHECK: cvt.rn.f32.u16 %f{{[0-9]+}}, %rs{{[0-9]+}};
56 ; CHECK: cvt.rn.f32.u32 %f{{[0-9]+}}, %r{{[0-9]+}};
63 ; CHECK: cvt.rn.f32.u64 %f{{[0-9]+}}, %rd{{[0-9]+}};
70 ; CHECK: cvt.rn.f32.f64 %f{{[0-9]+}}, %fd{{[0-9]+}};
77 ; CHECK: cvt.rn.f32.s16 %f{{[0-9]+}}, %rs{{[0-9]+}}
84 ; CHECK: cvt.rn.f32.s32 %f{{[0-9]+}}, %r{{[0-9]+}}
91 ; CHECK: cvt.rn.f32.s64 %f{{[0-9]+}}, %rd{{[0-9]+}}
98 ; CHECK: cvt.rn.f64.u16 %fd{{[0-9]+}}, %rs{{[0-9]+}};
105 ; CHECK: cvt.rn.f64.u32 %fd{{[0-9]+}}, %r{{[0-9]+}};
112 ; CHECK: cvt.rn.f64.u64 %fd{{[0-9]+}}, %rd{{[0-9]+}};
[all …]
Dfp-contract.ll7 ;; If fusion is allowed, we try to form fma.rn at the PTX level, and emit
10 ;; we do not form fma.rn at the PTX level and explicitly generate add.rn
16 ;; FAST: fma.rn.f32
17 ;; DEFAULT: mul.rn.f32
18 ;; DEFAULT: add.rn.f32
27 ;; We cannot form an fma here, but make sure we explicitly emit add.rn.f32
30 ;; DEFAULT: add.rn.f32
Dfma-disable.ll8 ; FMA: fma.rn.f32
9 ; MUL: mul.rn.f32
10 ; MUL: add.rn.f32
18 ; FMA: fma.rn.f64
19 ; MUL: mul.rn.f64
20 ; MUL: add.rn.f64
Dfma.ll7 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
15 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
16 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
26 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
34 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
35 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
Dfma-assoc.ll5 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
6 ; CHECK: fma.rn.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}};
17 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
18 ; CHECK: fma.rn.f64 %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}}, %fd{{[0-9]+}};
31 ; CHECK: fma.rn.f64
Di1-int-to-fp.ll6 ; CHECK: cvt.rn.f32.u32
15 ; CHECK: cvt.rn.f32.s32
24 ; CHECK: cvt.rn.f64.u32
33 ; CHECK: cvt.rn.f64.s32
/external/libvorbis/lib/
Dwindow.c2113 long rn=blocksizes[nW]; in _vorbis_apply_window() local
2118 long rightbegin=n/2+n/4-rn/4; in _vorbis_apply_window()
2119 long rightend=rightbegin+rn/2; in _vorbis_apply_window()
2129 for(i=rightbegin,p=rn/2-1;i<rightend;i++,p--) in _vorbis_apply_window()
/external/jemalloc/test/include/test/
Dmath.h56 double acu, factor, oflo, gin, term, rn, a, b, an, dif; in i_gamma() local
75 rn = p; in i_gamma()
78 rn += 1.0; in i_gamma()
79 term *= x / rn; in i_gamma()
105 rn = pn[4] / pn[5]; in i_gamma()
106 dif = fabs(gin - rn); in i_gamma()
107 if (dif <= acu && dif <= acu * rn) { in i_gamma()
111 gin = rn; in i_gamma()
/external/ipsec-tools/src/racoon/samples/roadwarrior/client/
Dphase1-down.sh11 DEFAULT_GW=`netstat -rn | awk '($1 == "default"){print $2}'`
14 DEFAULT_GW=`netstat -rn | awk '($1 == "0.0.0.0"){print $2}'`
34 if=`netstat -rn|awk '($1 == "default"){print $7}'`
41 if=`netstat -rn|awk '($1 == "0.0.0.0"){print $8}'`
Dphase1-up.sh10 DEFAULT_GW=`netstat -rn | awk '($1 == "default"){print $2}'`
13 DEFAULT_GW=`netstat -rn | awk '($1 == "0.0.0.0"){print $2}'`
35 if=`netstat -rn|awk '($1 == "default"){print $7}'`
42 if=`netstat -rn|awk '($1 == "0.0.0.0"){print $8}'`
/external/vixl/doc/
Dsupported-instructions.md17 const Register& rn,
26 const Register& rn,
35 const Register& rn,
44 const Register& rn,
81 const Register& rn,
90 const Register& rn,
98 void asr(const Register& rd, const Register& rn, unsigned shift)
105 void asrv(const Register& rd, const Register& rn, const Register& rm)
141 const Register& rn,
151 const Register& rn,
[all …]
/external/ltrace/sysdeps/linux-gnu/arm/
Dtrace.c336 enum arm_register rn = BITS(this_instr, 16, 19); in arm_get_next_pcs() local
338 if (arm_get_register(proc, rn, &rn_val) < 0) in arm_get_next_pcs()
491 const enum arm_register rn = BITS(inst1, 0, 3); in thumb_get_next_pcs() local
515 if (arm_get_register(proc, rn, &addr) < 0) in thumb_get_next_pcs()
527 const enum arm_register rn = BITS(inst2, 0, 3); in thumb_get_next_pcs() local
529 if (arm_get_register(proc, rn, &next) < 0) in thumb_get_next_pcs()
536 const enum arm_register rn = BITS(inst1, 0, 3); in thumb_get_next_pcs() local
538 if (arm_get_register(proc, rn, &base) < 0) in thumb_get_next_pcs()
542 if (rn == ARM_REG_PC) { in thumb_get_next_pcs()

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