| /external/vulkan-validation-layers/libs/glm/detail/ |
| D | intrinsic_integer.inl | 40 __m128i Reg1; local
94 __m128i Reg1; local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 791 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg()
811 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg()
822 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair()
|
| D | MipsSEFrameLowering.cpp | 442 unsigned Reg1 = in emitPrologue() local
459 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
|
| D | Mips16InstrInfo.cpp | 265 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 116 unsigned Reg1, bool isKill1, in addRegReg()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 488 unsigned Reg1 = Reg; in lowerCRSpilling() local
533 unsigned Reg1 = Reg; in lowerCRRestore() local
577 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
|
| D | PPCVSXSwapRemoval.cpp | 837 unsigned Reg1 = MI->getOperand(1).getReg(); in handleSpecialSwappables() local
|
| D | PPCInstrInfo.cpp | 349 unsigned Reg1 = MI->getOperand(1).getReg(); in commuteInstructionImpl() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 738 unsigned Reg1 = CSI[idx].getReg(); in spillCalleeSavedRegisters() local
815 unsigned Reg1 = CSI[i].getReg(); in restoreCalleeSavedRegisters() local
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
600 uint16_t Reg1; variable
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 227 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in SelectInlineAsm() local
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 1460 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwo() local
1473 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpaced() local
1528 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); in printVectorListTwoAllLanes() local
1575 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); in printVectorListTwoSpacedAllLanes() local
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 371 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
|
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1617 StringRef Reg1(R1); in processInstruction() local
1632 StringRef Reg1(R1); in processInstruction() local
1648 StringRef Reg1(R1); in processInstruction() local
1969 StringRef Reg1(R1); in processInstruction() local
2119 StringRef Reg1(R1); in processInstruction() local
|
| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 469 unsigned Reg1, unsigned Reg2) { in createRegSequence()
|
| D | Thumb2SizeReduction.cpp | 659 unsigned Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
|
| D | ARMBaseInstrInfo.cpp | 1262 const unsigned &Reg2) -> bool { in expandMEMCPY()
2736 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); in FoldImmediate() local
|
| D | ARMFastISel.cpp | 2779 unsigned Reg1 = getRegForValue(Src1Value); in SelectShift() local
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 100 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
|
| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) in UnionGroups()
|
| D | TargetInstrInfo.cpp | 140 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstructionImpl() local
|
| D | RegisterCoalescer.cpp | 1897 unsigned Reg1; in valuesIdentical() local
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1453 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, in emitRR()
1477 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, in emitRRX()
1488 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, in emitRRR()
1494 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, in emitRRI()
|
| /external/llvm/lib/MC/ |
| D | MCDwarf.cpp | 1034 unsigned Reg1 = Instr.getRegister(); in EmitCFIInstruction() local
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1122 for (const auto &Reg1 : Registers) { in computeComposites() local
|