1/* 2 * This file was generated automatically by gen-mterp.py for 'mips64'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: mips64/header.S */ 8/* 9 * Copyright (C) 2016 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24#include <machine/regdef.h> 25 26/* TODO: add the missing file and use its FP register definitions. */ 27/* #include <machine/fpregdef.h> */ 28/* FP register definitions */ 29#define f0 $f0 30#define f1 $f1 31#define f2 $f2 32#define f3 $f3 33#define f12 $f12 34#define f13 $f13 35 36/* 37 * It looks like the GNU assembler currently does not support the blec and bgtc 38 * idioms, which should translate into bgec and bltc respectively with swapped 39 * left and right register operands. 40 * TODO: remove these macros when the assembler is fixed. 41 */ 42.macro blec lreg, rreg, target 43 bgec \rreg, \lreg, \target 44.endm 45.macro bgtc lreg, rreg, target 46 bltc \rreg, \lreg, \target 47.endm 48 49/* 50Mterp and MIPS64 notes: 51 52The following registers have fixed assignments: 53 54 reg nick purpose 55 s0 rPC interpreted program counter, used for fetching instructions 56 s1 rFP interpreted frame pointer, used for accessing locals and args 57 s2 rSELF self (Thread) pointer 58 s3 rINST first 16-bit code unit of current instruction 59 s4 rIBASE interpreted instruction base pointer, used for computed goto 60 s5 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). 61*/ 62 63/* During bringup, we'll use the shadow frame model instead of rFP */ 64/* single-purpose registers, given names for clarity */ 65#define rPC s0 66#define rFP s1 67#define rSELF s2 68#define rINST s3 69#define rIBASE s4 70#define rREFS s5 71 72/* 73 * This is a #include, not a %include, because we want the C pre-processor 74 * to expand the macros into assembler assignment statements. 75 */ 76#include "asm_support.h" 77 78/* 79 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, 80 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 81 */ 82#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 83#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 84#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 85#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 86#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 87#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 88#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 89#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET) 90#define OFF_FP_SHADOWFRAME (-SHADOWFRAME_VREGS_OFFSET) 91 92#define MTERP_PROFILE_BRANCHES 1 93#define MTERP_LOGGING 0 94 95/* 96 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 97 * be done *before* something throws. 98 * 99 * It's okay to do this more than once. 100 * 101 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 102 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 103 * offset into the code_items_[] array. For effiency, we will "export" the 104 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 105 * to convert to a dex pc when needed. 106 */ 107.macro EXPORT_PC 108 sd rPC, OFF_FP_DEX_PC_PTR(rFP) 109.endm 110 111/* 112 * Refresh handler table. 113 */ 114.macro REFRESH_IBASE 115 ld rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) 116.endm 117 118/* 119 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 120 */ 121.macro FETCH_INST 122 lhu rINST, 0(rPC) 123.endm 124 125/* Advance rPC by some number of code units. */ 126.macro ADVANCE count 127 daddu rPC, rPC, (\count) * 2 128.endm 129 130/* 131 * Fetch the next instruction from the specified offset. Advances rPC 132 * to point to the next instruction. 133 * 134 * This must come AFTER anything that can throw an exception, or the 135 * exception catch may miss. (This also implies that it must come after 136 * EXPORT_PC.) 137 */ 138.macro FETCH_ADVANCE_INST count 139 ADVANCE \count 140 FETCH_INST 141.endm 142 143/* 144 * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load 145 * rINST ahead of possible exception point. Be sure to manually advance rPC 146 * later. 147 */ 148.macro PREFETCH_INST count 149 lhu rINST, ((\count) * 2)(rPC) 150.endm 151 152/* 153 * Put the instruction's opcode field into the specified register. 154 */ 155.macro GET_INST_OPCODE reg 156 and \reg, rINST, 255 157.endm 158 159/* 160 * Begin executing the opcode in _reg. 161 */ 162.macro GOTO_OPCODE reg 163 .set noat 164 sll AT, \reg, 7 165 daddu AT, rIBASE, AT 166 jic AT, 0 167 .set at 168.endm 169 170/* 171 * Get/set the 32-bit value from a Dalvik register. 172 * Note, GET_VREG does sign extension to 64 bits while 173 * GET_VREG_U does zero extension to 64 bits. 174 * One is useful for arithmetic while the other is 175 * useful for storing the result value as 64-bit. 176 */ 177.macro GET_VREG reg, vreg 178 .set noat 179 dlsa AT, \vreg, rFP, 2 180 lw \reg, 0(AT) 181 .set at 182.endm 183.macro GET_VREG_U reg, vreg 184 .set noat 185 dlsa AT, \vreg, rFP, 2 186 lwu \reg, 0(AT) 187 .set at 188.endm 189.macro GET_VREG_FLOAT reg, vreg 190 .set noat 191 dlsa AT, \vreg, rFP, 2 192 lwc1 \reg, 0(AT) 193 .set at 194.endm 195.macro SET_VREG reg, vreg 196 .set noat 197 dlsa AT, \vreg, rFP, 2 198 sw \reg, 0(AT) 199 dlsa AT, \vreg, rREFS, 2 200 sw zero, 0(AT) 201 .set at 202.endm 203.macro SET_VREG_OBJECT reg, vreg 204 .set noat 205 dlsa AT, \vreg, rFP, 2 206 sw \reg, 0(AT) 207 dlsa AT, \vreg, rREFS, 2 208 sw \reg, 0(AT) 209 .set at 210.endm 211.macro SET_VREG_FLOAT reg, vreg 212 .set noat 213 dlsa AT, \vreg, rFP, 2 214 swc1 \reg, 0(AT) 215 dlsa AT, \vreg, rREFS, 2 216 sw zero, 0(AT) 217 .set at 218.endm 219 220/* 221 * Get/set the 64-bit value from a Dalvik register. 222 * Avoid unaligned memory accesses. 223 * Note, SET_VREG_WIDE clobbers the register containing the value being stored. 224 * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number. 225 */ 226.macro GET_VREG_WIDE reg, vreg 227 .set noat 228 dlsa AT, \vreg, rFP, 2 229 lw \reg, 0(AT) 230 lw AT, 4(AT) 231 dinsu \reg, AT, 32, 32 232 .set at 233.endm 234.macro GET_VREG_DOUBLE reg, vreg 235 .set noat 236 dlsa AT, \vreg, rFP, 2 237 lwc1 \reg, 0(AT) 238 lw AT, 4(AT) 239 mthc1 AT, \reg 240 .set at 241.endm 242.macro SET_VREG_WIDE reg, vreg 243 .set noat 244 dlsa AT, \vreg, rFP, 2 245 sw \reg, 0(AT) 246 drotr32 \reg, \reg, 0 247 sw \reg, 4(AT) 248 dlsa AT, \vreg, rREFS, 2 249 sw zero, 0(AT) 250 sw zero, 4(AT) 251 .set at 252.endm 253.macro SET_VREG_DOUBLE reg, vreg 254 .set noat 255 dlsa AT, \vreg, rREFS, 2 256 sw zero, 0(AT) 257 sw zero, 4(AT) 258 dlsa AT, \vreg, rFP, 2 259 swc1 \reg, 0(AT) 260 mfhc1 \vreg, \reg 261 sw \vreg, 4(AT) 262 .set at 263.endm 264 265/* 266 * On-stack offsets for spilling/unspilling callee-saved registers 267 * and the frame size. 268 */ 269#define STACK_OFFSET_RA 0 270#define STACK_OFFSET_GP 8 271#define STACK_OFFSET_S0 16 272#define STACK_OFFSET_S1 24 273#define STACK_OFFSET_S2 32 274#define STACK_OFFSET_S3 40 275#define STACK_OFFSET_S4 48 276#define STACK_OFFSET_S5 56 277#define STACK_SIZE 64 278 279/* Constants for float/double_to_int/long conversions */ 280#define INT_MIN 0x80000000 281#define INT_MIN_AS_FLOAT 0xCF000000 282#define INT_MIN_AS_DOUBLE 0xC1E0000000000000 283#define LONG_MIN 0x8000000000000000 284#define LONG_MIN_AS_FLOAT 0xDF000000 285#define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 286 287/* File: mips64/entry.S */ 288/* 289 * Copyright (C) 2016 The Android Open Source Project 290 * 291 * Licensed under the Apache License, Version 2.0 (the "License"); 292 * you may not use this file except in compliance with the License. 293 * You may obtain a copy of the License at 294 * 295 * http://www.apache.org/licenses/LICENSE-2.0 296 * 297 * Unless required by applicable law or agreed to in writing, software 298 * distributed under the License is distributed on an "AS IS" BASIS, 299 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 300 * See the License for the specific language governing permissions and 301 * limitations under the License. 302 */ 303 304/* 305 * Interpreter entry point. 306 */ 307 308 .set reorder 309 310 .text 311 .global ExecuteMterpImpl 312 .type ExecuteMterpImpl, %function 313 .balign 16 314/* 315 * On entry: 316 * a0 Thread* self 317 * a1 code_item 318 * a2 ShadowFrame 319 * a3 JValue* result_register 320 * 321 */ 322ExecuteMterpImpl: 323 .cfi_startproc 324 .cpsetup t9, t8, ExecuteMterpImpl 325 326 .cfi_def_cfa sp, 0 327 daddu sp, sp, -STACK_SIZE 328 .cfi_adjust_cfa_offset STACK_SIZE 329 330 sd t8, STACK_OFFSET_GP(sp) 331 .cfi_rel_offset 28, STACK_OFFSET_GP 332 sd ra, STACK_OFFSET_RA(sp) 333 .cfi_rel_offset 31, STACK_OFFSET_RA 334 335 sd s0, STACK_OFFSET_S0(sp) 336 .cfi_rel_offset 16, STACK_OFFSET_S0 337 sd s1, STACK_OFFSET_S1(sp) 338 .cfi_rel_offset 17, STACK_OFFSET_S1 339 sd s2, STACK_OFFSET_S2(sp) 340 .cfi_rel_offset 18, STACK_OFFSET_S2 341 sd s3, STACK_OFFSET_S3(sp) 342 .cfi_rel_offset 19, STACK_OFFSET_S3 343 sd s4, STACK_OFFSET_S4(sp) 344 .cfi_rel_offset 20, STACK_OFFSET_S4 345 sd s5, STACK_OFFSET_S5(sp) 346 .cfi_rel_offset 21, STACK_OFFSET_S5 347 348 /* Remember the return register */ 349 sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) 350 351 /* Remember the code_item */ 352 sd a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2) 353 354 /* set up "named" registers */ 355 move rSELF, a0 356 daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET 357 lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) 358 dlsa rREFS, v0, rFP, 2 359 daddu rPC, a1, CODEITEM_INSNS_OFFSET 360 lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2) 361 dlsa rPC, v0, rPC, 1 362 EXPORT_PC 363 364 /* Starting ibase */ 365 REFRESH_IBASE 366 367 /* start executing the instruction at rPC */ 368 FETCH_INST 369 GET_INST_OPCODE v0 370 GOTO_OPCODE v0 371 372 /* NOTE: no fallthrough */ 373 374 375 .global artMterpAsmInstructionStart 376 .type artMterpAsmInstructionStart, %function 377artMterpAsmInstructionStart = .L_op_nop 378 .text 379 380/* ------------------------------ */ 381 .balign 128 382.L_op_nop: /* 0x00 */ 383/* File: mips64/op_nop.S */ 384 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 385 GET_INST_OPCODE v0 # extract opcode from rINST 386 GOTO_OPCODE v0 # jump to next instruction 387 388/* ------------------------------ */ 389 .balign 128 390.L_op_move: /* 0x01 */ 391/* File: mips64/op_move.S */ 392 /* for move, move-object, long-to-int */ 393 /* op vA, vB */ 394 ext a2, rINST, 8, 4 # a2 <- A 395 ext a3, rINST, 12, 4 # a3 <- B 396 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 397 GET_VREG a0, a3 # a0 <- vB 398 GET_INST_OPCODE v0 # extract opcode from rINST 399 .if 0 400 SET_VREG_OBJECT a0, a2 # vA <- vB 401 .else 402 SET_VREG a0, a2 # vA <- vB 403 .endif 404 GOTO_OPCODE v0 # jump to next instruction 405 406/* ------------------------------ */ 407 .balign 128 408.L_op_move_from16: /* 0x02 */ 409/* File: mips64/op_move_from16.S */ 410 /* for: move/from16, move-object/from16 */ 411 /* op vAA, vBBBB */ 412 lhu a3, 2(rPC) # a3 <- BBBB 413 srl a2, rINST, 8 # a2 <- AA 414 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 415 GET_VREG a0, a3 # a0 <- vBBBB 416 GET_INST_OPCODE v0 # extract opcode from rINST 417 .if 0 418 SET_VREG_OBJECT a0, a2 # vAA <- vBBBB 419 .else 420 SET_VREG a0, a2 # vAA <- vBBBB 421 .endif 422 GOTO_OPCODE v0 # jump to next instruction 423 424/* ------------------------------ */ 425 .balign 128 426.L_op_move_16: /* 0x03 */ 427/* File: mips64/op_move_16.S */ 428 /* for: move/16, move-object/16 */ 429 /* op vAAAA, vBBBB */ 430 lhu a3, 4(rPC) # a3 <- BBBB 431 lhu a2, 2(rPC) # a2 <- AAAA 432 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 433 GET_VREG a0, a3 # a0 <- vBBBB 434 GET_INST_OPCODE v0 # extract opcode from rINST 435 .if 0 436 SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB 437 .else 438 SET_VREG a0, a2 # vAAAA <- vBBBB 439 .endif 440 GOTO_OPCODE v0 # jump to next instruction 441 442/* ------------------------------ */ 443 .balign 128 444.L_op_move_wide: /* 0x04 */ 445/* File: mips64/op_move_wide.S */ 446 /* move-wide vA, vB */ 447 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 448 ext a3, rINST, 12, 4 # a3 <- B 449 ext a2, rINST, 8, 4 # a2 <- A 450 GET_VREG_WIDE a0, a3 # a0 <- vB 451 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 452 GET_INST_OPCODE v0 # extract opcode from rINST 453 SET_VREG_WIDE a0, a2 # vA <- vB 454 GOTO_OPCODE v0 # jump to next instruction 455 456/* ------------------------------ */ 457 .balign 128 458.L_op_move_wide_from16: /* 0x05 */ 459/* File: mips64/op_move_wide_from16.S */ 460 /* move-wide/from16 vAA, vBBBB */ 461 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 462 lhu a3, 2(rPC) # a3 <- BBBB 463 srl a2, rINST, 8 # a2 <- AA 464 GET_VREG_WIDE a0, a3 # a0 <- vBBBB 465 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 466 GET_INST_OPCODE v0 # extract opcode from rINST 467 SET_VREG_WIDE a0, a2 # vAA <- vBBBB 468 GOTO_OPCODE v0 # jump to next instruction 469 470/* ------------------------------ */ 471 .balign 128 472.L_op_move_wide_16: /* 0x06 */ 473/* File: mips64/op_move_wide_16.S */ 474 /* move-wide/16 vAAAA, vBBBB */ 475 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 476 lhu a3, 4(rPC) # a3 <- BBBB 477 lhu a2, 2(rPC) # a2 <- AAAA 478 GET_VREG_WIDE a0, a3 # a0 <- vBBBB 479 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 480 GET_INST_OPCODE v0 # extract opcode from rINST 481 SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB 482 GOTO_OPCODE v0 # jump to next instruction 483 484/* ------------------------------ */ 485 .balign 128 486.L_op_move_object: /* 0x07 */ 487/* File: mips64/op_move_object.S */ 488/* File: mips64/op_move.S */ 489 /* for move, move-object, long-to-int */ 490 /* op vA, vB */ 491 ext a2, rINST, 8, 4 # a2 <- A 492 ext a3, rINST, 12, 4 # a3 <- B 493 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 494 GET_VREG a0, a3 # a0 <- vB 495 GET_INST_OPCODE v0 # extract opcode from rINST 496 .if 1 497 SET_VREG_OBJECT a0, a2 # vA <- vB 498 .else 499 SET_VREG a0, a2 # vA <- vB 500 .endif 501 GOTO_OPCODE v0 # jump to next instruction 502 503 504/* ------------------------------ */ 505 .balign 128 506.L_op_move_object_from16: /* 0x08 */ 507/* File: mips64/op_move_object_from16.S */ 508/* File: mips64/op_move_from16.S */ 509 /* for: move/from16, move-object/from16 */ 510 /* op vAA, vBBBB */ 511 lhu a3, 2(rPC) # a3 <- BBBB 512 srl a2, rINST, 8 # a2 <- AA 513 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 514 GET_VREG a0, a3 # a0 <- vBBBB 515 GET_INST_OPCODE v0 # extract opcode from rINST 516 .if 1 517 SET_VREG_OBJECT a0, a2 # vAA <- vBBBB 518 .else 519 SET_VREG a0, a2 # vAA <- vBBBB 520 .endif 521 GOTO_OPCODE v0 # jump to next instruction 522 523 524/* ------------------------------ */ 525 .balign 128 526.L_op_move_object_16: /* 0x09 */ 527/* File: mips64/op_move_object_16.S */ 528/* File: mips64/op_move_16.S */ 529 /* for: move/16, move-object/16 */ 530 /* op vAAAA, vBBBB */ 531 lhu a3, 4(rPC) # a3 <- BBBB 532 lhu a2, 2(rPC) # a2 <- AAAA 533 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 534 GET_VREG a0, a3 # a0 <- vBBBB 535 GET_INST_OPCODE v0 # extract opcode from rINST 536 .if 1 537 SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB 538 .else 539 SET_VREG a0, a2 # vAAAA <- vBBBB 540 .endif 541 GOTO_OPCODE v0 # jump to next instruction 542 543 544/* ------------------------------ */ 545 .balign 128 546.L_op_move_result: /* 0x0a */ 547/* File: mips64/op_move_result.S */ 548 /* for: move-result, move-result-object */ 549 /* op vAA */ 550 srl a2, rINST, 8 # a2 <- AA 551 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 552 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 553 lw a0, 0(a0) # a0 <- result.i 554 GET_INST_OPCODE v0 # extract opcode from rINST 555 .if 0 556 SET_VREG_OBJECT a0, a2 # vAA <- result 557 .else 558 SET_VREG a0, a2 # vAA <- result 559 .endif 560 GOTO_OPCODE v0 # jump to next instruction 561 562/* ------------------------------ */ 563 .balign 128 564.L_op_move_result_wide: /* 0x0b */ 565/* File: mips64/op_move_result_wide.S */ 566 /* for: move-result-wide */ 567 /* op vAA */ 568 srl a2, rINST, 8 # a2 <- AA 569 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 570 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 571 ld a0, 0(a0) # a0 <- result.j 572 GET_INST_OPCODE v0 # extract opcode from rINST 573 SET_VREG_WIDE a0, a2 # vAA <- result 574 GOTO_OPCODE v0 # jump to next instruction 575 576/* ------------------------------ */ 577 .balign 128 578.L_op_move_result_object: /* 0x0c */ 579/* File: mips64/op_move_result_object.S */ 580/* File: mips64/op_move_result.S */ 581 /* for: move-result, move-result-object */ 582 /* op vAA */ 583 srl a2, rINST, 8 # a2 <- AA 584 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 585 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 586 lw a0, 0(a0) # a0 <- result.i 587 GET_INST_OPCODE v0 # extract opcode from rINST 588 .if 1 589 SET_VREG_OBJECT a0, a2 # vAA <- result 590 .else 591 SET_VREG a0, a2 # vAA <- result 592 .endif 593 GOTO_OPCODE v0 # jump to next instruction 594 595 596/* ------------------------------ */ 597 .balign 128 598.L_op_move_exception: /* 0x0d */ 599/* File: mips64/op_move_exception.S */ 600 /* move-exception vAA */ 601 srl a2, rINST, 8 # a2 <- AA 602 ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj 603 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 604 SET_VREG_OBJECT a0, a2 # vAA <- exception obj 605 GET_INST_OPCODE v0 # extract opcode from rINST 606 sd zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception 607 GOTO_OPCODE v0 # jump to next instruction 608 609/* ------------------------------ */ 610 .balign 128 611.L_op_return_void: /* 0x0e */ 612/* File: mips64/op_return_void.S */ 613 .extern MterpThreadFenceForConstructor 614 .extern MterpSuspendCheck 615 jal MterpThreadFenceForConstructor 616 lw ra, THREAD_FLAGS_OFFSET(rSELF) 617 move a0, rSELF 618 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 619 beqzc ra, 1f 620 jal MterpSuspendCheck # (self) 6211: 622 li a0, 0 623 b MterpReturn 624 625/* ------------------------------ */ 626 .balign 128 627.L_op_return: /* 0x0f */ 628/* File: mips64/op_return.S */ 629 /* 630 * Return a 32-bit value. 631 * 632 * for: return, return-object 633 */ 634 /* op vAA */ 635 .extern MterpThreadFenceForConstructor 636 .extern MterpSuspendCheck 637 jal MterpThreadFenceForConstructor 638 lw ra, THREAD_FLAGS_OFFSET(rSELF) 639 move a0, rSELF 640 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 641 beqzc ra, 1f 642 jal MterpSuspendCheck # (self) 6431: 644 srl a2, rINST, 8 # a2 <- AA 645 GET_VREG_U a0, a2 # a0 <- vAA 646 b MterpReturn 647 648/* ------------------------------ */ 649 .balign 128 650.L_op_return_wide: /* 0x10 */ 651/* File: mips64/op_return_wide.S */ 652 /* 653 * Return a 64-bit value. 654 */ 655 /* return-wide vAA */ 656 /* op vAA */ 657 .extern MterpThreadFenceForConstructor 658 .extern MterpSuspendCheck 659 jal MterpThreadFenceForConstructor 660 lw ra, THREAD_FLAGS_OFFSET(rSELF) 661 move a0, rSELF 662 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 663 beqzc ra, 1f 664 jal MterpSuspendCheck # (self) 6651: 666 srl a2, rINST, 8 # a2 <- AA 667 GET_VREG_WIDE a0, a2 # a0 <- vAA 668 b MterpReturn 669 670/* ------------------------------ */ 671 .balign 128 672.L_op_return_object: /* 0x11 */ 673/* File: mips64/op_return_object.S */ 674/* File: mips64/op_return.S */ 675 /* 676 * Return a 32-bit value. 677 * 678 * for: return, return-object 679 */ 680 /* op vAA */ 681 .extern MterpThreadFenceForConstructor 682 .extern MterpSuspendCheck 683 jal MterpThreadFenceForConstructor 684 lw ra, THREAD_FLAGS_OFFSET(rSELF) 685 move a0, rSELF 686 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 687 beqzc ra, 1f 688 jal MterpSuspendCheck # (self) 6891: 690 srl a2, rINST, 8 # a2 <- AA 691 GET_VREG_U a0, a2 # a0 <- vAA 692 b MterpReturn 693 694 695/* ------------------------------ */ 696 .balign 128 697.L_op_const_4: /* 0x12 */ 698/* File: mips64/op_const_4.S */ 699 /* const/4 vA, #+B */ 700 ext a2, rINST, 8, 4 # a2 <- A 701 seh a0, rINST # sign extend B in rINST 702 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 703 sra a0, a0, 12 # shift B into its final position 704 GET_INST_OPCODE v0 # extract opcode from rINST 705 SET_VREG a0, a2 # vA <- +B 706 GOTO_OPCODE v0 # jump to next instruction 707 708/* ------------------------------ */ 709 .balign 128 710.L_op_const_16: /* 0x13 */ 711/* File: mips64/op_const_16.S */ 712 /* const/16 vAA, #+BBBB */ 713 srl a2, rINST, 8 # a2 <- AA 714 lh a0, 2(rPC) # a0 <- sign-extended BBBB 715 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 716 GET_INST_OPCODE v0 # extract opcode from rINST 717 SET_VREG a0, a2 # vAA <- +BBBB 718 GOTO_OPCODE v0 # jump to next instruction 719 720/* ------------------------------ */ 721 .balign 128 722.L_op_const: /* 0x14 */ 723/* File: mips64/op_const.S */ 724 /* const vAA, #+BBBBbbbb */ 725 srl a2, rINST, 8 # a2 <- AA 726 lh a0, 2(rPC) # a0 <- bbbb (low) 727 lh a1, 4(rPC) # a1 <- BBBB (high) 728 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 729 ins a0, a1, 16, 16 # a0 = BBBBbbbb 730 GET_INST_OPCODE v0 # extract opcode from rINST 731 SET_VREG a0, a2 # vAA <- +BBBBbbbb 732 GOTO_OPCODE v0 # jump to next instruction 733 734/* ------------------------------ */ 735 .balign 128 736.L_op_const_high16: /* 0x15 */ 737/* File: mips64/op_const_high16.S */ 738 /* const/high16 vAA, #+BBBB0000 */ 739 srl a2, rINST, 8 # a2 <- AA 740 lh a0, 2(rPC) # a0 <- BBBB 741 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 742 sll a0, a0, 16 # a0 <- BBBB0000 743 GET_INST_OPCODE v0 # extract opcode from rINST 744 SET_VREG a0, a2 # vAA <- +BBBB0000 745 GOTO_OPCODE v0 # jump to next instruction 746 747/* ------------------------------ */ 748 .balign 128 749.L_op_const_wide_16: /* 0x16 */ 750/* File: mips64/op_const_wide_16.S */ 751 /* const-wide/16 vAA, #+BBBB */ 752 srl a2, rINST, 8 # a2 <- AA 753 lh a0, 2(rPC) # a0 <- sign-extended BBBB 754 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 755 GET_INST_OPCODE v0 # extract opcode from rINST 756 SET_VREG_WIDE a0, a2 # vAA <- +BBBB 757 GOTO_OPCODE v0 # jump to next instruction 758 759/* ------------------------------ */ 760 .balign 128 761.L_op_const_wide_32: /* 0x17 */ 762/* File: mips64/op_const_wide_32.S */ 763 /* const-wide/32 vAA, #+BBBBbbbb */ 764 srl a2, rINST, 8 # a2 <- AA 765 lh a0, 2(rPC) # a0 <- bbbb (low) 766 lh a1, 4(rPC) # a1 <- BBBB (high) 767 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 768 ins a0, a1, 16, 16 # a0 = BBBBbbbb 769 GET_INST_OPCODE v0 # extract opcode from rINST 770 SET_VREG_WIDE a0, a2 # vAA <- +BBBBbbbb 771 GOTO_OPCODE v0 # jump to next instruction 772 773/* ------------------------------ */ 774 .balign 128 775.L_op_const_wide: /* 0x18 */ 776/* File: mips64/op_const_wide.S */ 777 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 778 srl a4, rINST, 8 # a4 <- AA 779 lh a0, 2(rPC) # a0 <- bbbb (low) 780 lh a1, 4(rPC) # a1 <- BBBB (low middle) 781 lh a2, 6(rPC) # a2 <- hhhh (high middle) 782 lh a3, 8(rPC) # a3 <- HHHH (high) 783 FETCH_ADVANCE_INST 5 # advance rPC, load rINST 784 ins a0, a1, 16, 16 # a0 = BBBBbbbb 785 ins a2, a3, 16, 16 # a2 = HHHHhhhh 786 dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb 787 GET_INST_OPCODE v0 # extract opcode from rINST 788 SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb 789 GOTO_OPCODE v0 # jump to next instruction 790 791/* ------------------------------ */ 792 .balign 128 793.L_op_const_wide_high16: /* 0x19 */ 794/* File: mips64/op_const_wide_high16.S */ 795 /* const-wide/high16 vAA, #+BBBB000000000000 */ 796 srl a2, rINST, 8 # a2 <- AA 797 lh a0, 2(rPC) # a0 <- BBBB 798 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 799 dsll32 a0, a0, 16 # a0 <- BBBB000000000000 800 GET_INST_OPCODE v0 # extract opcode from rINST 801 SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000 802 GOTO_OPCODE v0 # jump to next instruction 803 804/* ------------------------------ */ 805 .balign 128 806.L_op_const_string: /* 0x1a */ 807/* File: mips64/op_const_string.S */ 808 /* const/string vAA, String//BBBB */ 809 .extern MterpConstString 810 EXPORT_PC 811 lhu a0, 2(rPC) # a0 <- BBBB 812 srl a1, rINST, 8 # a1 <- AA 813 daddu a2, rFP, OFF_FP_SHADOWFRAME 814 move a3, rSELF 815 jal MterpConstString # (index, tgt_reg, shadow_frame, self) 816 PREFETCH_INST 2 # load rINST 817 bnez v0, MterpPossibleException # let reference interpreter deal with it. 818 ADVANCE 2 # advance rPC 819 GET_INST_OPCODE v0 # extract opcode from rINST 820 GOTO_OPCODE v0 # jump to next instruction 821 822/* ------------------------------ */ 823 .balign 128 824.L_op_const_string_jumbo: /* 0x1b */ 825/* File: mips64/op_const_string_jumbo.S */ 826 /* const/string vAA, String//BBBBBBBB */ 827 .extern MterpConstString 828 EXPORT_PC 829 lh a0, 2(rPC) # a0 <- bbbb (low) 830 lh a4, 4(rPC) # a4 <- BBBB (high) 831 srl a1, rINST, 8 # a1 <- AA 832 ins a0, a4, 16, 16 # a0 <- BBBBbbbb 833 daddu a2, rFP, OFF_FP_SHADOWFRAME 834 move a3, rSELF 835 jal MterpConstString # (index, tgt_reg, shadow_frame, self) 836 PREFETCH_INST 3 # load rINST 837 bnez v0, MterpPossibleException # let reference interpreter deal with it. 838 ADVANCE 3 # advance rPC 839 GET_INST_OPCODE v0 # extract opcode from rINST 840 GOTO_OPCODE v0 # jump to next instruction 841 842/* ------------------------------ */ 843 .balign 128 844.L_op_const_class: /* 0x1c */ 845/* File: mips64/op_const_class.S */ 846 /* const/class vAA, Class//BBBB */ 847 .extern MterpConstClass 848 EXPORT_PC 849 lhu a0, 2(rPC) # a0 <- BBBB 850 srl a1, rINST, 8 # a1 <- AA 851 daddu a2, rFP, OFF_FP_SHADOWFRAME 852 move a3, rSELF 853 jal MterpConstClass # (index, tgt_reg, shadow_frame, self) 854 PREFETCH_INST 2 # load rINST 855 bnez v0, MterpPossibleException # let reference interpreter deal with it. 856 ADVANCE 2 # advance rPC 857 GET_INST_OPCODE v0 # extract opcode from rINST 858 GOTO_OPCODE v0 # jump to next instruction 859 860/* ------------------------------ */ 861 .balign 128 862.L_op_monitor_enter: /* 0x1d */ 863/* File: mips64/op_monitor_enter.S */ 864 /* 865 * Synchronize on an object. 866 */ 867 /* monitor-enter vAA */ 868 .extern artLockObjectFromCode 869 EXPORT_PC 870 srl a2, rINST, 8 # a2 <- AA 871 GET_VREG_U a0, a2 # a0 <- vAA (object) 872 move a1, rSELF # a1 <- self 873 jal artLockObjectFromCode 874 bnezc v0, MterpException 875 FETCH_ADVANCE_INST 1 876 GET_INST_OPCODE v0 # extract opcode from rINST 877 GOTO_OPCODE v0 # jump to next instruction 878 879/* ------------------------------ */ 880 .balign 128 881.L_op_monitor_exit: /* 0x1e */ 882/* File: mips64/op_monitor_exit.S */ 883 /* 884 * Unlock an object. 885 * 886 * Exceptions that occur when unlocking a monitor need to appear as 887 * if they happened at the following instruction. See the Dalvik 888 * instruction spec. 889 */ 890 /* monitor-exit vAA */ 891 .extern artUnlockObjectFromCode 892 EXPORT_PC 893 srl a2, rINST, 8 # a2 <- AA 894 GET_VREG_U a0, a2 # a0 <- vAA (object) 895 move a1, rSELF # a1 <- self 896 jal artUnlockObjectFromCode # v0 <- success for unlock(self, obj) 897 bnezc v0, MterpException 898 FETCH_ADVANCE_INST 1 # before throw: advance rPC, load rINST 899 GET_INST_OPCODE v0 # extract opcode from rINST 900 GOTO_OPCODE v0 # jump to next instruction 901 902/* ------------------------------ */ 903 .balign 128 904.L_op_check_cast: /* 0x1f */ 905/* File: mips64/op_check_cast.S */ 906 /* 907 * Check to see if a cast from one class to another is allowed. 908 */ 909 /* check-cast vAA, class//BBBB */ 910 .extern MterpCheckCast 911 EXPORT_PC 912 lhu a0, 2(rPC) # a0 <- BBBB 913 srl a1, rINST, 8 # a1 <- AA 914 dlsa a1, a1, rFP, 2 # a1 <- &object 915 ld a2, OFF_FP_METHOD(rFP) # a2 <- method 916 move a3, rSELF # a3 <- self 917 jal MterpCheckCast # (index, &obj, method, self) 918 PREFETCH_INST 2 919 bnez v0, MterpPossibleException 920 ADVANCE 2 921 GET_INST_OPCODE v0 # extract opcode from rINST 922 GOTO_OPCODE v0 # jump to next instruction 923 924/* ------------------------------ */ 925 .balign 128 926.L_op_instance_of: /* 0x20 */ 927/* File: mips64/op_instance_of.S */ 928 /* 929 * Check to see if an object reference is an instance of a class. 930 * 931 * Most common situation is a non-null object, being compared against 932 * an already-resolved class. 933 */ 934 /* instance-of vA, vB, class//CCCC */ 935 .extern MterpInstanceOf 936 EXPORT_PC 937 lhu a0, 2(rPC) # a0 <- CCCC 938 srl a1, rINST, 12 # a1 <- B 939 dlsa a1, a1, rFP, 2 # a1 <- &object 940 ld a2, OFF_FP_METHOD(rFP) # a2 <- method 941 move a3, rSELF # a3 <- self 942 jal MterpInstanceOf # (index, &obj, method, self) 943 ld a1, THREAD_EXCEPTION_OFFSET(rSELF) 944 ext a2, rINST, 8, 4 # a2 <- A 945 PREFETCH_INST 2 946 bnez a1, MterpException 947 ADVANCE 2 # advance rPC 948 SET_VREG v0, a2 # vA <- v0 949 GET_INST_OPCODE v0 # extract opcode from rINST 950 GOTO_OPCODE v0 # jump to next instruction 951 952/* ------------------------------ */ 953 .balign 128 954.L_op_array_length: /* 0x21 */ 955/* File: mips64/op_array_length.S */ 956 /* 957 * Return the length of an array. 958 */ 959 srl a1, rINST, 12 # a1 <- B 960 GET_VREG_U a0, a1 # a0 <- vB (object ref) 961 ext a2, rINST, 8, 4 # a2 <- A 962 beqz a0, common_errNullObject # yup, fail 963 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 964 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- array length 965 GET_INST_OPCODE v0 # extract opcode from rINST 966 SET_VREG a3, a2 # vB <- length 967 GOTO_OPCODE v0 # jump to next instruction 968 969/* ------------------------------ */ 970 .balign 128 971.L_op_new_instance: /* 0x22 */ 972/* File: mips64/op_new_instance.S */ 973 /* 974 * Create a new instance of a class. 975 */ 976 /* new-instance vAA, class//BBBB */ 977 .extern MterpNewInstance 978 EXPORT_PC 979 daddu a0, rFP, OFF_FP_SHADOWFRAME 980 move a1, rSELF 981 move a2, rINST 982 jal MterpNewInstance # (shadow_frame, self, inst_data) 983 beqzc v0, MterpPossibleException 984 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 985 GET_INST_OPCODE v0 # extract opcode from rINST 986 GOTO_OPCODE v0 # jump to next instruction 987 988/* ------------------------------ */ 989 .balign 128 990.L_op_new_array: /* 0x23 */ 991/* File: mips64/op_new_array.S */ 992 /* 993 * Allocate an array of objects, specified with the array class 994 * and a count. 995 * 996 * The verifier guarantees that this is an array class, so we don't 997 * check for it here. 998 */ 999 /* new-array vA, vB, class//CCCC */ 1000 .extern MterpNewArray 1001 EXPORT_PC 1002 daddu a0, rFP, OFF_FP_SHADOWFRAME 1003 move a1, rPC 1004 move a2, rINST 1005 move a3, rSELF 1006 jal MterpNewArray 1007 beqzc v0, MterpPossibleException 1008 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1009 GET_INST_OPCODE v0 # extract opcode from rINST 1010 GOTO_OPCODE v0 # jump to next instruction 1011 1012/* ------------------------------ */ 1013 .balign 128 1014.L_op_filled_new_array: /* 0x24 */ 1015/* File: mips64/op_filled_new_array.S */ 1016 /* 1017 * Create a new array with elements filled from registers. 1018 * 1019 * for: filled-new-array, filled-new-array/range 1020 */ 1021 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ 1022 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ 1023 .extern MterpFilledNewArray 1024 EXPORT_PC 1025 daddu a0, rFP, OFF_FP_SHADOWFRAME 1026 move a1, rPC 1027 move a2, rSELF 1028 jal MterpFilledNewArray 1029 beqzc v0, MterpPossibleException 1030 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 1031 GET_INST_OPCODE v0 # extract opcode from rINST 1032 GOTO_OPCODE v0 # jump to next instruction 1033 1034/* ------------------------------ */ 1035 .balign 128 1036.L_op_filled_new_array_range: /* 0x25 */ 1037/* File: mips64/op_filled_new_array_range.S */ 1038/* File: mips64/op_filled_new_array.S */ 1039 /* 1040 * Create a new array with elements filled from registers. 1041 * 1042 * for: filled-new-array, filled-new-array/range 1043 */ 1044 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ 1045 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ 1046 .extern MterpFilledNewArrayRange 1047 EXPORT_PC 1048 daddu a0, rFP, OFF_FP_SHADOWFRAME 1049 move a1, rPC 1050 move a2, rSELF 1051 jal MterpFilledNewArrayRange 1052 beqzc v0, MterpPossibleException 1053 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 1054 GET_INST_OPCODE v0 # extract opcode from rINST 1055 GOTO_OPCODE v0 # jump to next instruction 1056 1057 1058/* ------------------------------ */ 1059 .balign 128 1060.L_op_fill_array_data: /* 0x26 */ 1061/* File: mips64/op_fill_array_data.S */ 1062 /* fill-array-data vAA, +BBBBBBBB */ 1063 .extern MterpFillArrayData 1064 EXPORT_PC 1065 lh a1, 2(rPC) # a1 <- bbbb (lo) 1066 lh a0, 4(rPC) # a0 <- BBBB (hi) 1067 srl a3, rINST, 8 # a3 <- AA 1068 ins a1, a0, 16, 16 # a1 <- BBBBbbbb 1069 GET_VREG_U a0, a3 # a0 <- vAA (array object) 1070 dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.) 1071 jal MterpFillArrayData # (obj, payload) 1072 beqzc v0, MterpPossibleException # exception? 1073 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 1074 GET_INST_OPCODE v0 # extract opcode from rINST 1075 GOTO_OPCODE v0 # jump to next instruction 1076 1077/* ------------------------------ */ 1078 .balign 128 1079.L_op_throw: /* 0x27 */ 1080/* File: mips64/op_throw.S */ 1081 /* 1082 * Throw an exception object in the current thread. 1083 */ 1084 /* throw vAA */ 1085 EXPORT_PC 1086 srl a2, rINST, 8 # a2 <- AA 1087 GET_VREG_U a0, a2 # a0 <- vAA (exception object) 1088 beqzc a0, common_errNullObject 1089 sd a0, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj 1090 b MterpException 1091 1092/* ------------------------------ */ 1093 .balign 128 1094.L_op_goto: /* 0x28 */ 1095/* File: mips64/op_goto.S */ 1096 /* 1097 * Unconditional branch, 8-bit offset. 1098 * 1099 * The branch distance is a signed code-unit offset, which we need to 1100 * double to get a byte offset. 1101 */ 1102 /* goto +AA */ 1103 .extern MterpProfileBranch 1104 srl rINST, rINST, 8 1105 seb rINST, rINST # rINST <- offset (sign-extended AA) 1106#if MTERP_PROFILE_BRANCHES 1107 EXPORT_PC 1108 move a0, rSELF 1109 daddu a1, rFP, OFF_FP_SHADOWFRAME 1110 move a2, rINST 1111 jal MterpProfileBranch # (self, shadow_frame, offset) 1112 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1113#endif 1114 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1115 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1116 move a0, rINST # a0 <- offset 1117 FETCH_INST # load rINST 1118 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1119 GET_INST_OPCODE v0 # extract opcode from rINST 1120 GOTO_OPCODE v0 # jump to next instruction 1121 1122/* ------------------------------ */ 1123 .balign 128 1124.L_op_goto_16: /* 0x29 */ 1125/* File: mips64/op_goto_16.S */ 1126 /* 1127 * Unconditional branch, 16-bit offset. 1128 * 1129 * The branch distance is a signed code-unit offset, which we need to 1130 * double to get a byte offset. 1131 */ 1132 /* goto/16 +AAAA */ 1133 .extern MterpProfileBranch 1134 lh rINST, 2(rPC) # rINST <- offset (sign-extended AAAA) 1135#if MTERP_PROFILE_BRANCHES 1136 EXPORT_PC 1137 move a0, rSELF 1138 daddu a1, rFP, OFF_FP_SHADOWFRAME 1139 move a2, rINST 1140 jal MterpProfileBranch # (self, shadow_frame, offset) 1141 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1142#endif 1143 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1144 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1145 move a0, rINST # a0 <- offset 1146 FETCH_INST # load rINST 1147 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1148 GET_INST_OPCODE v0 # extract opcode from rINST 1149 GOTO_OPCODE v0 # jump to next instruction 1150 1151/* ------------------------------ */ 1152 .balign 128 1153.L_op_goto_32: /* 0x2a */ 1154/* File: mips64/op_goto_32.S */ 1155 /* 1156 * Unconditional branch, 32-bit offset. 1157 * 1158 * The branch distance is a signed code-unit offset, which we need to 1159 * double to get a byte offset. 1160 * 1161 * Unlike most opcodes, this one is allowed to branch to itself, so 1162 * our "backward branch" test must be "<=0" instead of "<0". 1163 */ 1164 /* goto/32 +AAAAAAAA */ 1165 .extern MterpProfileBranch 1166 lh rINST, 2(rPC) # rINST <- aaaa (low) 1167 lh a1, 4(rPC) # a1 <- AAAA (high) 1168 ins rINST, a1, 16, 16 # rINST <- offset (sign-extended AAAAaaaa) 1169#if MTERP_PROFILE_BRANCHES 1170 EXPORT_PC 1171 move a0, rSELF 1172 daddu a1, rFP, OFF_FP_SHADOWFRAME 1173 move a2, rINST 1174 jal MterpProfileBranch # (self, shadow_frame, offset) 1175 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1176#endif 1177 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1178 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1179 move a0, rINST # a0 <- offset 1180 FETCH_INST # load rINST 1181 blez a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1182 GET_INST_OPCODE v0 # extract opcode from rINST 1183 GOTO_OPCODE v0 # jump to next instruction 1184 1185/* ------------------------------ */ 1186 .balign 128 1187.L_op_packed_switch: /* 0x2b */ 1188/* File: mips64/op_packed_switch.S */ 1189 /* 1190 * Handle a packed-switch or sparse-switch instruction. In both cases 1191 * we decode it and hand it off to a helper function. 1192 * 1193 * We don't really expect backward branches in a switch statement, but 1194 * they're perfectly legal, so we check for them here. 1195 * 1196 * for: packed-switch, sparse-switch 1197 */ 1198 /* op vAA, +BBBBBBBB */ 1199 .extern MterpDoPackedSwitch 1200 .extern MterpProfileBranch 1201 lh a0, 2(rPC) # a0 <- bbbb (lo) 1202 lh a1, 4(rPC) # a1 <- BBBB (hi) 1203 srl a3, rINST, 8 # a3 <- AA 1204 ins a0, a1, 16, 16 # a0 <- BBBBbbbb 1205 GET_VREG a1, a3 # a1 <- vAA 1206 dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 1207 jal MterpDoPackedSwitch # v0 <- code-unit branch offset 1208 move rINST, v0 1209#if MTERP_PROFILE_BRANCHES 1210 EXPORT_PC 1211 move a0, rSELF 1212 daddu a1, rFP, OFF_FP_SHADOWFRAME 1213 move a2, rINST 1214 jal MterpProfileBranch # (self, shadow_frame, offset) 1215 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1216#endif 1217 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1218 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1219 move a0, rINST # a0 <- offset 1220 FETCH_INST # load rINST 1221 blez a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1222 GET_INST_OPCODE v0 # extract opcode from rINST 1223 GOTO_OPCODE v0 # jump to next instruction 1224 1225/* ------------------------------ */ 1226 .balign 128 1227.L_op_sparse_switch: /* 0x2c */ 1228/* File: mips64/op_sparse_switch.S */ 1229/* File: mips64/op_packed_switch.S */ 1230 /* 1231 * Handle a packed-switch or sparse-switch instruction. In both cases 1232 * we decode it and hand it off to a helper function. 1233 * 1234 * We don't really expect backward branches in a switch statement, but 1235 * they're perfectly legal, so we check for them here. 1236 * 1237 * for: packed-switch, sparse-switch 1238 */ 1239 /* op vAA, +BBBBBBBB */ 1240 .extern MterpDoSparseSwitch 1241 .extern MterpProfileBranch 1242 lh a0, 2(rPC) # a0 <- bbbb (lo) 1243 lh a1, 4(rPC) # a1 <- BBBB (hi) 1244 srl a3, rINST, 8 # a3 <- AA 1245 ins a0, a1, 16, 16 # a0 <- BBBBbbbb 1246 GET_VREG a1, a3 # a1 <- vAA 1247 dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 1248 jal MterpDoSparseSwitch # v0 <- code-unit branch offset 1249 move rINST, v0 1250#if MTERP_PROFILE_BRANCHES 1251 EXPORT_PC 1252 move a0, rSELF 1253 daddu a1, rFP, OFF_FP_SHADOWFRAME 1254 move a2, rINST 1255 jal MterpProfileBranch # (self, shadow_frame, offset) 1256 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1257#endif 1258 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1259 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1260 move a0, rINST # a0 <- offset 1261 FETCH_INST # load rINST 1262 blez a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1263 GET_INST_OPCODE v0 # extract opcode from rINST 1264 GOTO_OPCODE v0 # jump to next instruction 1265 1266 1267/* ------------------------------ */ 1268 .balign 128 1269.L_op_cmpl_float: /* 0x2d */ 1270/* File: mips64/op_cmpl_float.S */ 1271/* File: mips64/fcmp.S */ 1272 /* 1273 * Compare two floating-point values. Puts 0, 1, or -1 into the 1274 * destination register based on the results of the comparison. 1275 * 1276 * For: cmpl-float, cmpg-float 1277 */ 1278 /* op vAA, vBB, vCC */ 1279 srl a4, rINST, 8 # a4 <- AA 1280 lbu a2, 2(rPC) # a2 <- BB 1281 lbu a3, 3(rPC) # a3 <- CC 1282 GET_VREG_FLOAT f0, a2 # f0 <- vBB 1283 GET_VREG_FLOAT f1, a3 # f1 <- vCC 1284 cmp.eq.s f2, f0, f1 1285 li a0, 0 1286 bc1nez f2, 1f # done if vBB == vCC (ordered) 1287 .if 0 1288 cmp.lt.s f2, f0, f1 1289 li a0, -1 1290 bc1nez f2, 1f # done if vBB < vCC (ordered) 1291 li a0, 1 # vBB > vCC or unordered 1292 .else 1293 cmp.lt.s f2, f1, f0 1294 li a0, 1 1295 bc1nez f2, 1f # done if vBB > vCC (ordered) 1296 li a0, -1 # vBB < vCC or unordered 1297 .endif 12981: 1299 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1300 GET_INST_OPCODE v0 # extract opcode from rINST 1301 SET_VREG a0, a4 # vAA <- a0 1302 GOTO_OPCODE v0 # jump to next instruction 1303 1304 1305/* ------------------------------ */ 1306 .balign 128 1307.L_op_cmpg_float: /* 0x2e */ 1308/* File: mips64/op_cmpg_float.S */ 1309/* File: mips64/fcmp.S */ 1310 /* 1311 * Compare two floating-point values. Puts 0, 1, or -1 into the 1312 * destination register based on the results of the comparison. 1313 * 1314 * For: cmpl-float, cmpg-float 1315 */ 1316 /* op vAA, vBB, vCC */ 1317 srl a4, rINST, 8 # a4 <- AA 1318 lbu a2, 2(rPC) # a2 <- BB 1319 lbu a3, 3(rPC) # a3 <- CC 1320 GET_VREG_FLOAT f0, a2 # f0 <- vBB 1321 GET_VREG_FLOAT f1, a3 # f1 <- vCC 1322 cmp.eq.s f2, f0, f1 1323 li a0, 0 1324 bc1nez f2, 1f # done if vBB == vCC (ordered) 1325 .if 1 1326 cmp.lt.s f2, f0, f1 1327 li a0, -1 1328 bc1nez f2, 1f # done if vBB < vCC (ordered) 1329 li a0, 1 # vBB > vCC or unordered 1330 .else 1331 cmp.lt.s f2, f1, f0 1332 li a0, 1 1333 bc1nez f2, 1f # done if vBB > vCC (ordered) 1334 li a0, -1 # vBB < vCC or unordered 1335 .endif 13361: 1337 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1338 GET_INST_OPCODE v0 # extract opcode from rINST 1339 SET_VREG a0, a4 # vAA <- a0 1340 GOTO_OPCODE v0 # jump to next instruction 1341 1342 1343/* ------------------------------ */ 1344 .balign 128 1345.L_op_cmpl_double: /* 0x2f */ 1346/* File: mips64/op_cmpl_double.S */ 1347/* File: mips64/fcmpWide.S */ 1348 /* 1349 * Compare two floating-point values. Puts 0, 1, or -1 into the 1350 * destination register based on the results of the comparison. 1351 * 1352 * For: cmpl-double, cmpg-double 1353 */ 1354 /* op vAA, vBB, vCC */ 1355 srl a4, rINST, 8 # a4 <- AA 1356 lbu a2, 2(rPC) # a2 <- BB 1357 lbu a3, 3(rPC) # a3 <- CC 1358 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 1359 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 1360 cmp.eq.d f2, f0, f1 1361 li a0, 0 1362 bc1nez f2, 1f # done if vBB == vCC (ordered) 1363 .if 0 1364 cmp.lt.d f2, f0, f1 1365 li a0, -1 1366 bc1nez f2, 1f # done if vBB < vCC (ordered) 1367 li a0, 1 # vBB > vCC or unordered 1368 .else 1369 cmp.lt.d f2, f1, f0 1370 li a0, 1 1371 bc1nez f2, 1f # done if vBB > vCC (ordered) 1372 li a0, -1 # vBB < vCC or unordered 1373 .endif 13741: 1375 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1376 GET_INST_OPCODE v0 # extract opcode from rINST 1377 SET_VREG a0, a4 # vAA <- a0 1378 GOTO_OPCODE v0 # jump to next instruction 1379 1380 1381/* ------------------------------ */ 1382 .balign 128 1383.L_op_cmpg_double: /* 0x30 */ 1384/* File: mips64/op_cmpg_double.S */ 1385/* File: mips64/fcmpWide.S */ 1386 /* 1387 * Compare two floating-point values. Puts 0, 1, or -1 into the 1388 * destination register based on the results of the comparison. 1389 * 1390 * For: cmpl-double, cmpg-double 1391 */ 1392 /* op vAA, vBB, vCC */ 1393 srl a4, rINST, 8 # a4 <- AA 1394 lbu a2, 2(rPC) # a2 <- BB 1395 lbu a3, 3(rPC) # a3 <- CC 1396 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 1397 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 1398 cmp.eq.d f2, f0, f1 1399 li a0, 0 1400 bc1nez f2, 1f # done if vBB == vCC (ordered) 1401 .if 1 1402 cmp.lt.d f2, f0, f1 1403 li a0, -1 1404 bc1nez f2, 1f # done if vBB < vCC (ordered) 1405 li a0, 1 # vBB > vCC or unordered 1406 .else 1407 cmp.lt.d f2, f1, f0 1408 li a0, 1 1409 bc1nez f2, 1f # done if vBB > vCC (ordered) 1410 li a0, -1 # vBB < vCC or unordered 1411 .endif 14121: 1413 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1414 GET_INST_OPCODE v0 # extract opcode from rINST 1415 SET_VREG a0, a4 # vAA <- a0 1416 GOTO_OPCODE v0 # jump to next instruction 1417 1418 1419/* ------------------------------ */ 1420 .balign 128 1421.L_op_cmp_long: /* 0x31 */ 1422/* File: mips64/op_cmp_long.S */ 1423 /* cmp-long vAA, vBB, vCC */ 1424 lbu a2, 2(rPC) # a2 <- BB 1425 lbu a3, 3(rPC) # a3 <- CC 1426 srl a4, rINST, 8 # a4 <- AA 1427 GET_VREG_WIDE a0, a2 # a0 <- vBB 1428 GET_VREG_WIDE a1, a3 # a1 <- vCC 1429 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1430 slt a2, a0, a1 1431 slt a0, a1, a0 1432 subu a0, a0, a2 1433 GET_INST_OPCODE v0 # extract opcode from rINST 1434 SET_VREG a0, a4 # vAA <- result 1435 GOTO_OPCODE v0 # jump to next instruction 1436 1437/* ------------------------------ */ 1438 .balign 128 1439.L_op_if_eq: /* 0x32 */ 1440/* File: mips64/op_if_eq.S */ 1441/* File: mips64/bincmp.S */ 1442 /* 1443 * Generic two-operand compare-and-branch operation. Provide a "condition" 1444 * fragment that specifies the comparison to perform, e.g. for 1445 * "if-le" you would use "le". 1446 * 1447 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1448 */ 1449 /* if-cmp vA, vB, +CCCC */ 1450 .extern MterpProfileBranch 1451 ext a2, rINST, 8, 4 # a2 <- A 1452 ext a3, rINST, 12, 4 # a3 <- B 1453 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1454 GET_VREG a0, a2 # a0 <- vA 1455 GET_VREG a1, a3 # a1 <- vB 1456 beqc a0, a1, 1f 1457 li rINST, 2 # offset if branch not taken 14581: 1459#if MTERP_PROFILE_BRANCHES 1460 EXPORT_PC 1461 move a0, rSELF 1462 daddu a1, rFP, OFF_FP_SHADOWFRAME 1463 move a2, rINST 1464 jal MterpProfileBranch # (self, shadow_frame, offset) 1465 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1466#endif 1467 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1468 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1469 move a0, rINST # a0 <- offset 1470 FETCH_INST # load rINST 1471 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1472 GET_INST_OPCODE v0 # extract opcode from rINST 1473 GOTO_OPCODE v0 # jump to next instruction 1474 1475 1476/* ------------------------------ */ 1477 .balign 128 1478.L_op_if_ne: /* 0x33 */ 1479/* File: mips64/op_if_ne.S */ 1480/* File: mips64/bincmp.S */ 1481 /* 1482 * Generic two-operand compare-and-branch operation. Provide a "condition" 1483 * fragment that specifies the comparison to perform, e.g. for 1484 * "if-le" you would use "le". 1485 * 1486 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1487 */ 1488 /* if-cmp vA, vB, +CCCC */ 1489 .extern MterpProfileBranch 1490 ext a2, rINST, 8, 4 # a2 <- A 1491 ext a3, rINST, 12, 4 # a3 <- B 1492 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1493 GET_VREG a0, a2 # a0 <- vA 1494 GET_VREG a1, a3 # a1 <- vB 1495 bnec a0, a1, 1f 1496 li rINST, 2 # offset if branch not taken 14971: 1498#if MTERP_PROFILE_BRANCHES 1499 EXPORT_PC 1500 move a0, rSELF 1501 daddu a1, rFP, OFF_FP_SHADOWFRAME 1502 move a2, rINST 1503 jal MterpProfileBranch # (self, shadow_frame, offset) 1504 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1505#endif 1506 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1507 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1508 move a0, rINST # a0 <- offset 1509 FETCH_INST # load rINST 1510 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1511 GET_INST_OPCODE v0 # extract opcode from rINST 1512 GOTO_OPCODE v0 # jump to next instruction 1513 1514 1515/* ------------------------------ */ 1516 .balign 128 1517.L_op_if_lt: /* 0x34 */ 1518/* File: mips64/op_if_lt.S */ 1519/* File: mips64/bincmp.S */ 1520 /* 1521 * Generic two-operand compare-and-branch operation. Provide a "condition" 1522 * fragment that specifies the comparison to perform, e.g. for 1523 * "if-le" you would use "le". 1524 * 1525 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1526 */ 1527 /* if-cmp vA, vB, +CCCC */ 1528 .extern MterpProfileBranch 1529 ext a2, rINST, 8, 4 # a2 <- A 1530 ext a3, rINST, 12, 4 # a3 <- B 1531 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1532 GET_VREG a0, a2 # a0 <- vA 1533 GET_VREG a1, a3 # a1 <- vB 1534 bltc a0, a1, 1f 1535 li rINST, 2 # offset if branch not taken 15361: 1537#if MTERP_PROFILE_BRANCHES 1538 EXPORT_PC 1539 move a0, rSELF 1540 daddu a1, rFP, OFF_FP_SHADOWFRAME 1541 move a2, rINST 1542 jal MterpProfileBranch # (self, shadow_frame, offset) 1543 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1544#endif 1545 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1546 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1547 move a0, rINST # a0 <- offset 1548 FETCH_INST # load rINST 1549 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1550 GET_INST_OPCODE v0 # extract opcode from rINST 1551 GOTO_OPCODE v0 # jump to next instruction 1552 1553 1554/* ------------------------------ */ 1555 .balign 128 1556.L_op_if_ge: /* 0x35 */ 1557/* File: mips64/op_if_ge.S */ 1558/* File: mips64/bincmp.S */ 1559 /* 1560 * Generic two-operand compare-and-branch operation. Provide a "condition" 1561 * fragment that specifies the comparison to perform, e.g. for 1562 * "if-le" you would use "le". 1563 * 1564 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1565 */ 1566 /* if-cmp vA, vB, +CCCC */ 1567 .extern MterpProfileBranch 1568 ext a2, rINST, 8, 4 # a2 <- A 1569 ext a3, rINST, 12, 4 # a3 <- B 1570 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1571 GET_VREG a0, a2 # a0 <- vA 1572 GET_VREG a1, a3 # a1 <- vB 1573 bgec a0, a1, 1f 1574 li rINST, 2 # offset if branch not taken 15751: 1576#if MTERP_PROFILE_BRANCHES 1577 EXPORT_PC 1578 move a0, rSELF 1579 daddu a1, rFP, OFF_FP_SHADOWFRAME 1580 move a2, rINST 1581 jal MterpProfileBranch # (self, shadow_frame, offset) 1582 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1583#endif 1584 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1585 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1586 move a0, rINST # a0 <- offset 1587 FETCH_INST # load rINST 1588 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1589 GET_INST_OPCODE v0 # extract opcode from rINST 1590 GOTO_OPCODE v0 # jump to next instruction 1591 1592 1593/* ------------------------------ */ 1594 .balign 128 1595.L_op_if_gt: /* 0x36 */ 1596/* File: mips64/op_if_gt.S */ 1597/* File: mips64/bincmp.S */ 1598 /* 1599 * Generic two-operand compare-and-branch operation. Provide a "condition" 1600 * fragment that specifies the comparison to perform, e.g. for 1601 * "if-le" you would use "le". 1602 * 1603 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1604 */ 1605 /* if-cmp vA, vB, +CCCC */ 1606 .extern MterpProfileBranch 1607 ext a2, rINST, 8, 4 # a2 <- A 1608 ext a3, rINST, 12, 4 # a3 <- B 1609 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1610 GET_VREG a0, a2 # a0 <- vA 1611 GET_VREG a1, a3 # a1 <- vB 1612 bgtc a0, a1, 1f 1613 li rINST, 2 # offset if branch not taken 16141: 1615#if MTERP_PROFILE_BRANCHES 1616 EXPORT_PC 1617 move a0, rSELF 1618 daddu a1, rFP, OFF_FP_SHADOWFRAME 1619 move a2, rINST 1620 jal MterpProfileBranch # (self, shadow_frame, offset) 1621 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1622#endif 1623 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1624 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1625 move a0, rINST # a0 <- offset 1626 FETCH_INST # load rINST 1627 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1628 GET_INST_OPCODE v0 # extract opcode from rINST 1629 GOTO_OPCODE v0 # jump to next instruction 1630 1631 1632/* ------------------------------ */ 1633 .balign 128 1634.L_op_if_le: /* 0x37 */ 1635/* File: mips64/op_if_le.S */ 1636/* File: mips64/bincmp.S */ 1637 /* 1638 * Generic two-operand compare-and-branch operation. Provide a "condition" 1639 * fragment that specifies the comparison to perform, e.g. for 1640 * "if-le" you would use "le". 1641 * 1642 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1643 */ 1644 /* if-cmp vA, vB, +CCCC */ 1645 .extern MterpProfileBranch 1646 ext a2, rINST, 8, 4 # a2 <- A 1647 ext a3, rINST, 12, 4 # a3 <- B 1648 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1649 GET_VREG a0, a2 # a0 <- vA 1650 GET_VREG a1, a3 # a1 <- vB 1651 blec a0, a1, 1f 1652 li rINST, 2 # offset if branch not taken 16531: 1654#if MTERP_PROFILE_BRANCHES 1655 EXPORT_PC 1656 move a0, rSELF 1657 daddu a1, rFP, OFF_FP_SHADOWFRAME 1658 move a2, rINST 1659 jal MterpProfileBranch # (self, shadow_frame, offset) 1660 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1661#endif 1662 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1663 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1664 move a0, rINST # a0 <- offset 1665 FETCH_INST # load rINST 1666 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1667 GET_INST_OPCODE v0 # extract opcode from rINST 1668 GOTO_OPCODE v0 # jump to next instruction 1669 1670 1671/* ------------------------------ */ 1672 .balign 128 1673.L_op_if_eqz: /* 0x38 */ 1674/* File: mips64/op_if_eqz.S */ 1675/* File: mips64/zcmp.S */ 1676 /* 1677 * Generic one-operand compare-and-branch operation. Provide a "condition" 1678 * fragment that specifies the comparison to perform, e.g. for 1679 * "if-lez" you would use "le". 1680 * 1681 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1682 */ 1683 /* if-cmp vAA, +BBBB */ 1684 .extern MterpProfileBranch 1685 srl a2, rINST, 8 # a2 <- AA 1686 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1687 GET_VREG a0, a2 # a0 <- vAA 1688 beqzc a0, 1f 1689 li rINST, 2 # offset if branch not taken 16901: 1691#if MTERP_PROFILE_BRANCHES 1692 EXPORT_PC 1693 move a0, rSELF 1694 daddu a1, rFP, OFF_FP_SHADOWFRAME 1695 move a2, rINST 1696 jal MterpProfileBranch # (self, shadow_frame, offset) 1697 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1698#endif 1699 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1700 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1701 move a0, rINST # a0 <- offset 1702 FETCH_INST # load rINST 1703 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1704 GET_INST_OPCODE v0 # extract opcode from rINST 1705 GOTO_OPCODE v0 # jump to next instruction 1706 1707 1708/* ------------------------------ */ 1709 .balign 128 1710.L_op_if_nez: /* 0x39 */ 1711/* File: mips64/op_if_nez.S */ 1712/* File: mips64/zcmp.S */ 1713 /* 1714 * Generic one-operand compare-and-branch operation. Provide a "condition" 1715 * fragment that specifies the comparison to perform, e.g. for 1716 * "if-lez" you would use "le". 1717 * 1718 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1719 */ 1720 /* if-cmp vAA, +BBBB */ 1721 .extern MterpProfileBranch 1722 srl a2, rINST, 8 # a2 <- AA 1723 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1724 GET_VREG a0, a2 # a0 <- vAA 1725 bnezc a0, 1f 1726 li rINST, 2 # offset if branch not taken 17271: 1728#if MTERP_PROFILE_BRANCHES 1729 EXPORT_PC 1730 move a0, rSELF 1731 daddu a1, rFP, OFF_FP_SHADOWFRAME 1732 move a2, rINST 1733 jal MterpProfileBranch # (self, shadow_frame, offset) 1734 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1735#endif 1736 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1737 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1738 move a0, rINST # a0 <- offset 1739 FETCH_INST # load rINST 1740 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1741 GET_INST_OPCODE v0 # extract opcode from rINST 1742 GOTO_OPCODE v0 # jump to next instruction 1743 1744 1745/* ------------------------------ */ 1746 .balign 128 1747.L_op_if_ltz: /* 0x3a */ 1748/* File: mips64/op_if_ltz.S */ 1749/* File: mips64/zcmp.S */ 1750 /* 1751 * Generic one-operand compare-and-branch operation. Provide a "condition" 1752 * fragment that specifies the comparison to perform, e.g. for 1753 * "if-lez" you would use "le". 1754 * 1755 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1756 */ 1757 /* if-cmp vAA, +BBBB */ 1758 .extern MterpProfileBranch 1759 srl a2, rINST, 8 # a2 <- AA 1760 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1761 GET_VREG a0, a2 # a0 <- vAA 1762 bltzc a0, 1f 1763 li rINST, 2 # offset if branch not taken 17641: 1765#if MTERP_PROFILE_BRANCHES 1766 EXPORT_PC 1767 move a0, rSELF 1768 daddu a1, rFP, OFF_FP_SHADOWFRAME 1769 move a2, rINST 1770 jal MterpProfileBranch # (self, shadow_frame, offset) 1771 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1772#endif 1773 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1774 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1775 move a0, rINST # a0 <- offset 1776 FETCH_INST # load rINST 1777 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1778 GET_INST_OPCODE v0 # extract opcode from rINST 1779 GOTO_OPCODE v0 # jump to next instruction 1780 1781 1782/* ------------------------------ */ 1783 .balign 128 1784.L_op_if_gez: /* 0x3b */ 1785/* File: mips64/op_if_gez.S */ 1786/* File: mips64/zcmp.S */ 1787 /* 1788 * Generic one-operand compare-and-branch operation. Provide a "condition" 1789 * fragment that specifies the comparison to perform, e.g. for 1790 * "if-lez" you would use "le". 1791 * 1792 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1793 */ 1794 /* if-cmp vAA, +BBBB */ 1795 .extern MterpProfileBranch 1796 srl a2, rINST, 8 # a2 <- AA 1797 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1798 GET_VREG a0, a2 # a0 <- vAA 1799 bgezc a0, 1f 1800 li rINST, 2 # offset if branch not taken 18011: 1802#if MTERP_PROFILE_BRANCHES 1803 EXPORT_PC 1804 move a0, rSELF 1805 daddu a1, rFP, OFF_FP_SHADOWFRAME 1806 move a2, rINST 1807 jal MterpProfileBranch # (self, shadow_frame, offset) 1808 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1809#endif 1810 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1811 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1812 move a0, rINST # a0 <- offset 1813 FETCH_INST # load rINST 1814 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1815 GET_INST_OPCODE v0 # extract opcode from rINST 1816 GOTO_OPCODE v0 # jump to next instruction 1817 1818 1819/* ------------------------------ */ 1820 .balign 128 1821.L_op_if_gtz: /* 0x3c */ 1822/* File: mips64/op_if_gtz.S */ 1823/* File: mips64/zcmp.S */ 1824 /* 1825 * Generic one-operand compare-and-branch operation. Provide a "condition" 1826 * fragment that specifies the comparison to perform, e.g. for 1827 * "if-lez" you would use "le". 1828 * 1829 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1830 */ 1831 /* if-cmp vAA, +BBBB */ 1832 .extern MterpProfileBranch 1833 srl a2, rINST, 8 # a2 <- AA 1834 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1835 GET_VREG a0, a2 # a0 <- vAA 1836 bgtzc a0, 1f 1837 li rINST, 2 # offset if branch not taken 18381: 1839#if MTERP_PROFILE_BRANCHES 1840 EXPORT_PC 1841 move a0, rSELF 1842 daddu a1, rFP, OFF_FP_SHADOWFRAME 1843 move a2, rINST 1844 jal MterpProfileBranch # (self, shadow_frame, offset) 1845 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1846#endif 1847 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1848 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1849 move a0, rINST # a0 <- offset 1850 FETCH_INST # load rINST 1851 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1852 GET_INST_OPCODE v0 # extract opcode from rINST 1853 GOTO_OPCODE v0 # jump to next instruction 1854 1855 1856/* ------------------------------ */ 1857 .balign 128 1858.L_op_if_lez: /* 0x3d */ 1859/* File: mips64/op_if_lez.S */ 1860/* File: mips64/zcmp.S */ 1861 /* 1862 * Generic one-operand compare-and-branch operation. Provide a "condition" 1863 * fragment that specifies the comparison to perform, e.g. for 1864 * "if-lez" you would use "le". 1865 * 1866 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1867 */ 1868 /* if-cmp vAA, +BBBB */ 1869 .extern MterpProfileBranch 1870 srl a2, rINST, 8 # a2 <- AA 1871 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1872 GET_VREG a0, a2 # a0 <- vAA 1873 blezc a0, 1f 1874 li rINST, 2 # offset if branch not taken 18751: 1876#if MTERP_PROFILE_BRANCHES 1877 EXPORT_PC 1878 move a0, rSELF 1879 daddu a1, rFP, OFF_FP_SHADOWFRAME 1880 move a2, rINST 1881 jal MterpProfileBranch # (self, shadow_frame, offset) 1882 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 1883#endif 1884 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 1885 lw ra, THREAD_FLAGS_OFFSET(rSELF) # Preload flags for MterpCheckSuspendAndContinue 1886 move a0, rINST # a0 <- offset 1887 FETCH_INST # load rINST 1888 bltz a0, MterpCheckSuspendAndContinue # suspend check if backwards branch 1889 GET_INST_OPCODE v0 # extract opcode from rINST 1890 GOTO_OPCODE v0 # jump to next instruction 1891 1892 1893/* ------------------------------ */ 1894 .balign 128 1895.L_op_unused_3e: /* 0x3e */ 1896/* File: mips64/op_unused_3e.S */ 1897/* File: mips64/unused.S */ 1898/* 1899 * Bail to reference interpreter to throw. 1900 */ 1901 b MterpFallback 1902 1903 1904/* ------------------------------ */ 1905 .balign 128 1906.L_op_unused_3f: /* 0x3f */ 1907/* File: mips64/op_unused_3f.S */ 1908/* File: mips64/unused.S */ 1909/* 1910 * Bail to reference interpreter to throw. 1911 */ 1912 b MterpFallback 1913 1914 1915/* ------------------------------ */ 1916 .balign 128 1917.L_op_unused_40: /* 0x40 */ 1918/* File: mips64/op_unused_40.S */ 1919/* File: mips64/unused.S */ 1920/* 1921 * Bail to reference interpreter to throw. 1922 */ 1923 b MterpFallback 1924 1925 1926/* ------------------------------ */ 1927 .balign 128 1928.L_op_unused_41: /* 0x41 */ 1929/* File: mips64/op_unused_41.S */ 1930/* File: mips64/unused.S */ 1931/* 1932 * Bail to reference interpreter to throw. 1933 */ 1934 b MterpFallback 1935 1936 1937/* ------------------------------ */ 1938 .balign 128 1939.L_op_unused_42: /* 0x42 */ 1940/* File: mips64/op_unused_42.S */ 1941/* File: mips64/unused.S */ 1942/* 1943 * Bail to reference interpreter to throw. 1944 */ 1945 b MterpFallback 1946 1947 1948/* ------------------------------ */ 1949 .balign 128 1950.L_op_unused_43: /* 0x43 */ 1951/* File: mips64/op_unused_43.S */ 1952/* File: mips64/unused.S */ 1953/* 1954 * Bail to reference interpreter to throw. 1955 */ 1956 b MterpFallback 1957 1958 1959/* ------------------------------ */ 1960 .balign 128 1961.L_op_aget: /* 0x44 */ 1962/* File: mips64/op_aget.S */ 1963 /* 1964 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1965 * 1966 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1967 * 1968 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1969 * If this changes, specialize. 1970 */ 1971 /* op vAA, vBB, vCC */ 1972 lbu a2, 2(rPC) # a2 <- BB 1973 lbu a3, 3(rPC) # a3 <- CC 1974 srl a4, rINST, 8 # a4 <- AA 1975 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1976 GET_VREG a1, a3 # a1 <- vCC (requested index) 1977 beqz a0, common_errNullObject # bail if null array object 1978 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1979 .if 2 1980 # [d]lsa does not support shift count of 0. 1981 dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width 1982 .else 1983 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1984 .endif 1985 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1986 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1987 lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1988 GET_INST_OPCODE v0 # extract opcode from rINST 1989 SET_VREG a2, a4 # vAA <- a2 1990 GOTO_OPCODE v0 # jump to next instruction 1991 1992/* ------------------------------ */ 1993 .balign 128 1994.L_op_aget_wide: /* 0x45 */ 1995/* File: mips64/op_aget_wide.S */ 1996 /* 1997 * Array get, 64 bits. vAA <- vBB[vCC]. 1998 * 1999 */ 2000 /* aget-wide vAA, vBB, vCC */ 2001 lbu a2, 2(rPC) # a2 <- BB 2002 lbu a3, 3(rPC) # a3 <- CC 2003 srl a4, rINST, 8 # a4 <- AA 2004 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2005 GET_VREG a1, a3 # a1 <- vCC (requested index) 2006 beqz a0, common_errNullObject # bail if null array object 2007 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2008 dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width 2009 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2010 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2011 lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) 2012 lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) 2013 dinsu a2, a3, 32, 32 # a2 <- vBB[vCC] 2014 GET_INST_OPCODE v0 # extract opcode from rINST 2015 SET_VREG_WIDE a2, a4 # vAA <- a2 2016 GOTO_OPCODE v0 # jump to next instruction 2017 2018/* ------------------------------ */ 2019 .balign 128 2020.L_op_aget_object: /* 0x46 */ 2021/* File: mips64/op_aget_object.S */ 2022 /* 2023 * Array object get. vAA <- vBB[vCC]. 2024 * 2025 * for: aget-object 2026 */ 2027 /* op vAA, vBB, vCC */ 2028 .extern artAGetObjectFromMterp 2029 lbu a2, 2(rPC) # a2 <- BB 2030 lbu a3, 3(rPC) # a3 <- CC 2031 EXPORT_PC 2032 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2033 GET_VREG a1, a3 # a1 <- vCC (requested index) 2034 jal artAGetObjectFromMterp # (array, index) 2035 ld a1, THREAD_EXCEPTION_OFFSET(rSELF) 2036 srl a4, rINST, 8 # a4 <- AA 2037 PREFETCH_INST 2 2038 bnez a1, MterpException 2039 SET_VREG_OBJECT v0, a4 # vAA <- v0 2040 ADVANCE 2 2041 GET_INST_OPCODE v0 # extract opcode from rINST 2042 GOTO_OPCODE v0 # jump to next instruction 2043 2044/* ------------------------------ */ 2045 .balign 128 2046.L_op_aget_boolean: /* 0x47 */ 2047/* File: mips64/op_aget_boolean.S */ 2048/* File: mips64/op_aget.S */ 2049 /* 2050 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2051 * 2052 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2053 * 2054 * NOTE: assumes data offset for arrays is the same for all non-wide types. 2055 * If this changes, specialize. 2056 */ 2057 /* op vAA, vBB, vCC */ 2058 lbu a2, 2(rPC) # a2 <- BB 2059 lbu a3, 3(rPC) # a3 <- CC 2060 srl a4, rINST, 8 # a4 <- AA 2061 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2062 GET_VREG a1, a3 # a1 <- vCC (requested index) 2063 beqz a0, common_errNullObject # bail if null array object 2064 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2065 .if 0 2066 # [d]lsa does not support shift count of 0. 2067 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 2068 .else 2069 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2070 .endif 2071 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2072 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2073 lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2074 GET_INST_OPCODE v0 # extract opcode from rINST 2075 SET_VREG a2, a4 # vAA <- a2 2076 GOTO_OPCODE v0 # jump to next instruction 2077 2078 2079/* ------------------------------ */ 2080 .balign 128 2081.L_op_aget_byte: /* 0x48 */ 2082/* File: mips64/op_aget_byte.S */ 2083/* File: mips64/op_aget.S */ 2084 /* 2085 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2086 * 2087 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2088 * 2089 * NOTE: assumes data offset for arrays is the same for all non-wide types. 2090 * If this changes, specialize. 2091 */ 2092 /* op vAA, vBB, vCC */ 2093 lbu a2, 2(rPC) # a2 <- BB 2094 lbu a3, 3(rPC) # a3 <- CC 2095 srl a4, rINST, 8 # a4 <- AA 2096 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2097 GET_VREG a1, a3 # a1 <- vCC (requested index) 2098 beqz a0, common_errNullObject # bail if null array object 2099 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2100 .if 0 2101 # [d]lsa does not support shift count of 0. 2102 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 2103 .else 2104 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2105 .endif 2106 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2107 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2108 lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2109 GET_INST_OPCODE v0 # extract opcode from rINST 2110 SET_VREG a2, a4 # vAA <- a2 2111 GOTO_OPCODE v0 # jump to next instruction 2112 2113 2114/* ------------------------------ */ 2115 .balign 128 2116.L_op_aget_char: /* 0x49 */ 2117/* File: mips64/op_aget_char.S */ 2118/* File: mips64/op_aget.S */ 2119 /* 2120 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2121 * 2122 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2123 * 2124 * NOTE: assumes data offset for arrays is the same for all non-wide types. 2125 * If this changes, specialize. 2126 */ 2127 /* op vAA, vBB, vCC */ 2128 lbu a2, 2(rPC) # a2 <- BB 2129 lbu a3, 3(rPC) # a3 <- CC 2130 srl a4, rINST, 8 # a4 <- AA 2131 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2132 GET_VREG a1, a3 # a1 <- vCC (requested index) 2133 beqz a0, common_errNullObject # bail if null array object 2134 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2135 .if 1 2136 # [d]lsa does not support shift count of 0. 2137 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 2138 .else 2139 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2140 .endif 2141 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2142 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2143 lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2144 GET_INST_OPCODE v0 # extract opcode from rINST 2145 SET_VREG a2, a4 # vAA <- a2 2146 GOTO_OPCODE v0 # jump to next instruction 2147 2148 2149/* ------------------------------ */ 2150 .balign 128 2151.L_op_aget_short: /* 0x4a */ 2152/* File: mips64/op_aget_short.S */ 2153/* File: mips64/op_aget.S */ 2154 /* 2155 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2156 * 2157 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2158 * 2159 * NOTE: assumes data offset for arrays is the same for all non-wide types. 2160 * If this changes, specialize. 2161 */ 2162 /* op vAA, vBB, vCC */ 2163 lbu a2, 2(rPC) # a2 <- BB 2164 lbu a3, 3(rPC) # a3 <- CC 2165 srl a4, rINST, 8 # a4 <- AA 2166 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2167 GET_VREG a1, a3 # a1 <- vCC (requested index) 2168 beqz a0, common_errNullObject # bail if null array object 2169 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2170 .if 1 2171 # [d]lsa does not support shift count of 0. 2172 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 2173 .else 2174 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2175 .endif 2176 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2177 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2178 lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2179 GET_INST_OPCODE v0 # extract opcode from rINST 2180 SET_VREG a2, a4 # vAA <- a2 2181 GOTO_OPCODE v0 # jump to next instruction 2182 2183 2184/* ------------------------------ */ 2185 .balign 128 2186.L_op_aput: /* 0x4b */ 2187/* File: mips64/op_aput.S */ 2188 /* 2189 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2190 * 2191 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2192 * 2193 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2194 * If this changes, specialize. 2195 */ 2196 /* op vAA, vBB, vCC */ 2197 lbu a2, 2(rPC) # a2 <- BB 2198 lbu a3, 3(rPC) # a3 <- CC 2199 srl a4, rINST, 8 # a4 <- AA 2200 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2201 GET_VREG a1, a3 # a1 <- vCC (requested index) 2202 beqz a0, common_errNullObject # bail if null array object 2203 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2204 .if 2 2205 # [d]lsa does not support shift count of 0. 2206 dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width 2207 .else 2208 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2209 .endif 2210 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2211 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2212 GET_VREG a2, a4 # a2 <- vAA 2213 GET_INST_OPCODE v0 # extract opcode from rINST 2214 sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2215 GOTO_OPCODE v0 # jump to next instruction 2216 2217/* ------------------------------ */ 2218 .balign 128 2219.L_op_aput_wide: /* 0x4c */ 2220/* File: mips64/op_aput_wide.S */ 2221 /* 2222 * Array put, 64 bits. vBB[vCC] <- vAA. 2223 * 2224 */ 2225 /* aput-wide vAA, vBB, vCC */ 2226 lbu a2, 2(rPC) # a2 <- BB 2227 lbu a3, 3(rPC) # a3 <- CC 2228 srl a4, rINST, 8 # a4 <- AA 2229 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2230 GET_VREG a1, a3 # a1 <- vCC (requested index) 2231 beqz a0, common_errNullObject # bail if null array object 2232 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2233 dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width 2234 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2235 GET_VREG_WIDE a2, a4 # a2 <- vAA 2236 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2237 GET_INST_OPCODE v0 # extract opcode from rINST 2238 sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) 2239 dsrl32 a2, a2, 0 2240 sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2 2241 GOTO_OPCODE v0 # jump to next instruction 2242 2243/* ------------------------------ */ 2244 .balign 128 2245.L_op_aput_object: /* 0x4d */ 2246/* File: mips64/op_aput_object.S */ 2247 /* 2248 * Store an object into an array. vBB[vCC] <- vAA. 2249 */ 2250 /* op vAA, vBB, vCC */ 2251 .extern MterpAputObject 2252 EXPORT_PC 2253 daddu a0, rFP, OFF_FP_SHADOWFRAME 2254 move a1, rPC 2255 move a2, rINST 2256 jal MterpAputObject 2257 beqzc v0, MterpPossibleException 2258 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2259 GET_INST_OPCODE v0 # extract opcode from rINST 2260 GOTO_OPCODE v0 # jump to next instruction 2261 2262/* ------------------------------ */ 2263 .balign 128 2264.L_op_aput_boolean: /* 0x4e */ 2265/* File: mips64/op_aput_boolean.S */ 2266/* File: mips64/op_aput.S */ 2267 /* 2268 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2269 * 2270 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2271 * 2272 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2273 * If this changes, specialize. 2274 */ 2275 /* op vAA, vBB, vCC */ 2276 lbu a2, 2(rPC) # a2 <- BB 2277 lbu a3, 3(rPC) # a3 <- CC 2278 srl a4, rINST, 8 # a4 <- AA 2279 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2280 GET_VREG a1, a3 # a1 <- vCC (requested index) 2281 beqz a0, common_errNullObject # bail if null array object 2282 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2283 .if 0 2284 # [d]lsa does not support shift count of 0. 2285 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 2286 .else 2287 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2288 .endif 2289 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2290 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2291 GET_VREG a2, a4 # a2 <- vAA 2292 GET_INST_OPCODE v0 # extract opcode from rINST 2293 sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2294 GOTO_OPCODE v0 # jump to next instruction 2295 2296 2297/* ------------------------------ */ 2298 .balign 128 2299.L_op_aput_byte: /* 0x4f */ 2300/* File: mips64/op_aput_byte.S */ 2301/* File: mips64/op_aput.S */ 2302 /* 2303 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2304 * 2305 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2306 * 2307 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2308 * If this changes, specialize. 2309 */ 2310 /* op vAA, vBB, vCC */ 2311 lbu a2, 2(rPC) # a2 <- BB 2312 lbu a3, 3(rPC) # a3 <- CC 2313 srl a4, rINST, 8 # a4 <- AA 2314 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2315 GET_VREG a1, a3 # a1 <- vCC (requested index) 2316 beqz a0, common_errNullObject # bail if null array object 2317 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2318 .if 0 2319 # [d]lsa does not support shift count of 0. 2320 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 2321 .else 2322 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2323 .endif 2324 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2325 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2326 GET_VREG a2, a4 # a2 <- vAA 2327 GET_INST_OPCODE v0 # extract opcode from rINST 2328 sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2329 GOTO_OPCODE v0 # jump to next instruction 2330 2331 2332/* ------------------------------ */ 2333 .balign 128 2334.L_op_aput_char: /* 0x50 */ 2335/* File: mips64/op_aput_char.S */ 2336/* File: mips64/op_aput.S */ 2337 /* 2338 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2339 * 2340 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2341 * 2342 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2343 * If this changes, specialize. 2344 */ 2345 /* op vAA, vBB, vCC */ 2346 lbu a2, 2(rPC) # a2 <- BB 2347 lbu a3, 3(rPC) # a3 <- CC 2348 srl a4, rINST, 8 # a4 <- AA 2349 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2350 GET_VREG a1, a3 # a1 <- vCC (requested index) 2351 beqz a0, common_errNullObject # bail if null array object 2352 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2353 .if 1 2354 # [d]lsa does not support shift count of 0. 2355 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 2356 .else 2357 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2358 .endif 2359 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2360 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2361 GET_VREG a2, a4 # a2 <- vAA 2362 GET_INST_OPCODE v0 # extract opcode from rINST 2363 sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2364 GOTO_OPCODE v0 # jump to next instruction 2365 2366 2367/* ------------------------------ */ 2368 .balign 128 2369.L_op_aput_short: /* 0x51 */ 2370/* File: mips64/op_aput_short.S */ 2371/* File: mips64/op_aput.S */ 2372 /* 2373 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2374 * 2375 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2376 * 2377 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2378 * If this changes, specialize. 2379 */ 2380 /* op vAA, vBB, vCC */ 2381 lbu a2, 2(rPC) # a2 <- BB 2382 lbu a3, 3(rPC) # a3 <- CC 2383 srl a4, rINST, 8 # a4 <- AA 2384 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2385 GET_VREG a1, a3 # a1 <- vCC (requested index) 2386 beqz a0, common_errNullObject # bail if null array object 2387 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2388 .if 1 2389 # [d]lsa does not support shift count of 0. 2390 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 2391 .else 2392 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2393 .endif 2394 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2395 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2396 GET_VREG a2, a4 # a2 <- vAA 2397 GET_INST_OPCODE v0 # extract opcode from rINST 2398 sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2399 GOTO_OPCODE v0 # jump to next instruction 2400 2401 2402/* ------------------------------ */ 2403 .balign 128 2404.L_op_iget: /* 0x52 */ 2405/* File: mips64/op_iget.S */ 2406 /* 2407 * General instance field get. 2408 * 2409 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2410 */ 2411 .extern artGet32InstanceFromCode 2412 EXPORT_PC 2413 lhu a0, 2(rPC) # a0 <- field ref CCCC 2414 srl a1, rINST, 12 # a1 <- B 2415 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2416 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2417 move a3, rSELF # a3 <- self 2418 jal artGet32InstanceFromCode 2419 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2420 ext a2, rINST, 8, 4 # a2 <- A 2421 PREFETCH_INST 2 2422 bnez a3, MterpPossibleException # bail out 2423 .if 0 2424 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2425 .else 2426 SET_VREG v0, a2 # fp[A] <- v0 2427 .endif 2428 ADVANCE 2 2429 GET_INST_OPCODE v0 # extract opcode from rINST 2430 GOTO_OPCODE v0 # jump to next instruction 2431 2432/* ------------------------------ */ 2433 .balign 128 2434.L_op_iget_wide: /* 0x53 */ 2435/* File: mips64/op_iget_wide.S */ 2436 /* 2437 * 64-bit instance field get. 2438 * 2439 * for: iget-wide 2440 */ 2441 .extern artGet64InstanceFromCode 2442 EXPORT_PC 2443 lhu a0, 2(rPC) # a0 <- field ref CCCC 2444 srl a1, rINST, 12 # a1 <- B 2445 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2446 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2447 move a3, rSELF # a3 <- self 2448 jal artGet64InstanceFromCode 2449 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2450 ext a2, rINST, 8, 4 # a2 <- A 2451 PREFETCH_INST 2 2452 bnez a3, MterpPossibleException # bail out 2453 SET_VREG_WIDE v0, a2 # fp[A] <- v0 2454 ADVANCE 2 2455 GET_INST_OPCODE v0 # extract opcode from rINST 2456 GOTO_OPCODE v0 # jump to next instruction 2457 2458/* ------------------------------ */ 2459 .balign 128 2460.L_op_iget_object: /* 0x54 */ 2461/* File: mips64/op_iget_object.S */ 2462/* File: mips64/op_iget.S */ 2463 /* 2464 * General instance field get. 2465 * 2466 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2467 */ 2468 .extern artGetObjInstanceFromCode 2469 EXPORT_PC 2470 lhu a0, 2(rPC) # a0 <- field ref CCCC 2471 srl a1, rINST, 12 # a1 <- B 2472 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2473 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2474 move a3, rSELF # a3 <- self 2475 jal artGetObjInstanceFromCode 2476 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2477 ext a2, rINST, 8, 4 # a2 <- A 2478 PREFETCH_INST 2 2479 bnez a3, MterpPossibleException # bail out 2480 .if 1 2481 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2482 .else 2483 SET_VREG v0, a2 # fp[A] <- v0 2484 .endif 2485 ADVANCE 2 2486 GET_INST_OPCODE v0 # extract opcode from rINST 2487 GOTO_OPCODE v0 # jump to next instruction 2488 2489 2490/* ------------------------------ */ 2491 .balign 128 2492.L_op_iget_boolean: /* 0x55 */ 2493/* File: mips64/op_iget_boolean.S */ 2494/* File: mips64/op_iget.S */ 2495 /* 2496 * General instance field get. 2497 * 2498 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2499 */ 2500 .extern artGetBooleanInstanceFromCode 2501 EXPORT_PC 2502 lhu a0, 2(rPC) # a0 <- field ref CCCC 2503 srl a1, rINST, 12 # a1 <- B 2504 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2505 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2506 move a3, rSELF # a3 <- self 2507 jal artGetBooleanInstanceFromCode 2508 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2509 ext a2, rINST, 8, 4 # a2 <- A 2510 PREFETCH_INST 2 2511 bnez a3, MterpPossibleException # bail out 2512 .if 0 2513 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2514 .else 2515 SET_VREG v0, a2 # fp[A] <- v0 2516 .endif 2517 ADVANCE 2 2518 GET_INST_OPCODE v0 # extract opcode from rINST 2519 GOTO_OPCODE v0 # jump to next instruction 2520 2521 2522/* ------------------------------ */ 2523 .balign 128 2524.L_op_iget_byte: /* 0x56 */ 2525/* File: mips64/op_iget_byte.S */ 2526/* File: mips64/op_iget.S */ 2527 /* 2528 * General instance field get. 2529 * 2530 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2531 */ 2532 .extern artGetByteInstanceFromCode 2533 EXPORT_PC 2534 lhu a0, 2(rPC) # a0 <- field ref CCCC 2535 srl a1, rINST, 12 # a1 <- B 2536 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2537 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2538 move a3, rSELF # a3 <- self 2539 jal artGetByteInstanceFromCode 2540 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2541 ext a2, rINST, 8, 4 # a2 <- A 2542 PREFETCH_INST 2 2543 bnez a3, MterpPossibleException # bail out 2544 .if 0 2545 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2546 .else 2547 SET_VREG v0, a2 # fp[A] <- v0 2548 .endif 2549 ADVANCE 2 2550 GET_INST_OPCODE v0 # extract opcode from rINST 2551 GOTO_OPCODE v0 # jump to next instruction 2552 2553 2554/* ------------------------------ */ 2555 .balign 128 2556.L_op_iget_char: /* 0x57 */ 2557/* File: mips64/op_iget_char.S */ 2558/* File: mips64/op_iget.S */ 2559 /* 2560 * General instance field get. 2561 * 2562 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2563 */ 2564 .extern artGetCharInstanceFromCode 2565 EXPORT_PC 2566 lhu a0, 2(rPC) # a0 <- field ref CCCC 2567 srl a1, rINST, 12 # a1 <- B 2568 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2569 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2570 move a3, rSELF # a3 <- self 2571 jal artGetCharInstanceFromCode 2572 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2573 ext a2, rINST, 8, 4 # a2 <- A 2574 PREFETCH_INST 2 2575 bnez a3, MterpPossibleException # bail out 2576 .if 0 2577 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2578 .else 2579 SET_VREG v0, a2 # fp[A] <- v0 2580 .endif 2581 ADVANCE 2 2582 GET_INST_OPCODE v0 # extract opcode from rINST 2583 GOTO_OPCODE v0 # jump to next instruction 2584 2585 2586/* ------------------------------ */ 2587 .balign 128 2588.L_op_iget_short: /* 0x58 */ 2589/* File: mips64/op_iget_short.S */ 2590/* File: mips64/op_iget.S */ 2591 /* 2592 * General instance field get. 2593 * 2594 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2595 */ 2596 .extern artGetShortInstanceFromCode 2597 EXPORT_PC 2598 lhu a0, 2(rPC) # a0 <- field ref CCCC 2599 srl a1, rINST, 12 # a1 <- B 2600 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2601 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2602 move a3, rSELF # a3 <- self 2603 jal artGetShortInstanceFromCode 2604 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2605 ext a2, rINST, 8, 4 # a2 <- A 2606 PREFETCH_INST 2 2607 bnez a3, MterpPossibleException # bail out 2608 .if 0 2609 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2610 .else 2611 SET_VREG v0, a2 # fp[A] <- v0 2612 .endif 2613 ADVANCE 2 2614 GET_INST_OPCODE v0 # extract opcode from rINST 2615 GOTO_OPCODE v0 # jump to next instruction 2616 2617 2618/* ------------------------------ */ 2619 .balign 128 2620.L_op_iput: /* 0x59 */ 2621/* File: mips64/op_iput.S */ 2622 /* 2623 * General 32-bit instance field put. 2624 * 2625 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2626 */ 2627 /* op vA, vB, field//CCCC */ 2628 .extern artSet32InstanceFromMterp 2629 EXPORT_PC 2630 lhu a0, 2(rPC) # a0 <- field ref CCCC 2631 srl a1, rINST, 12 # a1 <- B 2632 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2633 ext a2, rINST, 8, 4 # a2 <- A 2634 GET_VREG a2, a2 # a2 <- fp[A] 2635 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2636 PREFETCH_INST 2 2637 jal artSet32InstanceFromMterp 2638 bnez v0, MterpPossibleException # bail out 2639 ADVANCE 2 2640 GET_INST_OPCODE v0 # extract opcode from rINST 2641 GOTO_OPCODE v0 # jump to next instruction 2642 2643/* ------------------------------ */ 2644 .balign 128 2645.L_op_iput_wide: /* 0x5a */ 2646/* File: mips64/op_iput_wide.S */ 2647 /* iput-wide vA, vB, field//CCCC */ 2648 .extern artSet64InstanceFromMterp 2649 EXPORT_PC 2650 lhu a0, 2(rPC) # a0 <- field ref CCCC 2651 srl a1, rINST, 12 # a1 <- B 2652 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2653 ext a2, rINST, 8, 4 # a2 <- A 2654 dlsa a2, a2, rFP, 2 # a2 <- &fp[A] 2655 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2656 PREFETCH_INST 2 2657 jal artSet64InstanceFromMterp 2658 bnez v0, MterpPossibleException # bail out 2659 ADVANCE 2 2660 GET_INST_OPCODE v0 # extract opcode from rINST 2661 GOTO_OPCODE v0 # jump to next instruction 2662 2663/* ------------------------------ */ 2664 .balign 128 2665.L_op_iput_object: /* 0x5b */ 2666/* File: mips64/op_iput_object.S */ 2667 .extern MterpIputObject 2668 EXPORT_PC 2669 daddu a0, rFP, OFF_FP_SHADOWFRAME 2670 move a1, rPC 2671 move a2, rINST 2672 move a3, rSELF 2673 jal MterpIputObject 2674 beqzc v0, MterpException 2675 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2676 GET_INST_OPCODE v0 # extract opcode from rINST 2677 GOTO_OPCODE v0 # jump to next instruction 2678 2679/* ------------------------------ */ 2680 .balign 128 2681.L_op_iput_boolean: /* 0x5c */ 2682/* File: mips64/op_iput_boolean.S */ 2683/* File: mips64/op_iput.S */ 2684 /* 2685 * General 32-bit instance field put. 2686 * 2687 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2688 */ 2689 /* op vA, vB, field//CCCC */ 2690 .extern artSet8InstanceFromMterp 2691 EXPORT_PC 2692 lhu a0, 2(rPC) # a0 <- field ref CCCC 2693 srl a1, rINST, 12 # a1 <- B 2694 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2695 ext a2, rINST, 8, 4 # a2 <- A 2696 GET_VREG a2, a2 # a2 <- fp[A] 2697 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2698 PREFETCH_INST 2 2699 jal artSet8InstanceFromMterp 2700 bnez v0, MterpPossibleException # bail out 2701 ADVANCE 2 2702 GET_INST_OPCODE v0 # extract opcode from rINST 2703 GOTO_OPCODE v0 # jump to next instruction 2704 2705 2706/* ------------------------------ */ 2707 .balign 128 2708.L_op_iput_byte: /* 0x5d */ 2709/* File: mips64/op_iput_byte.S */ 2710/* File: mips64/op_iput.S */ 2711 /* 2712 * General 32-bit instance field put. 2713 * 2714 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2715 */ 2716 /* op vA, vB, field//CCCC */ 2717 .extern artSet8InstanceFromMterp 2718 EXPORT_PC 2719 lhu a0, 2(rPC) # a0 <- field ref CCCC 2720 srl a1, rINST, 12 # a1 <- B 2721 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2722 ext a2, rINST, 8, 4 # a2 <- A 2723 GET_VREG a2, a2 # a2 <- fp[A] 2724 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2725 PREFETCH_INST 2 2726 jal artSet8InstanceFromMterp 2727 bnez v0, MterpPossibleException # bail out 2728 ADVANCE 2 2729 GET_INST_OPCODE v0 # extract opcode from rINST 2730 GOTO_OPCODE v0 # jump to next instruction 2731 2732 2733/* ------------------------------ */ 2734 .balign 128 2735.L_op_iput_char: /* 0x5e */ 2736/* File: mips64/op_iput_char.S */ 2737/* File: mips64/op_iput.S */ 2738 /* 2739 * General 32-bit instance field put. 2740 * 2741 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2742 */ 2743 /* op vA, vB, field//CCCC */ 2744 .extern artSet16InstanceFromMterp 2745 EXPORT_PC 2746 lhu a0, 2(rPC) # a0 <- field ref CCCC 2747 srl a1, rINST, 12 # a1 <- B 2748 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2749 ext a2, rINST, 8, 4 # a2 <- A 2750 GET_VREG a2, a2 # a2 <- fp[A] 2751 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2752 PREFETCH_INST 2 2753 jal artSet16InstanceFromMterp 2754 bnez v0, MterpPossibleException # bail out 2755 ADVANCE 2 2756 GET_INST_OPCODE v0 # extract opcode from rINST 2757 GOTO_OPCODE v0 # jump to next instruction 2758 2759 2760/* ------------------------------ */ 2761 .balign 128 2762.L_op_iput_short: /* 0x5f */ 2763/* File: mips64/op_iput_short.S */ 2764/* File: mips64/op_iput.S */ 2765 /* 2766 * General 32-bit instance field put. 2767 * 2768 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2769 */ 2770 /* op vA, vB, field//CCCC */ 2771 .extern artSet16InstanceFromMterp 2772 EXPORT_PC 2773 lhu a0, 2(rPC) # a0 <- field ref CCCC 2774 srl a1, rINST, 12 # a1 <- B 2775 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2776 ext a2, rINST, 8, 4 # a2 <- A 2777 GET_VREG a2, a2 # a2 <- fp[A] 2778 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2779 PREFETCH_INST 2 2780 jal artSet16InstanceFromMterp 2781 bnez v0, MterpPossibleException # bail out 2782 ADVANCE 2 2783 GET_INST_OPCODE v0 # extract opcode from rINST 2784 GOTO_OPCODE v0 # jump to next instruction 2785 2786 2787/* ------------------------------ */ 2788 .balign 128 2789.L_op_sget: /* 0x60 */ 2790/* File: mips64/op_sget.S */ 2791 /* 2792 * General SGET handler wrapper. 2793 * 2794 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2795 */ 2796 /* op vAA, field//BBBB */ 2797 .extern artGet32StaticFromCode 2798 EXPORT_PC 2799 lhu a0, 2(rPC) # a0 <- field ref BBBB 2800 ld a1, OFF_FP_METHOD(rFP) 2801 move a2, rSELF 2802 jal artGet32StaticFromCode 2803 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2804 srl a2, rINST, 8 # a2 <- AA 2805 2806 PREFETCH_INST 2 2807 bnez a3, MterpException # bail out 2808 .if 0 2809 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2810 .else 2811 SET_VREG v0, a2 # fp[AA] <- v0 2812 .endif 2813 ADVANCE 2 2814 GET_INST_OPCODE v0 # extract opcode from rINST 2815 GOTO_OPCODE v0 2816 2817/* ------------------------------ */ 2818 .balign 128 2819.L_op_sget_wide: /* 0x61 */ 2820/* File: mips64/op_sget_wide.S */ 2821 /* 2822 * SGET_WIDE handler wrapper. 2823 * 2824 */ 2825 /* sget-wide vAA, field//BBBB */ 2826 .extern artGet64StaticFromCode 2827 EXPORT_PC 2828 lhu a0, 2(rPC) # a0 <- field ref BBBB 2829 ld a1, OFF_FP_METHOD(rFP) 2830 move a2, rSELF 2831 jal artGet64StaticFromCode 2832 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2833 srl a4, rINST, 8 # a4 <- AA 2834 bnez a3, MterpException # bail out 2835 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2836 SET_VREG_WIDE v0, a4 2837 GET_INST_OPCODE v0 # extract opcode from rINST 2838 GOTO_OPCODE v0 # jump to next instruction 2839 2840/* ------------------------------ */ 2841 .balign 128 2842.L_op_sget_object: /* 0x62 */ 2843/* File: mips64/op_sget_object.S */ 2844/* File: mips64/op_sget.S */ 2845 /* 2846 * General SGET handler wrapper. 2847 * 2848 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2849 */ 2850 /* op vAA, field//BBBB */ 2851 .extern artGetObjStaticFromCode 2852 EXPORT_PC 2853 lhu a0, 2(rPC) # a0 <- field ref BBBB 2854 ld a1, OFF_FP_METHOD(rFP) 2855 move a2, rSELF 2856 jal artGetObjStaticFromCode 2857 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2858 srl a2, rINST, 8 # a2 <- AA 2859 2860 PREFETCH_INST 2 2861 bnez a3, MterpException # bail out 2862 .if 1 2863 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2864 .else 2865 SET_VREG v0, a2 # fp[AA] <- v0 2866 .endif 2867 ADVANCE 2 2868 GET_INST_OPCODE v0 # extract opcode from rINST 2869 GOTO_OPCODE v0 2870 2871 2872/* ------------------------------ */ 2873 .balign 128 2874.L_op_sget_boolean: /* 0x63 */ 2875/* File: mips64/op_sget_boolean.S */ 2876/* File: mips64/op_sget.S */ 2877 /* 2878 * General SGET handler wrapper. 2879 * 2880 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2881 */ 2882 /* op vAA, field//BBBB */ 2883 .extern artGetBooleanStaticFromCode 2884 EXPORT_PC 2885 lhu a0, 2(rPC) # a0 <- field ref BBBB 2886 ld a1, OFF_FP_METHOD(rFP) 2887 move a2, rSELF 2888 jal artGetBooleanStaticFromCode 2889 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2890 srl a2, rINST, 8 # a2 <- AA 2891 and v0, v0, 0xff 2892 PREFETCH_INST 2 2893 bnez a3, MterpException # bail out 2894 .if 0 2895 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2896 .else 2897 SET_VREG v0, a2 # fp[AA] <- v0 2898 .endif 2899 ADVANCE 2 2900 GET_INST_OPCODE v0 # extract opcode from rINST 2901 GOTO_OPCODE v0 2902 2903 2904/* ------------------------------ */ 2905 .balign 128 2906.L_op_sget_byte: /* 0x64 */ 2907/* File: mips64/op_sget_byte.S */ 2908/* File: mips64/op_sget.S */ 2909 /* 2910 * General SGET handler wrapper. 2911 * 2912 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2913 */ 2914 /* op vAA, field//BBBB */ 2915 .extern artGetByteStaticFromCode 2916 EXPORT_PC 2917 lhu a0, 2(rPC) # a0 <- field ref BBBB 2918 ld a1, OFF_FP_METHOD(rFP) 2919 move a2, rSELF 2920 jal artGetByteStaticFromCode 2921 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2922 srl a2, rINST, 8 # a2 <- AA 2923 seb v0, v0 2924 PREFETCH_INST 2 2925 bnez a3, MterpException # bail out 2926 .if 0 2927 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2928 .else 2929 SET_VREG v0, a2 # fp[AA] <- v0 2930 .endif 2931 ADVANCE 2 2932 GET_INST_OPCODE v0 # extract opcode from rINST 2933 GOTO_OPCODE v0 2934 2935 2936/* ------------------------------ */ 2937 .balign 128 2938.L_op_sget_char: /* 0x65 */ 2939/* File: mips64/op_sget_char.S */ 2940/* File: mips64/op_sget.S */ 2941 /* 2942 * General SGET handler wrapper. 2943 * 2944 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2945 */ 2946 /* op vAA, field//BBBB */ 2947 .extern artGetCharStaticFromCode 2948 EXPORT_PC 2949 lhu a0, 2(rPC) # a0 <- field ref BBBB 2950 ld a1, OFF_FP_METHOD(rFP) 2951 move a2, rSELF 2952 jal artGetCharStaticFromCode 2953 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2954 srl a2, rINST, 8 # a2 <- AA 2955 and v0, v0, 0xffff 2956 PREFETCH_INST 2 2957 bnez a3, MterpException # bail out 2958 .if 0 2959 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2960 .else 2961 SET_VREG v0, a2 # fp[AA] <- v0 2962 .endif 2963 ADVANCE 2 2964 GET_INST_OPCODE v0 # extract opcode from rINST 2965 GOTO_OPCODE v0 2966 2967 2968/* ------------------------------ */ 2969 .balign 128 2970.L_op_sget_short: /* 0x66 */ 2971/* File: mips64/op_sget_short.S */ 2972/* File: mips64/op_sget.S */ 2973 /* 2974 * General SGET handler wrapper. 2975 * 2976 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2977 */ 2978 /* op vAA, field//BBBB */ 2979 .extern artGetShortStaticFromCode 2980 EXPORT_PC 2981 lhu a0, 2(rPC) # a0 <- field ref BBBB 2982 ld a1, OFF_FP_METHOD(rFP) 2983 move a2, rSELF 2984 jal artGetShortStaticFromCode 2985 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2986 srl a2, rINST, 8 # a2 <- AA 2987 seh v0, v0 2988 PREFETCH_INST 2 2989 bnez a3, MterpException # bail out 2990 .if 0 2991 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2992 .else 2993 SET_VREG v0, a2 # fp[AA] <- v0 2994 .endif 2995 ADVANCE 2 2996 GET_INST_OPCODE v0 # extract opcode from rINST 2997 GOTO_OPCODE v0 2998 2999 3000/* ------------------------------ */ 3001 .balign 128 3002.L_op_sput: /* 0x67 */ 3003/* File: mips64/op_sput.S */ 3004 /* 3005 * General SPUT handler wrapper. 3006 * 3007 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3008 */ 3009 /* op vAA, field//BBBB */ 3010 .extern artSet32StaticFromCode 3011 EXPORT_PC 3012 lhu a0, 2(rPC) # a0 <- field ref BBBB 3013 srl a3, rINST, 8 # a3 <- AA 3014 GET_VREG a1, a3 # a1 <- fp[AA] 3015 ld a2, OFF_FP_METHOD(rFP) 3016 move a3, rSELF 3017 PREFETCH_INST 2 # Get next inst, but don't advance rPC 3018 jal artSet32StaticFromCode 3019 bnezc v0, MterpException # 0 on success 3020 ADVANCE 2 # Past exception point - now advance rPC 3021 GET_INST_OPCODE v0 # extract opcode from rINST 3022 GOTO_OPCODE v0 # jump to next instruction 3023 3024/* ------------------------------ */ 3025 .balign 128 3026.L_op_sput_wide: /* 0x68 */ 3027/* File: mips64/op_sput_wide.S */ 3028 /* 3029 * SPUT_WIDE handler wrapper. 3030 * 3031 */ 3032 /* sput-wide vAA, field//BBBB */ 3033 .extern artSet64IndirectStaticFromMterp 3034 EXPORT_PC 3035 lhu a0, 2(rPC) # a0 <- field ref BBBB 3036 ld a1, OFF_FP_METHOD(rFP) 3037 srl a2, rINST, 8 # a2 <- AA 3038 dlsa a2, a2, rFP, 2 3039 move a3, rSELF 3040 PREFETCH_INST 2 # Get next inst, but don't advance rPC 3041 jal artSet64IndirectStaticFromMterp 3042 bnezc v0, MterpException # 0 on success, -1 on failure 3043 ADVANCE 2 # Past exception point - now advance rPC 3044 GET_INST_OPCODE v0 # extract opcode from rINST 3045 GOTO_OPCODE v0 # jump to next instruction 3046 3047/* ------------------------------ */ 3048 .balign 128 3049.L_op_sput_object: /* 0x69 */ 3050/* File: mips64/op_sput_object.S */ 3051 .extern MterpSputObject 3052 EXPORT_PC 3053 daddu a0, rFP, OFF_FP_SHADOWFRAME 3054 move a1, rPC 3055 move a2, rINST 3056 move a3, rSELF 3057 jal MterpSputObject 3058 beqzc v0, MterpException 3059 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 3060 GET_INST_OPCODE v0 # extract opcode from rINST 3061 GOTO_OPCODE v0 # jump to next instruction 3062 3063/* ------------------------------ */ 3064 .balign 128 3065.L_op_sput_boolean: /* 0x6a */ 3066/* File: mips64/op_sput_boolean.S */ 3067/* File: mips64/op_sput.S */ 3068 /* 3069 * General SPUT handler wrapper. 3070 * 3071 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3072 */ 3073 /* op vAA, field//BBBB */ 3074 .extern artSet8StaticFromCode 3075 EXPORT_PC 3076 lhu a0, 2(rPC) # a0 <- field ref BBBB 3077 srl a3, rINST, 8 # a3 <- AA 3078 GET_VREG a1, a3 # a1 <- fp[AA] 3079 ld a2, OFF_FP_METHOD(rFP) 3080 move a3, rSELF 3081 PREFETCH_INST 2 # Get next inst, but don't advance rPC 3082 jal artSet8StaticFromCode 3083 bnezc v0, MterpException # 0 on success 3084 ADVANCE 2 # Past exception point - now advance rPC 3085 GET_INST_OPCODE v0 # extract opcode from rINST 3086 GOTO_OPCODE v0 # jump to next instruction 3087 3088 3089/* ------------------------------ */ 3090 .balign 128 3091.L_op_sput_byte: /* 0x6b */ 3092/* File: mips64/op_sput_byte.S */ 3093/* File: mips64/op_sput.S */ 3094 /* 3095 * General SPUT handler wrapper. 3096 * 3097 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3098 */ 3099 /* op vAA, field//BBBB */ 3100 .extern artSet8StaticFromCode 3101 EXPORT_PC 3102 lhu a0, 2(rPC) # a0 <- field ref BBBB 3103 srl a3, rINST, 8 # a3 <- AA 3104 GET_VREG a1, a3 # a1 <- fp[AA] 3105 ld a2, OFF_FP_METHOD(rFP) 3106 move a3, rSELF 3107 PREFETCH_INST 2 # Get next inst, but don't advance rPC 3108 jal artSet8StaticFromCode 3109 bnezc v0, MterpException # 0 on success 3110 ADVANCE 2 # Past exception point - now advance rPC 3111 GET_INST_OPCODE v0 # extract opcode from rINST 3112 GOTO_OPCODE v0 # jump to next instruction 3113 3114 3115/* ------------------------------ */ 3116 .balign 128 3117.L_op_sput_char: /* 0x6c */ 3118/* File: mips64/op_sput_char.S */ 3119/* File: mips64/op_sput.S */ 3120 /* 3121 * General SPUT handler wrapper. 3122 * 3123 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3124 */ 3125 /* op vAA, field//BBBB */ 3126 .extern artSet16StaticFromCode 3127 EXPORT_PC 3128 lhu a0, 2(rPC) # a0 <- field ref BBBB 3129 srl a3, rINST, 8 # a3 <- AA 3130 GET_VREG a1, a3 # a1 <- fp[AA] 3131 ld a2, OFF_FP_METHOD(rFP) 3132 move a3, rSELF 3133 PREFETCH_INST 2 # Get next inst, but don't advance rPC 3134 jal artSet16StaticFromCode 3135 bnezc v0, MterpException # 0 on success 3136 ADVANCE 2 # Past exception point - now advance rPC 3137 GET_INST_OPCODE v0 # extract opcode from rINST 3138 GOTO_OPCODE v0 # jump to next instruction 3139 3140 3141/* ------------------------------ */ 3142 .balign 128 3143.L_op_sput_short: /* 0x6d */ 3144/* File: mips64/op_sput_short.S */ 3145/* File: mips64/op_sput.S */ 3146 /* 3147 * General SPUT handler wrapper. 3148 * 3149 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3150 */ 3151 /* op vAA, field//BBBB */ 3152 .extern artSet16StaticFromCode 3153 EXPORT_PC 3154 lhu a0, 2(rPC) # a0 <- field ref BBBB 3155 srl a3, rINST, 8 # a3 <- AA 3156 GET_VREG a1, a3 # a1 <- fp[AA] 3157 ld a2, OFF_FP_METHOD(rFP) 3158 move a3, rSELF 3159 PREFETCH_INST 2 # Get next inst, but don't advance rPC 3160 jal artSet16StaticFromCode 3161 bnezc v0, MterpException # 0 on success 3162 ADVANCE 2 # Past exception point - now advance rPC 3163 GET_INST_OPCODE v0 # extract opcode from rINST 3164 GOTO_OPCODE v0 # jump to next instruction 3165 3166 3167/* ------------------------------ */ 3168 .balign 128 3169.L_op_invoke_virtual: /* 0x6e */ 3170/* File: mips64/op_invoke_virtual.S */ 3171/* File: mips64/invoke.S */ 3172 /* 3173 * Generic invoke handler wrapper. 3174 */ 3175 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3176 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3177 .extern MterpInvokeVirtual 3178 .extern MterpShouldSwitchInterpreters 3179 EXPORT_PC 3180 move a0, rSELF 3181 daddu a1, rFP, OFF_FP_SHADOWFRAME 3182 move a2, rPC 3183 move a3, rINST 3184 jal MterpInvokeVirtual 3185 beqzc v0, MterpException 3186 FETCH_ADVANCE_INST 3 3187 jal MterpShouldSwitchInterpreters 3188 bnezc v0, MterpFallback 3189 GET_INST_OPCODE v0 3190 GOTO_OPCODE v0 3191 3192 /* 3193 * Handle a virtual method call. 3194 * 3195 * for: invoke-virtual, invoke-virtual/range 3196 */ 3197 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3198 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3199 3200/* ------------------------------ */ 3201 .balign 128 3202.L_op_invoke_super: /* 0x6f */ 3203/* File: mips64/op_invoke_super.S */ 3204/* File: mips64/invoke.S */ 3205 /* 3206 * Generic invoke handler wrapper. 3207 */ 3208 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3209 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3210 .extern MterpInvokeSuper 3211 .extern MterpShouldSwitchInterpreters 3212 EXPORT_PC 3213 move a0, rSELF 3214 daddu a1, rFP, OFF_FP_SHADOWFRAME 3215 move a2, rPC 3216 move a3, rINST 3217 jal MterpInvokeSuper 3218 beqzc v0, MterpException 3219 FETCH_ADVANCE_INST 3 3220 jal MterpShouldSwitchInterpreters 3221 bnezc v0, MterpFallback 3222 GET_INST_OPCODE v0 3223 GOTO_OPCODE v0 3224 3225 /* 3226 * Handle a "super" method call. 3227 * 3228 * for: invoke-super, invoke-super/range 3229 */ 3230 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3231 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3232 3233/* ------------------------------ */ 3234 .balign 128 3235.L_op_invoke_direct: /* 0x70 */ 3236/* File: mips64/op_invoke_direct.S */ 3237/* File: mips64/invoke.S */ 3238 /* 3239 * Generic invoke handler wrapper. 3240 */ 3241 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3242 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3243 .extern MterpInvokeDirect 3244 .extern MterpShouldSwitchInterpreters 3245 EXPORT_PC 3246 move a0, rSELF 3247 daddu a1, rFP, OFF_FP_SHADOWFRAME 3248 move a2, rPC 3249 move a3, rINST 3250 jal MterpInvokeDirect 3251 beqzc v0, MterpException 3252 FETCH_ADVANCE_INST 3 3253 jal MterpShouldSwitchInterpreters 3254 bnezc v0, MterpFallback 3255 GET_INST_OPCODE v0 3256 GOTO_OPCODE v0 3257 3258 3259/* ------------------------------ */ 3260 .balign 128 3261.L_op_invoke_static: /* 0x71 */ 3262/* File: mips64/op_invoke_static.S */ 3263/* File: mips64/invoke.S */ 3264 /* 3265 * Generic invoke handler wrapper. 3266 */ 3267 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3268 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3269 .extern MterpInvokeStatic 3270 .extern MterpShouldSwitchInterpreters 3271 EXPORT_PC 3272 move a0, rSELF 3273 daddu a1, rFP, OFF_FP_SHADOWFRAME 3274 move a2, rPC 3275 move a3, rINST 3276 jal MterpInvokeStatic 3277 beqzc v0, MterpException 3278 FETCH_ADVANCE_INST 3 3279 jal MterpShouldSwitchInterpreters 3280 bnezc v0, MterpFallback 3281 GET_INST_OPCODE v0 3282 GOTO_OPCODE v0 3283 3284 3285/* ------------------------------ */ 3286 .balign 128 3287.L_op_invoke_interface: /* 0x72 */ 3288/* File: mips64/op_invoke_interface.S */ 3289/* File: mips64/invoke.S */ 3290 /* 3291 * Generic invoke handler wrapper. 3292 */ 3293 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3294 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3295 .extern MterpInvokeInterface 3296 .extern MterpShouldSwitchInterpreters 3297 EXPORT_PC 3298 move a0, rSELF 3299 daddu a1, rFP, OFF_FP_SHADOWFRAME 3300 move a2, rPC 3301 move a3, rINST 3302 jal MterpInvokeInterface 3303 beqzc v0, MterpException 3304 FETCH_ADVANCE_INST 3 3305 jal MterpShouldSwitchInterpreters 3306 bnezc v0, MterpFallback 3307 GET_INST_OPCODE v0 3308 GOTO_OPCODE v0 3309 3310 /* 3311 * Handle an interface method call. 3312 * 3313 * for: invoke-interface, invoke-interface/range 3314 */ 3315 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3316 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3317 3318/* ------------------------------ */ 3319 .balign 128 3320.L_op_return_void_no_barrier: /* 0x73 */ 3321/* File: mips64/op_return_void_no_barrier.S */ 3322 .extern MterpSuspendCheck 3323 lw ra, THREAD_FLAGS_OFFSET(rSELF) 3324 move a0, rSELF 3325 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 3326 beqzc ra, 1f 3327 jal MterpSuspendCheck # (self) 33281: 3329 li a0, 0 3330 b MterpReturn 3331 3332/* ------------------------------ */ 3333 .balign 128 3334.L_op_invoke_virtual_range: /* 0x74 */ 3335/* File: mips64/op_invoke_virtual_range.S */ 3336/* File: mips64/invoke.S */ 3337 /* 3338 * Generic invoke handler wrapper. 3339 */ 3340 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3341 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3342 .extern MterpInvokeVirtualRange 3343 .extern MterpShouldSwitchInterpreters 3344 EXPORT_PC 3345 move a0, rSELF 3346 daddu a1, rFP, OFF_FP_SHADOWFRAME 3347 move a2, rPC 3348 move a3, rINST 3349 jal MterpInvokeVirtualRange 3350 beqzc v0, MterpException 3351 FETCH_ADVANCE_INST 3 3352 jal MterpShouldSwitchInterpreters 3353 bnezc v0, MterpFallback 3354 GET_INST_OPCODE v0 3355 GOTO_OPCODE v0 3356 3357 3358/* ------------------------------ */ 3359 .balign 128 3360.L_op_invoke_super_range: /* 0x75 */ 3361/* File: mips64/op_invoke_super_range.S */ 3362/* File: mips64/invoke.S */ 3363 /* 3364 * Generic invoke handler wrapper. 3365 */ 3366 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3367 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3368 .extern MterpInvokeSuperRange 3369 .extern MterpShouldSwitchInterpreters 3370 EXPORT_PC 3371 move a0, rSELF 3372 daddu a1, rFP, OFF_FP_SHADOWFRAME 3373 move a2, rPC 3374 move a3, rINST 3375 jal MterpInvokeSuperRange 3376 beqzc v0, MterpException 3377 FETCH_ADVANCE_INST 3 3378 jal MterpShouldSwitchInterpreters 3379 bnezc v0, MterpFallback 3380 GET_INST_OPCODE v0 3381 GOTO_OPCODE v0 3382 3383 3384/* ------------------------------ */ 3385 .balign 128 3386.L_op_invoke_direct_range: /* 0x76 */ 3387/* File: mips64/op_invoke_direct_range.S */ 3388/* File: mips64/invoke.S */ 3389 /* 3390 * Generic invoke handler wrapper. 3391 */ 3392 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3393 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3394 .extern MterpInvokeDirectRange 3395 .extern MterpShouldSwitchInterpreters 3396 EXPORT_PC 3397 move a0, rSELF 3398 daddu a1, rFP, OFF_FP_SHADOWFRAME 3399 move a2, rPC 3400 move a3, rINST 3401 jal MterpInvokeDirectRange 3402 beqzc v0, MterpException 3403 FETCH_ADVANCE_INST 3 3404 jal MterpShouldSwitchInterpreters 3405 bnezc v0, MterpFallback 3406 GET_INST_OPCODE v0 3407 GOTO_OPCODE v0 3408 3409 3410/* ------------------------------ */ 3411 .balign 128 3412.L_op_invoke_static_range: /* 0x77 */ 3413/* File: mips64/op_invoke_static_range.S */ 3414/* File: mips64/invoke.S */ 3415 /* 3416 * Generic invoke handler wrapper. 3417 */ 3418 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3419 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3420 .extern MterpInvokeStaticRange 3421 .extern MterpShouldSwitchInterpreters 3422 EXPORT_PC 3423 move a0, rSELF 3424 daddu a1, rFP, OFF_FP_SHADOWFRAME 3425 move a2, rPC 3426 move a3, rINST 3427 jal MterpInvokeStaticRange 3428 beqzc v0, MterpException 3429 FETCH_ADVANCE_INST 3 3430 jal MterpShouldSwitchInterpreters 3431 bnezc v0, MterpFallback 3432 GET_INST_OPCODE v0 3433 GOTO_OPCODE v0 3434 3435 3436/* ------------------------------ */ 3437 .balign 128 3438.L_op_invoke_interface_range: /* 0x78 */ 3439/* File: mips64/op_invoke_interface_range.S */ 3440/* File: mips64/invoke.S */ 3441 /* 3442 * Generic invoke handler wrapper. 3443 */ 3444 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3445 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3446 .extern MterpInvokeInterfaceRange 3447 .extern MterpShouldSwitchInterpreters 3448 EXPORT_PC 3449 move a0, rSELF 3450 daddu a1, rFP, OFF_FP_SHADOWFRAME 3451 move a2, rPC 3452 move a3, rINST 3453 jal MterpInvokeInterfaceRange 3454 beqzc v0, MterpException 3455 FETCH_ADVANCE_INST 3 3456 jal MterpShouldSwitchInterpreters 3457 bnezc v0, MterpFallback 3458 GET_INST_OPCODE v0 3459 GOTO_OPCODE v0 3460 3461 3462/* ------------------------------ */ 3463 .balign 128 3464.L_op_unused_79: /* 0x79 */ 3465/* File: mips64/op_unused_79.S */ 3466/* File: mips64/unused.S */ 3467/* 3468 * Bail to reference interpreter to throw. 3469 */ 3470 b MterpFallback 3471 3472 3473/* ------------------------------ */ 3474 .balign 128 3475.L_op_unused_7a: /* 0x7a */ 3476/* File: mips64/op_unused_7a.S */ 3477/* File: mips64/unused.S */ 3478/* 3479 * Bail to reference interpreter to throw. 3480 */ 3481 b MterpFallback 3482 3483 3484/* ------------------------------ */ 3485 .balign 128 3486.L_op_neg_int: /* 0x7b */ 3487/* File: mips64/op_neg_int.S */ 3488/* File: mips64/unop.S */ 3489 /* 3490 * Generic 32-bit unary operation. Provide an "instr" line that 3491 * specifies an instruction that performs "a0 = op a0". 3492 * 3493 * for: int-to-byte, int-to-char, int-to-short, 3494 * not-int, neg-int 3495 */ 3496 /* unop vA, vB */ 3497 ext a3, rINST, 12, 4 # a3 <- B 3498 GET_VREG a0, a3 # a0 <- vB 3499 ext a2, rINST, 8, 4 # a2 <- A 3500 # optional op 3501 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3502 subu a0, zero, a0 # a0 <- op, a0-a3 changed 3503 GET_INST_OPCODE v0 # extract opcode from rINST 3504 SET_VREG a0, a2 # vA <- a0 3505 GOTO_OPCODE v0 # jump to next instruction 3506 3507 3508/* ------------------------------ */ 3509 .balign 128 3510.L_op_not_int: /* 0x7c */ 3511/* File: mips64/op_not_int.S */ 3512/* File: mips64/unop.S */ 3513 /* 3514 * Generic 32-bit unary operation. Provide an "instr" line that 3515 * specifies an instruction that performs "a0 = op a0". 3516 * 3517 * for: int-to-byte, int-to-char, int-to-short, 3518 * not-int, neg-int 3519 */ 3520 /* unop vA, vB */ 3521 ext a3, rINST, 12, 4 # a3 <- B 3522 GET_VREG a0, a3 # a0 <- vB 3523 ext a2, rINST, 8, 4 # a2 <- A 3524 # optional op 3525 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3526 nor a0, zero, a0 # a0 <- op, a0-a3 changed 3527 GET_INST_OPCODE v0 # extract opcode from rINST 3528 SET_VREG a0, a2 # vA <- a0 3529 GOTO_OPCODE v0 # jump to next instruction 3530 3531 3532/* ------------------------------ */ 3533 .balign 128 3534.L_op_neg_long: /* 0x7d */ 3535/* File: mips64/op_neg_long.S */ 3536/* File: mips64/unopWide.S */ 3537 /* 3538 * Generic 64-bit unary operation. Provide an "instr" line that 3539 * specifies an instruction that performs "a0 = op a0". 3540 * 3541 * For: not-long, neg-long 3542 */ 3543 /* unop vA, vB */ 3544 ext a3, rINST, 12, 4 # a3 <- B 3545 GET_VREG_WIDE a0, a3 # a0 <- vB 3546 ext a2, rINST, 8, 4 # a2 <- A 3547 # optional op 3548 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3549 dsubu a0, zero, a0 # a0 <- op, a0-a3 changed 3550 GET_INST_OPCODE v0 # extract opcode from rINST 3551 SET_VREG_WIDE a0, a2 # vA <- a0 3552 GOTO_OPCODE v0 # jump to next instruction 3553 3554 3555/* ------------------------------ */ 3556 .balign 128 3557.L_op_not_long: /* 0x7e */ 3558/* File: mips64/op_not_long.S */ 3559/* File: mips64/unopWide.S */ 3560 /* 3561 * Generic 64-bit unary operation. Provide an "instr" line that 3562 * specifies an instruction that performs "a0 = op a0". 3563 * 3564 * For: not-long, neg-long 3565 */ 3566 /* unop vA, vB */ 3567 ext a3, rINST, 12, 4 # a3 <- B 3568 GET_VREG_WIDE a0, a3 # a0 <- vB 3569 ext a2, rINST, 8, 4 # a2 <- A 3570 # optional op 3571 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3572 nor a0, zero, a0 # a0 <- op, a0-a3 changed 3573 GET_INST_OPCODE v0 # extract opcode from rINST 3574 SET_VREG_WIDE a0, a2 # vA <- a0 3575 GOTO_OPCODE v0 # jump to next instruction 3576 3577 3578/* ------------------------------ */ 3579 .balign 128 3580.L_op_neg_float: /* 0x7f */ 3581/* File: mips64/op_neg_float.S */ 3582/* File: mips64/fcvtHeader.S */ 3583 /* 3584 * Loads a specified register from vB. Used primarily for conversions 3585 * from or to a floating-point type. 3586 * 3587 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3588 * store the result in vA and jump to the next instruction. 3589 * 3590 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3591 * float-to-int, float-to-long, float-to-double, double-to-int, 3592 * double-to-long, double-to-float, neg-float, neg-double. 3593 */ 3594 ext a1, rINST, 8, 4 # a1 <- A 3595 srl a2, rINST, 12 # a2 <- B 3596 GET_VREG_FLOAT f0, a2 3597 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3598 3599 neg.s f0, f0 3600/* File: mips64/fcvtFooter.S */ 3601 /* 3602 * Stores a specified register containing the result of conversion 3603 * from or to a floating-point type and jumps to the next instruction. 3604 * 3605 * Expects a1 to contain the destination Dalvik register number. 3606 * a1 is set up by fcvtHeader.S. 3607 * 3608 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3609 * float-to-int, float-to-long, float-to-double, double-to-int, 3610 * double-to-long, double-to-float, neg-float, neg-double. 3611 * 3612 * Note that this file can't be included after a break in other files 3613 * and in those files its contents appear as a copy. 3614 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3615 */ 3616 GET_INST_OPCODE v0 # extract opcode from rINST 3617 SET_VREG_FLOAT f0, a1 3618 GOTO_OPCODE v0 # jump to next instruction 3619 3620 3621/* ------------------------------ */ 3622 .balign 128 3623.L_op_neg_double: /* 0x80 */ 3624/* File: mips64/op_neg_double.S */ 3625/* File: mips64/fcvtHeader.S */ 3626 /* 3627 * Loads a specified register from vB. Used primarily for conversions 3628 * from or to a floating-point type. 3629 * 3630 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3631 * store the result in vA and jump to the next instruction. 3632 * 3633 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3634 * float-to-int, float-to-long, float-to-double, double-to-int, 3635 * double-to-long, double-to-float, neg-float, neg-double. 3636 */ 3637 ext a1, rINST, 8, 4 # a1 <- A 3638 srl a2, rINST, 12 # a2 <- B 3639 GET_VREG_DOUBLE f0, a2 3640 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3641 3642 neg.d f0, f0 3643/* File: mips64/fcvtFooter.S */ 3644 /* 3645 * Stores a specified register containing the result of conversion 3646 * from or to a floating-point type and jumps to the next instruction. 3647 * 3648 * Expects a1 to contain the destination Dalvik register number. 3649 * a1 is set up by fcvtHeader.S. 3650 * 3651 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3652 * float-to-int, float-to-long, float-to-double, double-to-int, 3653 * double-to-long, double-to-float, neg-float, neg-double. 3654 * 3655 * Note that this file can't be included after a break in other files 3656 * and in those files its contents appear as a copy. 3657 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3658 */ 3659 GET_INST_OPCODE v0 # extract opcode from rINST 3660 SET_VREG_DOUBLE f0, a1 3661 GOTO_OPCODE v0 # jump to next instruction 3662 3663 3664/* ------------------------------ */ 3665 .balign 128 3666.L_op_int_to_long: /* 0x81 */ 3667/* File: mips64/op_int_to_long.S */ 3668 /* int-to-long vA, vB */ 3669 ext a3, rINST, 12, 4 # a3 <- B 3670 GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) 3671 ext a2, rINST, 8, 4 # a2 <- A 3672 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3673 GET_INST_OPCODE v0 # extract opcode from rINST 3674 SET_VREG_WIDE a0, a2 # vA <- vB 3675 GOTO_OPCODE v0 # jump to next instruction 3676 3677/* ------------------------------ */ 3678 .balign 128 3679.L_op_int_to_float: /* 0x82 */ 3680/* File: mips64/op_int_to_float.S */ 3681 /* 3682 * Conversion from or to floating-point happens in a floating-point register. 3683 * Therefore we load the input and store the output into or from a 3684 * floating-point register irrespective of the type. 3685 */ 3686/* File: mips64/fcvtHeader.S */ 3687 /* 3688 * Loads a specified register from vB. Used primarily for conversions 3689 * from or to a floating-point type. 3690 * 3691 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3692 * store the result in vA and jump to the next instruction. 3693 * 3694 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3695 * float-to-int, float-to-long, float-to-double, double-to-int, 3696 * double-to-long, double-to-float, neg-float, neg-double. 3697 */ 3698 ext a1, rINST, 8, 4 # a1 <- A 3699 srl a2, rINST, 12 # a2 <- B 3700 GET_VREG_FLOAT f0, a2 3701 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3702 3703 cvt.s.w f0, f0 3704/* File: mips64/fcvtFooter.S */ 3705 /* 3706 * Stores a specified register containing the result of conversion 3707 * from or to a floating-point type and jumps to the next instruction. 3708 * 3709 * Expects a1 to contain the destination Dalvik register number. 3710 * a1 is set up by fcvtHeader.S. 3711 * 3712 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3713 * float-to-int, float-to-long, float-to-double, double-to-int, 3714 * double-to-long, double-to-float, neg-float, neg-double. 3715 * 3716 * Note that this file can't be included after a break in other files 3717 * and in those files its contents appear as a copy. 3718 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3719 */ 3720 GET_INST_OPCODE v0 # extract opcode from rINST 3721 SET_VREG_FLOAT f0, a1 3722 GOTO_OPCODE v0 # jump to next instruction 3723 3724 3725/* ------------------------------ */ 3726 .balign 128 3727.L_op_int_to_double: /* 0x83 */ 3728/* File: mips64/op_int_to_double.S */ 3729 /* 3730 * Conversion from or to floating-point happens in a floating-point register. 3731 * Therefore we load the input and store the output into or from a 3732 * floating-point register irrespective of the type. 3733 */ 3734/* File: mips64/fcvtHeader.S */ 3735 /* 3736 * Loads a specified register from vB. Used primarily for conversions 3737 * from or to a floating-point type. 3738 * 3739 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3740 * store the result in vA and jump to the next instruction. 3741 * 3742 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3743 * float-to-int, float-to-long, float-to-double, double-to-int, 3744 * double-to-long, double-to-float, neg-float, neg-double. 3745 */ 3746 ext a1, rINST, 8, 4 # a1 <- A 3747 srl a2, rINST, 12 # a2 <- B 3748 GET_VREG_FLOAT f0, a2 3749 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3750 3751 cvt.d.w f0, f0 3752/* File: mips64/fcvtFooter.S */ 3753 /* 3754 * Stores a specified register containing the result of conversion 3755 * from or to a floating-point type and jumps to the next instruction. 3756 * 3757 * Expects a1 to contain the destination Dalvik register number. 3758 * a1 is set up by fcvtHeader.S. 3759 * 3760 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3761 * float-to-int, float-to-long, float-to-double, double-to-int, 3762 * double-to-long, double-to-float, neg-float, neg-double. 3763 * 3764 * Note that this file can't be included after a break in other files 3765 * and in those files its contents appear as a copy. 3766 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3767 */ 3768 GET_INST_OPCODE v0 # extract opcode from rINST 3769 SET_VREG_DOUBLE f0, a1 3770 GOTO_OPCODE v0 # jump to next instruction 3771 3772 3773/* ------------------------------ */ 3774 .balign 128 3775.L_op_long_to_int: /* 0x84 */ 3776/* File: mips64/op_long_to_int.S */ 3777/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3778/* File: mips64/op_move.S */ 3779 /* for move, move-object, long-to-int */ 3780 /* op vA, vB */ 3781 ext a2, rINST, 8, 4 # a2 <- A 3782 ext a3, rINST, 12, 4 # a3 <- B 3783 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3784 GET_VREG a0, a3 # a0 <- vB 3785 GET_INST_OPCODE v0 # extract opcode from rINST 3786 .if 0 3787 SET_VREG_OBJECT a0, a2 # vA <- vB 3788 .else 3789 SET_VREG a0, a2 # vA <- vB 3790 .endif 3791 GOTO_OPCODE v0 # jump to next instruction 3792 3793 3794/* ------------------------------ */ 3795 .balign 128 3796.L_op_long_to_float: /* 0x85 */ 3797/* File: mips64/op_long_to_float.S */ 3798 /* 3799 * Conversion from or to floating-point happens in a floating-point register. 3800 * Therefore we load the input and store the output into or from a 3801 * floating-point register irrespective of the type. 3802 */ 3803/* File: mips64/fcvtHeader.S */ 3804 /* 3805 * Loads a specified register from vB. Used primarily for conversions 3806 * from or to a floating-point type. 3807 * 3808 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3809 * store the result in vA and jump to the next instruction. 3810 * 3811 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3812 * float-to-int, float-to-long, float-to-double, double-to-int, 3813 * double-to-long, double-to-float, neg-float, neg-double. 3814 */ 3815 ext a1, rINST, 8, 4 # a1 <- A 3816 srl a2, rINST, 12 # a2 <- B 3817 GET_VREG_DOUBLE f0, a2 3818 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3819 3820 cvt.s.l f0, f0 3821/* File: mips64/fcvtFooter.S */ 3822 /* 3823 * Stores a specified register containing the result of conversion 3824 * from or to a floating-point type and jumps to the next instruction. 3825 * 3826 * Expects a1 to contain the destination Dalvik register number. 3827 * a1 is set up by fcvtHeader.S. 3828 * 3829 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3830 * float-to-int, float-to-long, float-to-double, double-to-int, 3831 * double-to-long, double-to-float, neg-float, neg-double. 3832 * 3833 * Note that this file can't be included after a break in other files 3834 * and in those files its contents appear as a copy. 3835 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3836 */ 3837 GET_INST_OPCODE v0 # extract opcode from rINST 3838 SET_VREG_FLOAT f0, a1 3839 GOTO_OPCODE v0 # jump to next instruction 3840 3841 3842/* ------------------------------ */ 3843 .balign 128 3844.L_op_long_to_double: /* 0x86 */ 3845/* File: mips64/op_long_to_double.S */ 3846 /* 3847 * Conversion from or to floating-point happens in a floating-point register. 3848 * Therefore we load the input and store the output into or from a 3849 * floating-point register irrespective of the type. 3850 */ 3851/* File: mips64/fcvtHeader.S */ 3852 /* 3853 * Loads a specified register from vB. Used primarily for conversions 3854 * from or to a floating-point type. 3855 * 3856 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3857 * store the result in vA and jump to the next instruction. 3858 * 3859 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3860 * float-to-int, float-to-long, float-to-double, double-to-int, 3861 * double-to-long, double-to-float, neg-float, neg-double. 3862 */ 3863 ext a1, rINST, 8, 4 # a1 <- A 3864 srl a2, rINST, 12 # a2 <- B 3865 GET_VREG_DOUBLE f0, a2 3866 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3867 3868 cvt.d.l f0, f0 3869/* File: mips64/fcvtFooter.S */ 3870 /* 3871 * Stores a specified register containing the result of conversion 3872 * from or to a floating-point type and jumps to the next instruction. 3873 * 3874 * Expects a1 to contain the destination Dalvik register number. 3875 * a1 is set up by fcvtHeader.S. 3876 * 3877 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3878 * float-to-int, float-to-long, float-to-double, double-to-int, 3879 * double-to-long, double-to-float, neg-float, neg-double. 3880 * 3881 * Note that this file can't be included after a break in other files 3882 * and in those files its contents appear as a copy. 3883 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3884 */ 3885 GET_INST_OPCODE v0 # extract opcode from rINST 3886 SET_VREG_DOUBLE f0, a1 3887 GOTO_OPCODE v0 # jump to next instruction 3888 3889 3890/* ------------------------------ */ 3891 .balign 128 3892.L_op_float_to_int: /* 0x87 */ 3893/* File: mips64/op_float_to_int.S */ 3894/* File: mips64/fcvtHeader.S */ 3895 /* 3896 * Loads a specified register from vB. Used primarily for conversions 3897 * from or to a floating-point type. 3898 * 3899 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3900 * store the result in vA and jump to the next instruction. 3901 * 3902 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3903 * float-to-int, float-to-long, float-to-double, double-to-int, 3904 * double-to-long, double-to-float, neg-float, neg-double. 3905 */ 3906 ext a1, rINST, 8, 4 # a1 <- A 3907 srl a2, rINST, 12 # a2 <- B 3908 GET_VREG_FLOAT f0, a2 3909 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3910 3911 /* 3912 * TODO: simplify this when the MIPS64R6 emulator 3913 * supports NAN2008=1. 3914 */ 3915 li t0, INT_MIN_AS_FLOAT 3916 mtc1 t0, f1 3917 cmp.le.s f1, f1, f0 3918 bc1nez f1, .Lop_float_to_int_trunc 3919 cmp.eq.s f1, f0, f0 3920 li t0, INT_MIN 3921 mfc1 t1, f1 3922 and t0, t0, t1 3923 b .Lop_float_to_int_done 3924 3925/* ------------------------------ */ 3926 .balign 128 3927.L_op_float_to_long: /* 0x88 */ 3928/* File: mips64/op_float_to_long.S */ 3929/* File: mips64/fcvtHeader.S */ 3930 /* 3931 * Loads a specified register from vB. Used primarily for conversions 3932 * from or to a floating-point type. 3933 * 3934 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3935 * store the result in vA and jump to the next instruction. 3936 * 3937 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3938 * float-to-int, float-to-long, float-to-double, double-to-int, 3939 * double-to-long, double-to-float, neg-float, neg-double. 3940 */ 3941 ext a1, rINST, 8, 4 # a1 <- A 3942 srl a2, rINST, 12 # a2 <- B 3943 GET_VREG_FLOAT f0, a2 3944 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3945 3946 /* 3947 * TODO: simplify this when the MIPS64R6 emulator 3948 * supports NAN2008=1. 3949 */ 3950 li t0, LONG_MIN_AS_FLOAT 3951 mtc1 t0, f1 3952 cmp.le.s f1, f1, f0 3953 bc1nez f1, .Lop_float_to_long_trunc 3954 cmp.eq.s f1, f0, f0 3955 dli t0, LONG_MIN 3956 mfc1 t1, f1 3957 and t0, t0, t1 3958 b .Lop_float_to_long_done 3959 3960/* ------------------------------ */ 3961 .balign 128 3962.L_op_float_to_double: /* 0x89 */ 3963/* File: mips64/op_float_to_double.S */ 3964 /* 3965 * Conversion from or to floating-point happens in a floating-point register. 3966 * Therefore we load the input and store the output into or from a 3967 * floating-point register irrespective of the type. 3968 */ 3969/* File: mips64/fcvtHeader.S */ 3970 /* 3971 * Loads a specified register from vB. Used primarily for conversions 3972 * from or to a floating-point type. 3973 * 3974 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3975 * store the result in vA and jump to the next instruction. 3976 * 3977 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3978 * float-to-int, float-to-long, float-to-double, double-to-int, 3979 * double-to-long, double-to-float, neg-float, neg-double. 3980 */ 3981 ext a1, rINST, 8, 4 # a1 <- A 3982 srl a2, rINST, 12 # a2 <- B 3983 GET_VREG_FLOAT f0, a2 3984 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3985 3986 cvt.d.s f0, f0 3987/* File: mips64/fcvtFooter.S */ 3988 /* 3989 * Stores a specified register containing the result of conversion 3990 * from or to a floating-point type and jumps to the next instruction. 3991 * 3992 * Expects a1 to contain the destination Dalvik register number. 3993 * a1 is set up by fcvtHeader.S. 3994 * 3995 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3996 * float-to-int, float-to-long, float-to-double, double-to-int, 3997 * double-to-long, double-to-float, neg-float, neg-double. 3998 * 3999 * Note that this file can't be included after a break in other files 4000 * and in those files its contents appear as a copy. 4001 * See: float-to-int, float-to-long, double-to-int, double-to-long. 4002 */ 4003 GET_INST_OPCODE v0 # extract opcode from rINST 4004 SET_VREG_DOUBLE f0, a1 4005 GOTO_OPCODE v0 # jump to next instruction 4006 4007 4008/* ------------------------------ */ 4009 .balign 128 4010.L_op_double_to_int: /* 0x8a */ 4011/* File: mips64/op_double_to_int.S */ 4012/* File: mips64/fcvtHeader.S */ 4013 /* 4014 * Loads a specified register from vB. Used primarily for conversions 4015 * from or to a floating-point type. 4016 * 4017 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 4018 * store the result in vA and jump to the next instruction. 4019 * 4020 * For: int-to-float, int-to-double, long-to-float, long-to-double, 4021 * float-to-int, float-to-long, float-to-double, double-to-int, 4022 * double-to-long, double-to-float, neg-float, neg-double. 4023 */ 4024 ext a1, rINST, 8, 4 # a1 <- A 4025 srl a2, rINST, 12 # a2 <- B 4026 GET_VREG_DOUBLE f0, a2 4027 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 4028 4029 /* 4030 * TODO: simplify this when the MIPS64R6 emulator 4031 * supports NAN2008=1. 4032 */ 4033 dli t0, INT_MIN_AS_DOUBLE 4034 dmtc1 t0, f1 4035 cmp.le.d f1, f1, f0 4036 bc1nez f1, .Lop_double_to_int_trunc 4037 cmp.eq.d f1, f0, f0 4038 li t0, INT_MIN 4039 mfc1 t1, f1 4040 and t0, t0, t1 4041 b .Lop_double_to_int_done 4042 4043/* ------------------------------ */ 4044 .balign 128 4045.L_op_double_to_long: /* 0x8b */ 4046/* File: mips64/op_double_to_long.S */ 4047/* File: mips64/fcvtHeader.S */ 4048 /* 4049 * Loads a specified register from vB. Used primarily for conversions 4050 * from or to a floating-point type. 4051 * 4052 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 4053 * store the result in vA and jump to the next instruction. 4054 * 4055 * For: int-to-float, int-to-double, long-to-float, long-to-double, 4056 * float-to-int, float-to-long, float-to-double, double-to-int, 4057 * double-to-long, double-to-float, neg-float, neg-double. 4058 */ 4059 ext a1, rINST, 8, 4 # a1 <- A 4060 srl a2, rINST, 12 # a2 <- B 4061 GET_VREG_DOUBLE f0, a2 4062 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 4063 4064 /* 4065 * TODO: simplify this when the MIPS64R6 emulator 4066 * supports NAN2008=1. 4067 */ 4068 dli t0, LONG_MIN_AS_DOUBLE 4069 dmtc1 t0, f1 4070 cmp.le.d f1, f1, f0 4071 bc1nez f1, .Lop_double_to_long_trunc 4072 cmp.eq.d f1, f0, f0 4073 dli t0, LONG_MIN 4074 mfc1 t1, f1 4075 and t0, t0, t1 4076 b .Lop_double_to_long_done 4077 4078/* ------------------------------ */ 4079 .balign 128 4080.L_op_double_to_float: /* 0x8c */ 4081/* File: mips64/op_double_to_float.S */ 4082 /* 4083 * Conversion from or to floating-point happens in a floating-point register. 4084 * Therefore we load the input and store the output into or from a 4085 * floating-point register irrespective of the type. 4086 */ 4087/* File: mips64/fcvtHeader.S */ 4088 /* 4089 * Loads a specified register from vB. Used primarily for conversions 4090 * from or to a floating-point type. 4091 * 4092 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 4093 * store the result in vA and jump to the next instruction. 4094 * 4095 * For: int-to-float, int-to-double, long-to-float, long-to-double, 4096 * float-to-int, float-to-long, float-to-double, double-to-int, 4097 * double-to-long, double-to-float, neg-float, neg-double. 4098 */ 4099 ext a1, rINST, 8, 4 # a1 <- A 4100 srl a2, rINST, 12 # a2 <- B 4101 GET_VREG_DOUBLE f0, a2 4102 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 4103 4104 cvt.s.d f0, f0 4105/* File: mips64/fcvtFooter.S */ 4106 /* 4107 * Stores a specified register containing the result of conversion 4108 * from or to a floating-point type and jumps to the next instruction. 4109 * 4110 * Expects a1 to contain the destination Dalvik register number. 4111 * a1 is set up by fcvtHeader.S. 4112 * 4113 * For: int-to-float, int-to-double, long-to-float, long-to-double, 4114 * float-to-int, float-to-long, float-to-double, double-to-int, 4115 * double-to-long, double-to-float, neg-float, neg-double. 4116 * 4117 * Note that this file can't be included after a break in other files 4118 * and in those files its contents appear as a copy. 4119 * See: float-to-int, float-to-long, double-to-int, double-to-long. 4120 */ 4121 GET_INST_OPCODE v0 # extract opcode from rINST 4122 SET_VREG_FLOAT f0, a1 4123 GOTO_OPCODE v0 # jump to next instruction 4124 4125 4126/* ------------------------------ */ 4127 .balign 128 4128.L_op_int_to_byte: /* 0x8d */ 4129/* File: mips64/op_int_to_byte.S */ 4130/* File: mips64/unop.S */ 4131 /* 4132 * Generic 32-bit unary operation. Provide an "instr" line that 4133 * specifies an instruction that performs "a0 = op a0". 4134 * 4135 * for: int-to-byte, int-to-char, int-to-short, 4136 * not-int, neg-int 4137 */ 4138 /* unop vA, vB */ 4139 ext a3, rINST, 12, 4 # a3 <- B 4140 GET_VREG a0, a3 # a0 <- vB 4141 ext a2, rINST, 8, 4 # a2 <- A 4142 # optional op 4143 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 4144 seb a0, a0 # a0 <- op, a0-a3 changed 4145 GET_INST_OPCODE v0 # extract opcode from rINST 4146 SET_VREG a0, a2 # vA <- a0 4147 GOTO_OPCODE v0 # jump to next instruction 4148 4149 4150/* ------------------------------ */ 4151 .balign 128 4152.L_op_int_to_char: /* 0x8e */ 4153/* File: mips64/op_int_to_char.S */ 4154/* File: mips64/unop.S */ 4155 /* 4156 * Generic 32-bit unary operation. Provide an "instr" line that 4157 * specifies an instruction that performs "a0 = op a0". 4158 * 4159 * for: int-to-byte, int-to-char, int-to-short, 4160 * not-int, neg-int 4161 */ 4162 /* unop vA, vB */ 4163 ext a3, rINST, 12, 4 # a3 <- B 4164 GET_VREG a0, a3 # a0 <- vB 4165 ext a2, rINST, 8, 4 # a2 <- A 4166 # optional op 4167 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 4168 and a0, a0, 0xffff # a0 <- op, a0-a3 changed 4169 GET_INST_OPCODE v0 # extract opcode from rINST 4170 SET_VREG a0, a2 # vA <- a0 4171 GOTO_OPCODE v0 # jump to next instruction 4172 4173 4174/* ------------------------------ */ 4175 .balign 128 4176.L_op_int_to_short: /* 0x8f */ 4177/* File: mips64/op_int_to_short.S */ 4178/* File: mips64/unop.S */ 4179 /* 4180 * Generic 32-bit unary operation. Provide an "instr" line that 4181 * specifies an instruction that performs "a0 = op a0". 4182 * 4183 * for: int-to-byte, int-to-char, int-to-short, 4184 * not-int, neg-int 4185 */ 4186 /* unop vA, vB */ 4187 ext a3, rINST, 12, 4 # a3 <- B 4188 GET_VREG a0, a3 # a0 <- vB 4189 ext a2, rINST, 8, 4 # a2 <- A 4190 # optional op 4191 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 4192 seh a0, a0 # a0 <- op, a0-a3 changed 4193 GET_INST_OPCODE v0 # extract opcode from rINST 4194 SET_VREG a0, a2 # vA <- a0 4195 GOTO_OPCODE v0 # jump to next instruction 4196 4197 4198/* ------------------------------ */ 4199 .balign 128 4200.L_op_add_int: /* 0x90 */ 4201/* File: mips64/op_add_int.S */ 4202/* File: mips64/binop.S */ 4203 /* 4204 * Generic 32-bit binary operation. Provide an "instr" line that 4205 * specifies an instruction that performs "result = a0 op a1". 4206 * This could be a MIPS instruction or a function call. (If the result 4207 * comes back in a register other than a0, you can override "result".) 4208 * 4209 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4210 * vCC (a1). Useful for integer division and modulus. Note that we 4211 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4212 * correctly. 4213 * 4214 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4215 * xor-int, shl-int, shr-int, ushr-int 4216 */ 4217 /* binop vAA, vBB, vCC */ 4218 srl a4, rINST, 8 # a4 <- AA 4219 lbu a2, 2(rPC) # a2 <- BB 4220 lbu a3, 3(rPC) # a3 <- CC 4221 GET_VREG a0, a2 # a0 <- vBB 4222 GET_VREG a1, a3 # a1 <- vCC 4223 .if 0 4224 beqz a1, common_errDivideByZero # is second operand zero? 4225 .endif 4226 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4227 # optional op 4228 addu a0, a0, a1 # a0 <- op, a0-a3 changed 4229 GET_INST_OPCODE v0 # extract opcode from rINST 4230 SET_VREG a0, a4 # vAA <- a0 4231 GOTO_OPCODE v0 # jump to next instruction 4232 4233 4234/* ------------------------------ */ 4235 .balign 128 4236.L_op_sub_int: /* 0x91 */ 4237/* File: mips64/op_sub_int.S */ 4238/* File: mips64/binop.S */ 4239 /* 4240 * Generic 32-bit binary operation. Provide an "instr" line that 4241 * specifies an instruction that performs "result = a0 op a1". 4242 * This could be a MIPS instruction or a function call. (If the result 4243 * comes back in a register other than a0, you can override "result".) 4244 * 4245 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4246 * vCC (a1). Useful for integer division and modulus. Note that we 4247 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4248 * correctly. 4249 * 4250 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4251 * xor-int, shl-int, shr-int, ushr-int 4252 */ 4253 /* binop vAA, vBB, vCC */ 4254 srl a4, rINST, 8 # a4 <- AA 4255 lbu a2, 2(rPC) # a2 <- BB 4256 lbu a3, 3(rPC) # a3 <- CC 4257 GET_VREG a0, a2 # a0 <- vBB 4258 GET_VREG a1, a3 # a1 <- vCC 4259 .if 0 4260 beqz a1, common_errDivideByZero # is second operand zero? 4261 .endif 4262 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4263 # optional op 4264 subu a0, a0, a1 # a0 <- op, a0-a3 changed 4265 GET_INST_OPCODE v0 # extract opcode from rINST 4266 SET_VREG a0, a4 # vAA <- a0 4267 GOTO_OPCODE v0 # jump to next instruction 4268 4269 4270/* ------------------------------ */ 4271 .balign 128 4272.L_op_mul_int: /* 0x92 */ 4273/* File: mips64/op_mul_int.S */ 4274/* File: mips64/binop.S */ 4275 /* 4276 * Generic 32-bit binary operation. Provide an "instr" line that 4277 * specifies an instruction that performs "result = a0 op a1". 4278 * This could be a MIPS instruction or a function call. (If the result 4279 * comes back in a register other than a0, you can override "result".) 4280 * 4281 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4282 * vCC (a1). Useful for integer division and modulus. Note that we 4283 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4284 * correctly. 4285 * 4286 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4287 * xor-int, shl-int, shr-int, ushr-int 4288 */ 4289 /* binop vAA, vBB, vCC */ 4290 srl a4, rINST, 8 # a4 <- AA 4291 lbu a2, 2(rPC) # a2 <- BB 4292 lbu a3, 3(rPC) # a3 <- CC 4293 GET_VREG a0, a2 # a0 <- vBB 4294 GET_VREG a1, a3 # a1 <- vCC 4295 .if 0 4296 beqz a1, common_errDivideByZero # is second operand zero? 4297 .endif 4298 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4299 # optional op 4300 mul a0, a0, a1 # a0 <- op, a0-a3 changed 4301 GET_INST_OPCODE v0 # extract opcode from rINST 4302 SET_VREG a0, a4 # vAA <- a0 4303 GOTO_OPCODE v0 # jump to next instruction 4304 4305 4306/* ------------------------------ */ 4307 .balign 128 4308.L_op_div_int: /* 0x93 */ 4309/* File: mips64/op_div_int.S */ 4310/* File: mips64/binop.S */ 4311 /* 4312 * Generic 32-bit binary operation. Provide an "instr" line that 4313 * specifies an instruction that performs "result = a0 op a1". 4314 * This could be a MIPS instruction or a function call. (If the result 4315 * comes back in a register other than a0, you can override "result".) 4316 * 4317 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4318 * vCC (a1). Useful for integer division and modulus. Note that we 4319 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4320 * correctly. 4321 * 4322 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4323 * xor-int, shl-int, shr-int, ushr-int 4324 */ 4325 /* binop vAA, vBB, vCC */ 4326 srl a4, rINST, 8 # a4 <- AA 4327 lbu a2, 2(rPC) # a2 <- BB 4328 lbu a3, 3(rPC) # a3 <- CC 4329 GET_VREG a0, a2 # a0 <- vBB 4330 GET_VREG a1, a3 # a1 <- vCC 4331 .if 1 4332 beqz a1, common_errDivideByZero # is second operand zero? 4333 .endif 4334 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4335 # optional op 4336 div a0, a0, a1 # a0 <- op, a0-a3 changed 4337 GET_INST_OPCODE v0 # extract opcode from rINST 4338 SET_VREG a0, a4 # vAA <- a0 4339 GOTO_OPCODE v0 # jump to next instruction 4340 4341 4342/* ------------------------------ */ 4343 .balign 128 4344.L_op_rem_int: /* 0x94 */ 4345/* File: mips64/op_rem_int.S */ 4346/* File: mips64/binop.S */ 4347 /* 4348 * Generic 32-bit binary operation. Provide an "instr" line that 4349 * specifies an instruction that performs "result = a0 op a1". 4350 * This could be a MIPS instruction or a function call. (If the result 4351 * comes back in a register other than a0, you can override "result".) 4352 * 4353 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4354 * vCC (a1). Useful for integer division and modulus. Note that we 4355 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4356 * correctly. 4357 * 4358 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4359 * xor-int, shl-int, shr-int, ushr-int 4360 */ 4361 /* binop vAA, vBB, vCC */ 4362 srl a4, rINST, 8 # a4 <- AA 4363 lbu a2, 2(rPC) # a2 <- BB 4364 lbu a3, 3(rPC) # a3 <- CC 4365 GET_VREG a0, a2 # a0 <- vBB 4366 GET_VREG a1, a3 # a1 <- vCC 4367 .if 1 4368 beqz a1, common_errDivideByZero # is second operand zero? 4369 .endif 4370 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4371 # optional op 4372 mod a0, a0, a1 # a0 <- op, a0-a3 changed 4373 GET_INST_OPCODE v0 # extract opcode from rINST 4374 SET_VREG a0, a4 # vAA <- a0 4375 GOTO_OPCODE v0 # jump to next instruction 4376 4377 4378/* ------------------------------ */ 4379 .balign 128 4380.L_op_and_int: /* 0x95 */ 4381/* File: mips64/op_and_int.S */ 4382/* File: mips64/binop.S */ 4383 /* 4384 * Generic 32-bit binary operation. Provide an "instr" line that 4385 * specifies an instruction that performs "result = a0 op a1". 4386 * This could be a MIPS instruction or a function call. (If the result 4387 * comes back in a register other than a0, you can override "result".) 4388 * 4389 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4390 * vCC (a1). Useful for integer division and modulus. Note that we 4391 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4392 * correctly. 4393 * 4394 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4395 * xor-int, shl-int, shr-int, ushr-int 4396 */ 4397 /* binop vAA, vBB, vCC */ 4398 srl a4, rINST, 8 # a4 <- AA 4399 lbu a2, 2(rPC) # a2 <- BB 4400 lbu a3, 3(rPC) # a3 <- CC 4401 GET_VREG a0, a2 # a0 <- vBB 4402 GET_VREG a1, a3 # a1 <- vCC 4403 .if 0 4404 beqz a1, common_errDivideByZero # is second operand zero? 4405 .endif 4406 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4407 # optional op 4408 and a0, a0, a1 # a0 <- op, a0-a3 changed 4409 GET_INST_OPCODE v0 # extract opcode from rINST 4410 SET_VREG a0, a4 # vAA <- a0 4411 GOTO_OPCODE v0 # jump to next instruction 4412 4413 4414/* ------------------------------ */ 4415 .balign 128 4416.L_op_or_int: /* 0x96 */ 4417/* File: mips64/op_or_int.S */ 4418/* File: mips64/binop.S */ 4419 /* 4420 * Generic 32-bit binary operation. Provide an "instr" line that 4421 * specifies an instruction that performs "result = a0 op a1". 4422 * This could be a MIPS instruction or a function call. (If the result 4423 * comes back in a register other than a0, you can override "result".) 4424 * 4425 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4426 * vCC (a1). Useful for integer division and modulus. Note that we 4427 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4428 * correctly. 4429 * 4430 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4431 * xor-int, shl-int, shr-int, ushr-int 4432 */ 4433 /* binop vAA, vBB, vCC */ 4434 srl a4, rINST, 8 # a4 <- AA 4435 lbu a2, 2(rPC) # a2 <- BB 4436 lbu a3, 3(rPC) # a3 <- CC 4437 GET_VREG a0, a2 # a0 <- vBB 4438 GET_VREG a1, a3 # a1 <- vCC 4439 .if 0 4440 beqz a1, common_errDivideByZero # is second operand zero? 4441 .endif 4442 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4443 # optional op 4444 or a0, a0, a1 # a0 <- op, a0-a3 changed 4445 GET_INST_OPCODE v0 # extract opcode from rINST 4446 SET_VREG a0, a4 # vAA <- a0 4447 GOTO_OPCODE v0 # jump to next instruction 4448 4449 4450/* ------------------------------ */ 4451 .balign 128 4452.L_op_xor_int: /* 0x97 */ 4453/* File: mips64/op_xor_int.S */ 4454/* File: mips64/binop.S */ 4455 /* 4456 * Generic 32-bit binary operation. Provide an "instr" line that 4457 * specifies an instruction that performs "result = a0 op a1". 4458 * This could be a MIPS instruction or a function call. (If the result 4459 * comes back in a register other than a0, you can override "result".) 4460 * 4461 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4462 * vCC (a1). Useful for integer division and modulus. Note that we 4463 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4464 * correctly. 4465 * 4466 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4467 * xor-int, shl-int, shr-int, ushr-int 4468 */ 4469 /* binop vAA, vBB, vCC */ 4470 srl a4, rINST, 8 # a4 <- AA 4471 lbu a2, 2(rPC) # a2 <- BB 4472 lbu a3, 3(rPC) # a3 <- CC 4473 GET_VREG a0, a2 # a0 <- vBB 4474 GET_VREG a1, a3 # a1 <- vCC 4475 .if 0 4476 beqz a1, common_errDivideByZero # is second operand zero? 4477 .endif 4478 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4479 # optional op 4480 xor a0, a0, a1 # a0 <- op, a0-a3 changed 4481 GET_INST_OPCODE v0 # extract opcode from rINST 4482 SET_VREG a0, a4 # vAA <- a0 4483 GOTO_OPCODE v0 # jump to next instruction 4484 4485 4486/* ------------------------------ */ 4487 .balign 128 4488.L_op_shl_int: /* 0x98 */ 4489/* File: mips64/op_shl_int.S */ 4490/* File: mips64/binop.S */ 4491 /* 4492 * Generic 32-bit binary operation. Provide an "instr" line that 4493 * specifies an instruction that performs "result = a0 op a1". 4494 * This could be a MIPS instruction or a function call. (If the result 4495 * comes back in a register other than a0, you can override "result".) 4496 * 4497 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4498 * vCC (a1). Useful for integer division and modulus. Note that we 4499 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4500 * correctly. 4501 * 4502 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4503 * xor-int, shl-int, shr-int, ushr-int 4504 */ 4505 /* binop vAA, vBB, vCC */ 4506 srl a4, rINST, 8 # a4 <- AA 4507 lbu a2, 2(rPC) # a2 <- BB 4508 lbu a3, 3(rPC) # a3 <- CC 4509 GET_VREG a0, a2 # a0 <- vBB 4510 GET_VREG a1, a3 # a1 <- vCC 4511 .if 0 4512 beqz a1, common_errDivideByZero # is second operand zero? 4513 .endif 4514 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4515 # optional op 4516 sll a0, a0, a1 # a0 <- op, a0-a3 changed 4517 GET_INST_OPCODE v0 # extract opcode from rINST 4518 SET_VREG a0, a4 # vAA <- a0 4519 GOTO_OPCODE v0 # jump to next instruction 4520 4521 4522/* ------------------------------ */ 4523 .balign 128 4524.L_op_shr_int: /* 0x99 */ 4525/* File: mips64/op_shr_int.S */ 4526/* File: mips64/binop.S */ 4527 /* 4528 * Generic 32-bit binary operation. Provide an "instr" line that 4529 * specifies an instruction that performs "result = a0 op a1". 4530 * This could be a MIPS instruction or a function call. (If the result 4531 * comes back in a register other than a0, you can override "result".) 4532 * 4533 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4534 * vCC (a1). Useful for integer division and modulus. Note that we 4535 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4536 * correctly. 4537 * 4538 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4539 * xor-int, shl-int, shr-int, ushr-int 4540 */ 4541 /* binop vAA, vBB, vCC */ 4542 srl a4, rINST, 8 # a4 <- AA 4543 lbu a2, 2(rPC) # a2 <- BB 4544 lbu a3, 3(rPC) # a3 <- CC 4545 GET_VREG a0, a2 # a0 <- vBB 4546 GET_VREG a1, a3 # a1 <- vCC 4547 .if 0 4548 beqz a1, common_errDivideByZero # is second operand zero? 4549 .endif 4550 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4551 # optional op 4552 sra a0, a0, a1 # a0 <- op, a0-a3 changed 4553 GET_INST_OPCODE v0 # extract opcode from rINST 4554 SET_VREG a0, a4 # vAA <- a0 4555 GOTO_OPCODE v0 # jump to next instruction 4556 4557 4558/* ------------------------------ */ 4559 .balign 128 4560.L_op_ushr_int: /* 0x9a */ 4561/* File: mips64/op_ushr_int.S */ 4562/* File: mips64/binop.S */ 4563 /* 4564 * Generic 32-bit binary operation. Provide an "instr" line that 4565 * specifies an instruction that performs "result = a0 op a1". 4566 * This could be a MIPS instruction or a function call. (If the result 4567 * comes back in a register other than a0, you can override "result".) 4568 * 4569 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4570 * vCC (a1). Useful for integer division and modulus. Note that we 4571 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4572 * correctly. 4573 * 4574 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4575 * xor-int, shl-int, shr-int, ushr-int 4576 */ 4577 /* binop vAA, vBB, vCC */ 4578 srl a4, rINST, 8 # a4 <- AA 4579 lbu a2, 2(rPC) # a2 <- BB 4580 lbu a3, 3(rPC) # a3 <- CC 4581 GET_VREG a0, a2 # a0 <- vBB 4582 GET_VREG a1, a3 # a1 <- vCC 4583 .if 0 4584 beqz a1, common_errDivideByZero # is second operand zero? 4585 .endif 4586 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4587 # optional op 4588 srl a0, a0, a1 # a0 <- op, a0-a3 changed 4589 GET_INST_OPCODE v0 # extract opcode from rINST 4590 SET_VREG a0, a4 # vAA <- a0 4591 GOTO_OPCODE v0 # jump to next instruction 4592 4593 4594/* ------------------------------ */ 4595 .balign 128 4596.L_op_add_long: /* 0x9b */ 4597/* File: mips64/op_add_long.S */ 4598/* File: mips64/binopWide.S */ 4599 /* 4600 * Generic 64-bit binary operation. Provide an "instr" line that 4601 * specifies an instruction that performs "result = a0 op a1". 4602 * This could be a MIPS instruction or a function call. (If the result 4603 * comes back in a register other than a0, you can override "result".) 4604 * 4605 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4606 * vCC (a1). Useful for integer division and modulus. Note that we 4607 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4608 * correctly. 4609 * 4610 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4611 * xor-long, shl-long, shr-long, ushr-long 4612 */ 4613 /* binop vAA, vBB, vCC */ 4614 srl a4, rINST, 8 # a4 <- AA 4615 lbu a2, 2(rPC) # a2 <- BB 4616 lbu a3, 3(rPC) # a3 <- CC 4617 GET_VREG_WIDE a0, a2 # a0 <- vBB 4618 GET_VREG_WIDE a1, a3 # a1 <- vCC 4619 .if 0 4620 beqz a1, common_errDivideByZero # is second operand zero? 4621 .endif 4622 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4623 # optional op 4624 daddu a0, a0, a1 # a0 <- op, a0-a3 changed 4625 GET_INST_OPCODE v0 # extract opcode from rINST 4626 SET_VREG_WIDE a0, a4 # vAA <- a0 4627 GOTO_OPCODE v0 # jump to next instruction 4628 4629 4630/* ------------------------------ */ 4631 .balign 128 4632.L_op_sub_long: /* 0x9c */ 4633/* File: mips64/op_sub_long.S */ 4634/* File: mips64/binopWide.S */ 4635 /* 4636 * Generic 64-bit binary operation. Provide an "instr" line that 4637 * specifies an instruction that performs "result = a0 op a1". 4638 * This could be a MIPS instruction or a function call. (If the result 4639 * comes back in a register other than a0, you can override "result".) 4640 * 4641 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4642 * vCC (a1). Useful for integer division and modulus. Note that we 4643 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4644 * correctly. 4645 * 4646 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4647 * xor-long, shl-long, shr-long, ushr-long 4648 */ 4649 /* binop vAA, vBB, vCC */ 4650 srl a4, rINST, 8 # a4 <- AA 4651 lbu a2, 2(rPC) # a2 <- BB 4652 lbu a3, 3(rPC) # a3 <- CC 4653 GET_VREG_WIDE a0, a2 # a0 <- vBB 4654 GET_VREG_WIDE a1, a3 # a1 <- vCC 4655 .if 0 4656 beqz a1, common_errDivideByZero # is second operand zero? 4657 .endif 4658 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4659 # optional op 4660 dsubu a0, a0, a1 # a0 <- op, a0-a3 changed 4661 GET_INST_OPCODE v0 # extract opcode from rINST 4662 SET_VREG_WIDE a0, a4 # vAA <- a0 4663 GOTO_OPCODE v0 # jump to next instruction 4664 4665 4666/* ------------------------------ */ 4667 .balign 128 4668.L_op_mul_long: /* 0x9d */ 4669/* File: mips64/op_mul_long.S */ 4670/* File: mips64/binopWide.S */ 4671 /* 4672 * Generic 64-bit binary operation. Provide an "instr" line that 4673 * specifies an instruction that performs "result = a0 op a1". 4674 * This could be a MIPS instruction or a function call. (If the result 4675 * comes back in a register other than a0, you can override "result".) 4676 * 4677 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4678 * vCC (a1). Useful for integer division and modulus. Note that we 4679 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4680 * correctly. 4681 * 4682 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4683 * xor-long, shl-long, shr-long, ushr-long 4684 */ 4685 /* binop vAA, vBB, vCC */ 4686 srl a4, rINST, 8 # a4 <- AA 4687 lbu a2, 2(rPC) # a2 <- BB 4688 lbu a3, 3(rPC) # a3 <- CC 4689 GET_VREG_WIDE a0, a2 # a0 <- vBB 4690 GET_VREG_WIDE a1, a3 # a1 <- vCC 4691 .if 0 4692 beqz a1, common_errDivideByZero # is second operand zero? 4693 .endif 4694 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4695 # optional op 4696 dmul a0, a0, a1 # a0 <- op, a0-a3 changed 4697 GET_INST_OPCODE v0 # extract opcode from rINST 4698 SET_VREG_WIDE a0, a4 # vAA <- a0 4699 GOTO_OPCODE v0 # jump to next instruction 4700 4701 4702/* ------------------------------ */ 4703 .balign 128 4704.L_op_div_long: /* 0x9e */ 4705/* File: mips64/op_div_long.S */ 4706/* File: mips64/binopWide.S */ 4707 /* 4708 * Generic 64-bit binary operation. Provide an "instr" line that 4709 * specifies an instruction that performs "result = a0 op a1". 4710 * This could be a MIPS instruction or a function call. (If the result 4711 * comes back in a register other than a0, you can override "result".) 4712 * 4713 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4714 * vCC (a1). Useful for integer division and modulus. Note that we 4715 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4716 * correctly. 4717 * 4718 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4719 * xor-long, shl-long, shr-long, ushr-long 4720 */ 4721 /* binop vAA, vBB, vCC */ 4722 srl a4, rINST, 8 # a4 <- AA 4723 lbu a2, 2(rPC) # a2 <- BB 4724 lbu a3, 3(rPC) # a3 <- CC 4725 GET_VREG_WIDE a0, a2 # a0 <- vBB 4726 GET_VREG_WIDE a1, a3 # a1 <- vCC 4727 .if 1 4728 beqz a1, common_errDivideByZero # is second operand zero? 4729 .endif 4730 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4731 # optional op 4732 ddiv a0, a0, a1 # a0 <- op, a0-a3 changed 4733 GET_INST_OPCODE v0 # extract opcode from rINST 4734 SET_VREG_WIDE a0, a4 # vAA <- a0 4735 GOTO_OPCODE v0 # jump to next instruction 4736 4737 4738/* ------------------------------ */ 4739 .balign 128 4740.L_op_rem_long: /* 0x9f */ 4741/* File: mips64/op_rem_long.S */ 4742/* File: mips64/binopWide.S */ 4743 /* 4744 * Generic 64-bit binary operation. Provide an "instr" line that 4745 * specifies an instruction that performs "result = a0 op a1". 4746 * This could be a MIPS instruction or a function call. (If the result 4747 * comes back in a register other than a0, you can override "result".) 4748 * 4749 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4750 * vCC (a1). Useful for integer division and modulus. Note that we 4751 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4752 * correctly. 4753 * 4754 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4755 * xor-long, shl-long, shr-long, ushr-long 4756 */ 4757 /* binop vAA, vBB, vCC */ 4758 srl a4, rINST, 8 # a4 <- AA 4759 lbu a2, 2(rPC) # a2 <- BB 4760 lbu a3, 3(rPC) # a3 <- CC 4761 GET_VREG_WIDE a0, a2 # a0 <- vBB 4762 GET_VREG_WIDE a1, a3 # a1 <- vCC 4763 .if 1 4764 beqz a1, common_errDivideByZero # is second operand zero? 4765 .endif 4766 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4767 # optional op 4768 dmod a0, a0, a1 # a0 <- op, a0-a3 changed 4769 GET_INST_OPCODE v0 # extract opcode from rINST 4770 SET_VREG_WIDE a0, a4 # vAA <- a0 4771 GOTO_OPCODE v0 # jump to next instruction 4772 4773 4774/* ------------------------------ */ 4775 .balign 128 4776.L_op_and_long: /* 0xa0 */ 4777/* File: mips64/op_and_long.S */ 4778/* File: mips64/binopWide.S */ 4779 /* 4780 * Generic 64-bit binary operation. Provide an "instr" line that 4781 * specifies an instruction that performs "result = a0 op a1". 4782 * This could be a MIPS instruction or a function call. (If the result 4783 * comes back in a register other than a0, you can override "result".) 4784 * 4785 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4786 * vCC (a1). Useful for integer division and modulus. Note that we 4787 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4788 * correctly. 4789 * 4790 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4791 * xor-long, shl-long, shr-long, ushr-long 4792 */ 4793 /* binop vAA, vBB, vCC */ 4794 srl a4, rINST, 8 # a4 <- AA 4795 lbu a2, 2(rPC) # a2 <- BB 4796 lbu a3, 3(rPC) # a3 <- CC 4797 GET_VREG_WIDE a0, a2 # a0 <- vBB 4798 GET_VREG_WIDE a1, a3 # a1 <- vCC 4799 .if 0 4800 beqz a1, common_errDivideByZero # is second operand zero? 4801 .endif 4802 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4803 # optional op 4804 and a0, a0, a1 # a0 <- op, a0-a3 changed 4805 GET_INST_OPCODE v0 # extract opcode from rINST 4806 SET_VREG_WIDE a0, a4 # vAA <- a0 4807 GOTO_OPCODE v0 # jump to next instruction 4808 4809 4810/* ------------------------------ */ 4811 .balign 128 4812.L_op_or_long: /* 0xa1 */ 4813/* File: mips64/op_or_long.S */ 4814/* File: mips64/binopWide.S */ 4815 /* 4816 * Generic 64-bit binary operation. Provide an "instr" line that 4817 * specifies an instruction that performs "result = a0 op a1". 4818 * This could be a MIPS instruction or a function call. (If the result 4819 * comes back in a register other than a0, you can override "result".) 4820 * 4821 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4822 * vCC (a1). Useful for integer division and modulus. Note that we 4823 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4824 * correctly. 4825 * 4826 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4827 * xor-long, shl-long, shr-long, ushr-long 4828 */ 4829 /* binop vAA, vBB, vCC */ 4830 srl a4, rINST, 8 # a4 <- AA 4831 lbu a2, 2(rPC) # a2 <- BB 4832 lbu a3, 3(rPC) # a3 <- CC 4833 GET_VREG_WIDE a0, a2 # a0 <- vBB 4834 GET_VREG_WIDE a1, a3 # a1 <- vCC 4835 .if 0 4836 beqz a1, common_errDivideByZero # is second operand zero? 4837 .endif 4838 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4839 # optional op 4840 or a0, a0, a1 # a0 <- op, a0-a3 changed 4841 GET_INST_OPCODE v0 # extract opcode from rINST 4842 SET_VREG_WIDE a0, a4 # vAA <- a0 4843 GOTO_OPCODE v0 # jump to next instruction 4844 4845 4846/* ------------------------------ */ 4847 .balign 128 4848.L_op_xor_long: /* 0xa2 */ 4849/* File: mips64/op_xor_long.S */ 4850/* File: mips64/binopWide.S */ 4851 /* 4852 * Generic 64-bit binary operation. Provide an "instr" line that 4853 * specifies an instruction that performs "result = a0 op a1". 4854 * This could be a MIPS instruction or a function call. (If the result 4855 * comes back in a register other than a0, you can override "result".) 4856 * 4857 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4858 * vCC (a1). Useful for integer division and modulus. Note that we 4859 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4860 * correctly. 4861 * 4862 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4863 * xor-long, shl-long, shr-long, ushr-long 4864 */ 4865 /* binop vAA, vBB, vCC */ 4866 srl a4, rINST, 8 # a4 <- AA 4867 lbu a2, 2(rPC) # a2 <- BB 4868 lbu a3, 3(rPC) # a3 <- CC 4869 GET_VREG_WIDE a0, a2 # a0 <- vBB 4870 GET_VREG_WIDE a1, a3 # a1 <- vCC 4871 .if 0 4872 beqz a1, common_errDivideByZero # is second operand zero? 4873 .endif 4874 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4875 # optional op 4876 xor a0, a0, a1 # a0 <- op, a0-a3 changed 4877 GET_INST_OPCODE v0 # extract opcode from rINST 4878 SET_VREG_WIDE a0, a4 # vAA <- a0 4879 GOTO_OPCODE v0 # jump to next instruction 4880 4881 4882/* ------------------------------ */ 4883 .balign 128 4884.L_op_shl_long: /* 0xa3 */ 4885/* File: mips64/op_shl_long.S */ 4886/* File: mips64/binopWide.S */ 4887 /* 4888 * Generic 64-bit binary operation. Provide an "instr" line that 4889 * specifies an instruction that performs "result = a0 op a1". 4890 * This could be a MIPS instruction or a function call. (If the result 4891 * comes back in a register other than a0, you can override "result".) 4892 * 4893 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4894 * vCC (a1). Useful for integer division and modulus. Note that we 4895 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4896 * correctly. 4897 * 4898 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4899 * xor-long, shl-long, shr-long, ushr-long 4900 */ 4901 /* binop vAA, vBB, vCC */ 4902 srl a4, rINST, 8 # a4 <- AA 4903 lbu a2, 2(rPC) # a2 <- BB 4904 lbu a3, 3(rPC) # a3 <- CC 4905 GET_VREG_WIDE a0, a2 # a0 <- vBB 4906 GET_VREG_WIDE a1, a3 # a1 <- vCC 4907 .if 0 4908 beqz a1, common_errDivideByZero # is second operand zero? 4909 .endif 4910 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4911 # optional op 4912 dsll a0, a0, a1 # a0 <- op, a0-a3 changed 4913 GET_INST_OPCODE v0 # extract opcode from rINST 4914 SET_VREG_WIDE a0, a4 # vAA <- a0 4915 GOTO_OPCODE v0 # jump to next instruction 4916 4917 4918/* ------------------------------ */ 4919 .balign 128 4920.L_op_shr_long: /* 0xa4 */ 4921/* File: mips64/op_shr_long.S */ 4922/* File: mips64/binopWide.S */ 4923 /* 4924 * Generic 64-bit binary operation. Provide an "instr" line that 4925 * specifies an instruction that performs "result = a0 op a1". 4926 * This could be a MIPS instruction or a function call. (If the result 4927 * comes back in a register other than a0, you can override "result".) 4928 * 4929 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4930 * vCC (a1). Useful for integer division and modulus. Note that we 4931 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4932 * correctly. 4933 * 4934 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4935 * xor-long, shl-long, shr-long, ushr-long 4936 */ 4937 /* binop vAA, vBB, vCC */ 4938 srl a4, rINST, 8 # a4 <- AA 4939 lbu a2, 2(rPC) # a2 <- BB 4940 lbu a3, 3(rPC) # a3 <- CC 4941 GET_VREG_WIDE a0, a2 # a0 <- vBB 4942 GET_VREG_WIDE a1, a3 # a1 <- vCC 4943 .if 0 4944 beqz a1, common_errDivideByZero # is second operand zero? 4945 .endif 4946 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4947 # optional op 4948 dsra a0, a0, a1 # a0 <- op, a0-a3 changed 4949 GET_INST_OPCODE v0 # extract opcode from rINST 4950 SET_VREG_WIDE a0, a4 # vAA <- a0 4951 GOTO_OPCODE v0 # jump to next instruction 4952 4953 4954/* ------------------------------ */ 4955 .balign 128 4956.L_op_ushr_long: /* 0xa5 */ 4957/* File: mips64/op_ushr_long.S */ 4958/* File: mips64/binopWide.S */ 4959 /* 4960 * Generic 64-bit binary operation. Provide an "instr" line that 4961 * specifies an instruction that performs "result = a0 op a1". 4962 * This could be a MIPS instruction or a function call. (If the result 4963 * comes back in a register other than a0, you can override "result".) 4964 * 4965 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4966 * vCC (a1). Useful for integer division and modulus. Note that we 4967 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4968 * correctly. 4969 * 4970 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4971 * xor-long, shl-long, shr-long, ushr-long 4972 */ 4973 /* binop vAA, vBB, vCC */ 4974 srl a4, rINST, 8 # a4 <- AA 4975 lbu a2, 2(rPC) # a2 <- BB 4976 lbu a3, 3(rPC) # a3 <- CC 4977 GET_VREG_WIDE a0, a2 # a0 <- vBB 4978 GET_VREG_WIDE a1, a3 # a1 <- vCC 4979 .if 0 4980 beqz a1, common_errDivideByZero # is second operand zero? 4981 .endif 4982 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4983 # optional op 4984 dsrl a0, a0, a1 # a0 <- op, a0-a3 changed 4985 GET_INST_OPCODE v0 # extract opcode from rINST 4986 SET_VREG_WIDE a0, a4 # vAA <- a0 4987 GOTO_OPCODE v0 # jump to next instruction 4988 4989 4990/* ------------------------------ */ 4991 .balign 128 4992.L_op_add_float: /* 0xa6 */ 4993/* File: mips64/op_add_float.S */ 4994/* File: mips64/fbinop.S */ 4995 /*: 4996 * Generic 32-bit floating-point operation. 4997 * 4998 * For: add-float, sub-float, mul-float, div-float. 4999 * form: <op> f0, f0, f1 5000 */ 5001 /* binop vAA, vBB, vCC */ 5002 srl a4, rINST, 8 # a4 <- AA 5003 lbu a2, 2(rPC) # a2 <- BB 5004 lbu a3, 3(rPC) # a3 <- CC 5005 GET_VREG_FLOAT f0, a2 # f0 <- vBB 5006 GET_VREG_FLOAT f1, a3 # f1 <- vCC 5007 add.s f0, f0, f1 # f0 <- f0 op f1 5008 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5009 GET_INST_OPCODE v0 # extract opcode from rINST 5010 SET_VREG_FLOAT f0, a4 # vAA <- f0 5011 GOTO_OPCODE v0 # jump to next instruction 5012 5013 5014/* ------------------------------ */ 5015 .balign 128 5016.L_op_sub_float: /* 0xa7 */ 5017/* File: mips64/op_sub_float.S */ 5018/* File: mips64/fbinop.S */ 5019 /*: 5020 * Generic 32-bit floating-point operation. 5021 * 5022 * For: add-float, sub-float, mul-float, div-float. 5023 * form: <op> f0, f0, f1 5024 */ 5025 /* binop vAA, vBB, vCC */ 5026 srl a4, rINST, 8 # a4 <- AA 5027 lbu a2, 2(rPC) # a2 <- BB 5028 lbu a3, 3(rPC) # a3 <- CC 5029 GET_VREG_FLOAT f0, a2 # f0 <- vBB 5030 GET_VREG_FLOAT f1, a3 # f1 <- vCC 5031 sub.s f0, f0, f1 # f0 <- f0 op f1 5032 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5033 GET_INST_OPCODE v0 # extract opcode from rINST 5034 SET_VREG_FLOAT f0, a4 # vAA <- f0 5035 GOTO_OPCODE v0 # jump to next instruction 5036 5037 5038/* ------------------------------ */ 5039 .balign 128 5040.L_op_mul_float: /* 0xa8 */ 5041/* File: mips64/op_mul_float.S */ 5042/* File: mips64/fbinop.S */ 5043 /*: 5044 * Generic 32-bit floating-point operation. 5045 * 5046 * For: add-float, sub-float, mul-float, div-float. 5047 * form: <op> f0, f0, f1 5048 */ 5049 /* binop vAA, vBB, vCC */ 5050 srl a4, rINST, 8 # a4 <- AA 5051 lbu a2, 2(rPC) # a2 <- BB 5052 lbu a3, 3(rPC) # a3 <- CC 5053 GET_VREG_FLOAT f0, a2 # f0 <- vBB 5054 GET_VREG_FLOAT f1, a3 # f1 <- vCC 5055 mul.s f0, f0, f1 # f0 <- f0 op f1 5056 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5057 GET_INST_OPCODE v0 # extract opcode from rINST 5058 SET_VREG_FLOAT f0, a4 # vAA <- f0 5059 GOTO_OPCODE v0 # jump to next instruction 5060 5061 5062/* ------------------------------ */ 5063 .balign 128 5064.L_op_div_float: /* 0xa9 */ 5065/* File: mips64/op_div_float.S */ 5066/* File: mips64/fbinop.S */ 5067 /*: 5068 * Generic 32-bit floating-point operation. 5069 * 5070 * For: add-float, sub-float, mul-float, div-float. 5071 * form: <op> f0, f0, f1 5072 */ 5073 /* binop vAA, vBB, vCC */ 5074 srl a4, rINST, 8 # a4 <- AA 5075 lbu a2, 2(rPC) # a2 <- BB 5076 lbu a3, 3(rPC) # a3 <- CC 5077 GET_VREG_FLOAT f0, a2 # f0 <- vBB 5078 GET_VREG_FLOAT f1, a3 # f1 <- vCC 5079 div.s f0, f0, f1 # f0 <- f0 op f1 5080 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5081 GET_INST_OPCODE v0 # extract opcode from rINST 5082 SET_VREG_FLOAT f0, a4 # vAA <- f0 5083 GOTO_OPCODE v0 # jump to next instruction 5084 5085 5086/* ------------------------------ */ 5087 .balign 128 5088.L_op_rem_float: /* 0xaa */ 5089/* File: mips64/op_rem_float.S */ 5090 /* rem-float vAA, vBB, vCC */ 5091 .extern fmodf 5092 lbu a2, 2(rPC) # a2 <- BB 5093 lbu a3, 3(rPC) # a3 <- CC 5094 GET_VREG_FLOAT f12, a2 # f12 <- vBB 5095 GET_VREG_FLOAT f13, a3 # f13 <- vCC 5096 jal fmodf # f0 <- f12 op f13 5097 srl a4, rINST, 8 # a4 <- AA 5098 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5099 GET_INST_OPCODE v0 # extract opcode from rINST 5100 SET_VREG_FLOAT f0, a4 # vAA <- f0 5101 GOTO_OPCODE v0 # jump to next instruction 5102 5103/* ------------------------------ */ 5104 .balign 128 5105.L_op_add_double: /* 0xab */ 5106/* File: mips64/op_add_double.S */ 5107/* File: mips64/fbinopWide.S */ 5108 /*: 5109 * Generic 64-bit floating-point operation. 5110 * 5111 * For: add-double, sub-double, mul-double, div-double. 5112 * form: <op> f0, f0, f1 5113 */ 5114 /* binop vAA, vBB, vCC */ 5115 srl a4, rINST, 8 # a4 <- AA 5116 lbu a2, 2(rPC) # a2 <- BB 5117 lbu a3, 3(rPC) # a3 <- CC 5118 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 5119 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 5120 add.d f0, f0, f1 # f0 <- f0 op f1 5121 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5122 GET_INST_OPCODE v0 # extract opcode from rINST 5123 SET_VREG_DOUBLE f0, a4 # vAA <- f0 5124 GOTO_OPCODE v0 # jump to next instruction 5125 5126 5127/* ------------------------------ */ 5128 .balign 128 5129.L_op_sub_double: /* 0xac */ 5130/* File: mips64/op_sub_double.S */ 5131/* File: mips64/fbinopWide.S */ 5132 /*: 5133 * Generic 64-bit floating-point operation. 5134 * 5135 * For: add-double, sub-double, mul-double, div-double. 5136 * form: <op> f0, f0, f1 5137 */ 5138 /* binop vAA, vBB, vCC */ 5139 srl a4, rINST, 8 # a4 <- AA 5140 lbu a2, 2(rPC) # a2 <- BB 5141 lbu a3, 3(rPC) # a3 <- CC 5142 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 5143 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 5144 sub.d f0, f0, f1 # f0 <- f0 op f1 5145 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5146 GET_INST_OPCODE v0 # extract opcode from rINST 5147 SET_VREG_DOUBLE f0, a4 # vAA <- f0 5148 GOTO_OPCODE v0 # jump to next instruction 5149 5150 5151/* ------------------------------ */ 5152 .balign 128 5153.L_op_mul_double: /* 0xad */ 5154/* File: mips64/op_mul_double.S */ 5155/* File: mips64/fbinopWide.S */ 5156 /*: 5157 * Generic 64-bit floating-point operation. 5158 * 5159 * For: add-double, sub-double, mul-double, div-double. 5160 * form: <op> f0, f0, f1 5161 */ 5162 /* binop vAA, vBB, vCC */ 5163 srl a4, rINST, 8 # a4 <- AA 5164 lbu a2, 2(rPC) # a2 <- BB 5165 lbu a3, 3(rPC) # a3 <- CC 5166 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 5167 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 5168 mul.d f0, f0, f1 # f0 <- f0 op f1 5169 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5170 GET_INST_OPCODE v0 # extract opcode from rINST 5171 SET_VREG_DOUBLE f0, a4 # vAA <- f0 5172 GOTO_OPCODE v0 # jump to next instruction 5173 5174 5175/* ------------------------------ */ 5176 .balign 128 5177.L_op_div_double: /* 0xae */ 5178/* File: mips64/op_div_double.S */ 5179/* File: mips64/fbinopWide.S */ 5180 /*: 5181 * Generic 64-bit floating-point operation. 5182 * 5183 * For: add-double, sub-double, mul-double, div-double. 5184 * form: <op> f0, f0, f1 5185 */ 5186 /* binop vAA, vBB, vCC */ 5187 srl a4, rINST, 8 # a4 <- AA 5188 lbu a2, 2(rPC) # a2 <- BB 5189 lbu a3, 3(rPC) # a3 <- CC 5190 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 5191 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 5192 div.d f0, f0, f1 # f0 <- f0 op f1 5193 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5194 GET_INST_OPCODE v0 # extract opcode from rINST 5195 SET_VREG_DOUBLE f0, a4 # vAA <- f0 5196 GOTO_OPCODE v0 # jump to next instruction 5197 5198 5199/* ------------------------------ */ 5200 .balign 128 5201.L_op_rem_double: /* 0xaf */ 5202/* File: mips64/op_rem_double.S */ 5203 /* rem-double vAA, vBB, vCC */ 5204 .extern fmod 5205 lbu a2, 2(rPC) # a2 <- BB 5206 lbu a3, 3(rPC) # a3 <- CC 5207 GET_VREG_DOUBLE f12, a2 # f12 <- vBB 5208 GET_VREG_DOUBLE f13, a3 # f13 <- vCC 5209 jal fmod # f0 <- f12 op f13 5210 srl a4, rINST, 8 # a4 <- AA 5211 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5212 GET_INST_OPCODE v0 # extract opcode from rINST 5213 SET_VREG_DOUBLE f0, a4 # vAA <- f0 5214 GOTO_OPCODE v0 # jump to next instruction 5215 5216/* ------------------------------ */ 5217 .balign 128 5218.L_op_add_int_2addr: /* 0xb0 */ 5219/* File: mips64/op_add_int_2addr.S */ 5220/* File: mips64/binop2addr.S */ 5221 /* 5222 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5223 * that specifies an instruction that performs "result = a0 op a1". 5224 * This could be a MIPS instruction or a function call. (If the result 5225 * comes back in a register other than a0, you can override "result".) 5226 * 5227 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5228 * vB (a1). Useful for integer division and modulus. Note that we 5229 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5230 * correctly. 5231 * 5232 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5233 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5234 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5235 */ 5236 /* binop/2addr vA, vB */ 5237 ext a2, rINST, 8, 4 # a2 <- A 5238 ext a3, rINST, 12, 4 # a3 <- B 5239 GET_VREG a0, a2 # a0 <- vA 5240 GET_VREG a1, a3 # a1 <- vB 5241 .if 0 5242 beqz a1, common_errDivideByZero # is second operand zero? 5243 .endif 5244 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5245 # optional op 5246 addu a0, a0, a1 # a0 <- op, a0-a3 changed 5247 GET_INST_OPCODE v0 # extract opcode from rINST 5248 SET_VREG a0, a2 # vA <- a0 5249 GOTO_OPCODE v0 # jump to next instruction 5250 5251 5252/* ------------------------------ */ 5253 .balign 128 5254.L_op_sub_int_2addr: /* 0xb1 */ 5255/* File: mips64/op_sub_int_2addr.S */ 5256/* File: mips64/binop2addr.S */ 5257 /* 5258 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5259 * that specifies an instruction that performs "result = a0 op a1". 5260 * This could be a MIPS instruction or a function call. (If the result 5261 * comes back in a register other than a0, you can override "result".) 5262 * 5263 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5264 * vB (a1). Useful for integer division and modulus. Note that we 5265 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5266 * correctly. 5267 * 5268 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5269 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5270 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5271 */ 5272 /* binop/2addr vA, vB */ 5273 ext a2, rINST, 8, 4 # a2 <- A 5274 ext a3, rINST, 12, 4 # a3 <- B 5275 GET_VREG a0, a2 # a0 <- vA 5276 GET_VREG a1, a3 # a1 <- vB 5277 .if 0 5278 beqz a1, common_errDivideByZero # is second operand zero? 5279 .endif 5280 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5281 # optional op 5282 subu a0, a0, a1 # a0 <- op, a0-a3 changed 5283 GET_INST_OPCODE v0 # extract opcode from rINST 5284 SET_VREG a0, a2 # vA <- a0 5285 GOTO_OPCODE v0 # jump to next instruction 5286 5287 5288/* ------------------------------ */ 5289 .balign 128 5290.L_op_mul_int_2addr: /* 0xb2 */ 5291/* File: mips64/op_mul_int_2addr.S */ 5292/* File: mips64/binop2addr.S */ 5293 /* 5294 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5295 * that specifies an instruction that performs "result = a0 op a1". 5296 * This could be a MIPS instruction or a function call. (If the result 5297 * comes back in a register other than a0, you can override "result".) 5298 * 5299 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5300 * vB (a1). Useful for integer division and modulus. Note that we 5301 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5302 * correctly. 5303 * 5304 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5305 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5306 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5307 */ 5308 /* binop/2addr vA, vB */ 5309 ext a2, rINST, 8, 4 # a2 <- A 5310 ext a3, rINST, 12, 4 # a3 <- B 5311 GET_VREG a0, a2 # a0 <- vA 5312 GET_VREG a1, a3 # a1 <- vB 5313 .if 0 5314 beqz a1, common_errDivideByZero # is second operand zero? 5315 .endif 5316 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5317 # optional op 5318 mul a0, a0, a1 # a0 <- op, a0-a3 changed 5319 GET_INST_OPCODE v0 # extract opcode from rINST 5320 SET_VREG a0, a2 # vA <- a0 5321 GOTO_OPCODE v0 # jump to next instruction 5322 5323 5324/* ------------------------------ */ 5325 .balign 128 5326.L_op_div_int_2addr: /* 0xb3 */ 5327/* File: mips64/op_div_int_2addr.S */ 5328/* File: mips64/binop2addr.S */ 5329 /* 5330 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5331 * that specifies an instruction that performs "result = a0 op a1". 5332 * This could be a MIPS instruction or a function call. (If the result 5333 * comes back in a register other than a0, you can override "result".) 5334 * 5335 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5336 * vB (a1). Useful for integer division and modulus. Note that we 5337 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5338 * correctly. 5339 * 5340 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5341 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5342 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5343 */ 5344 /* binop/2addr vA, vB */ 5345 ext a2, rINST, 8, 4 # a2 <- A 5346 ext a3, rINST, 12, 4 # a3 <- B 5347 GET_VREG a0, a2 # a0 <- vA 5348 GET_VREG a1, a3 # a1 <- vB 5349 .if 1 5350 beqz a1, common_errDivideByZero # is second operand zero? 5351 .endif 5352 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5353 # optional op 5354 div a0, a0, a1 # a0 <- op, a0-a3 changed 5355 GET_INST_OPCODE v0 # extract opcode from rINST 5356 SET_VREG a0, a2 # vA <- a0 5357 GOTO_OPCODE v0 # jump to next instruction 5358 5359 5360/* ------------------------------ */ 5361 .balign 128 5362.L_op_rem_int_2addr: /* 0xb4 */ 5363/* File: mips64/op_rem_int_2addr.S */ 5364/* File: mips64/binop2addr.S */ 5365 /* 5366 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5367 * that specifies an instruction that performs "result = a0 op a1". 5368 * This could be a MIPS instruction or a function call. (If the result 5369 * comes back in a register other than a0, you can override "result".) 5370 * 5371 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5372 * vB (a1). Useful for integer division and modulus. Note that we 5373 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5374 * correctly. 5375 * 5376 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5377 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5378 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5379 */ 5380 /* binop/2addr vA, vB */ 5381 ext a2, rINST, 8, 4 # a2 <- A 5382 ext a3, rINST, 12, 4 # a3 <- B 5383 GET_VREG a0, a2 # a0 <- vA 5384 GET_VREG a1, a3 # a1 <- vB 5385 .if 1 5386 beqz a1, common_errDivideByZero # is second operand zero? 5387 .endif 5388 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5389 # optional op 5390 mod a0, a0, a1 # a0 <- op, a0-a3 changed 5391 GET_INST_OPCODE v0 # extract opcode from rINST 5392 SET_VREG a0, a2 # vA <- a0 5393 GOTO_OPCODE v0 # jump to next instruction 5394 5395 5396/* ------------------------------ */ 5397 .balign 128 5398.L_op_and_int_2addr: /* 0xb5 */ 5399/* File: mips64/op_and_int_2addr.S */ 5400/* File: mips64/binop2addr.S */ 5401 /* 5402 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5403 * that specifies an instruction that performs "result = a0 op a1". 5404 * This could be a MIPS instruction or a function call. (If the result 5405 * comes back in a register other than a0, you can override "result".) 5406 * 5407 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5408 * vB (a1). Useful for integer division and modulus. Note that we 5409 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5410 * correctly. 5411 * 5412 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5413 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5414 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5415 */ 5416 /* binop/2addr vA, vB */ 5417 ext a2, rINST, 8, 4 # a2 <- A 5418 ext a3, rINST, 12, 4 # a3 <- B 5419 GET_VREG a0, a2 # a0 <- vA 5420 GET_VREG a1, a3 # a1 <- vB 5421 .if 0 5422 beqz a1, common_errDivideByZero # is second operand zero? 5423 .endif 5424 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5425 # optional op 5426 and a0, a0, a1 # a0 <- op, a0-a3 changed 5427 GET_INST_OPCODE v0 # extract opcode from rINST 5428 SET_VREG a0, a2 # vA <- a0 5429 GOTO_OPCODE v0 # jump to next instruction 5430 5431 5432/* ------------------------------ */ 5433 .balign 128 5434.L_op_or_int_2addr: /* 0xb6 */ 5435/* File: mips64/op_or_int_2addr.S */ 5436/* File: mips64/binop2addr.S */ 5437 /* 5438 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5439 * that specifies an instruction that performs "result = a0 op a1". 5440 * This could be a MIPS instruction or a function call. (If the result 5441 * comes back in a register other than a0, you can override "result".) 5442 * 5443 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5444 * vB (a1). Useful for integer division and modulus. Note that we 5445 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5446 * correctly. 5447 * 5448 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5449 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5450 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5451 */ 5452 /* binop/2addr vA, vB */ 5453 ext a2, rINST, 8, 4 # a2 <- A 5454 ext a3, rINST, 12, 4 # a3 <- B 5455 GET_VREG a0, a2 # a0 <- vA 5456 GET_VREG a1, a3 # a1 <- vB 5457 .if 0 5458 beqz a1, common_errDivideByZero # is second operand zero? 5459 .endif 5460 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5461 # optional op 5462 or a0, a0, a1 # a0 <- op, a0-a3 changed 5463 GET_INST_OPCODE v0 # extract opcode from rINST 5464 SET_VREG a0, a2 # vA <- a0 5465 GOTO_OPCODE v0 # jump to next instruction 5466 5467 5468/* ------------------------------ */ 5469 .balign 128 5470.L_op_xor_int_2addr: /* 0xb7 */ 5471/* File: mips64/op_xor_int_2addr.S */ 5472/* File: mips64/binop2addr.S */ 5473 /* 5474 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5475 * that specifies an instruction that performs "result = a0 op a1". 5476 * This could be a MIPS instruction or a function call. (If the result 5477 * comes back in a register other than a0, you can override "result".) 5478 * 5479 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5480 * vB (a1). Useful for integer division and modulus. Note that we 5481 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5482 * correctly. 5483 * 5484 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5485 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5486 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5487 */ 5488 /* binop/2addr vA, vB */ 5489 ext a2, rINST, 8, 4 # a2 <- A 5490 ext a3, rINST, 12, 4 # a3 <- B 5491 GET_VREG a0, a2 # a0 <- vA 5492 GET_VREG a1, a3 # a1 <- vB 5493 .if 0 5494 beqz a1, common_errDivideByZero # is second operand zero? 5495 .endif 5496 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5497 # optional op 5498 xor a0, a0, a1 # a0 <- op, a0-a3 changed 5499 GET_INST_OPCODE v0 # extract opcode from rINST 5500 SET_VREG a0, a2 # vA <- a0 5501 GOTO_OPCODE v0 # jump to next instruction 5502 5503 5504/* ------------------------------ */ 5505 .balign 128 5506.L_op_shl_int_2addr: /* 0xb8 */ 5507/* File: mips64/op_shl_int_2addr.S */ 5508/* File: mips64/binop2addr.S */ 5509 /* 5510 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5511 * that specifies an instruction that performs "result = a0 op a1". 5512 * This could be a MIPS instruction or a function call. (If the result 5513 * comes back in a register other than a0, you can override "result".) 5514 * 5515 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5516 * vB (a1). Useful for integer division and modulus. Note that we 5517 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5518 * correctly. 5519 * 5520 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5521 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5522 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5523 */ 5524 /* binop/2addr vA, vB */ 5525 ext a2, rINST, 8, 4 # a2 <- A 5526 ext a3, rINST, 12, 4 # a3 <- B 5527 GET_VREG a0, a2 # a0 <- vA 5528 GET_VREG a1, a3 # a1 <- vB 5529 .if 0 5530 beqz a1, common_errDivideByZero # is second operand zero? 5531 .endif 5532 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5533 # optional op 5534 sll a0, a0, a1 # a0 <- op, a0-a3 changed 5535 GET_INST_OPCODE v0 # extract opcode from rINST 5536 SET_VREG a0, a2 # vA <- a0 5537 GOTO_OPCODE v0 # jump to next instruction 5538 5539 5540/* ------------------------------ */ 5541 .balign 128 5542.L_op_shr_int_2addr: /* 0xb9 */ 5543/* File: mips64/op_shr_int_2addr.S */ 5544/* File: mips64/binop2addr.S */ 5545 /* 5546 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5547 * that specifies an instruction that performs "result = a0 op a1". 5548 * This could be a MIPS instruction or a function call. (If the result 5549 * comes back in a register other than a0, you can override "result".) 5550 * 5551 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5552 * vB (a1). Useful for integer division and modulus. Note that we 5553 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5554 * correctly. 5555 * 5556 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5557 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5558 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5559 */ 5560 /* binop/2addr vA, vB */ 5561 ext a2, rINST, 8, 4 # a2 <- A 5562 ext a3, rINST, 12, 4 # a3 <- B 5563 GET_VREG a0, a2 # a0 <- vA 5564 GET_VREG a1, a3 # a1 <- vB 5565 .if 0 5566 beqz a1, common_errDivideByZero # is second operand zero? 5567 .endif 5568 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5569 # optional op 5570 sra a0, a0, a1 # a0 <- op, a0-a3 changed 5571 GET_INST_OPCODE v0 # extract opcode from rINST 5572 SET_VREG a0, a2 # vA <- a0 5573 GOTO_OPCODE v0 # jump to next instruction 5574 5575 5576/* ------------------------------ */ 5577 .balign 128 5578.L_op_ushr_int_2addr: /* 0xba */ 5579/* File: mips64/op_ushr_int_2addr.S */ 5580/* File: mips64/binop2addr.S */ 5581 /* 5582 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5583 * that specifies an instruction that performs "result = a0 op a1". 5584 * This could be a MIPS instruction or a function call. (If the result 5585 * comes back in a register other than a0, you can override "result".) 5586 * 5587 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5588 * vB (a1). Useful for integer division and modulus. Note that we 5589 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5590 * correctly. 5591 * 5592 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5593 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5594 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5595 */ 5596 /* binop/2addr vA, vB */ 5597 ext a2, rINST, 8, 4 # a2 <- A 5598 ext a3, rINST, 12, 4 # a3 <- B 5599 GET_VREG a0, a2 # a0 <- vA 5600 GET_VREG a1, a3 # a1 <- vB 5601 .if 0 5602 beqz a1, common_errDivideByZero # is second operand zero? 5603 .endif 5604 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5605 # optional op 5606 srl a0, a0, a1 # a0 <- op, a0-a3 changed 5607 GET_INST_OPCODE v0 # extract opcode from rINST 5608 SET_VREG a0, a2 # vA <- a0 5609 GOTO_OPCODE v0 # jump to next instruction 5610 5611 5612/* ------------------------------ */ 5613 .balign 128 5614.L_op_add_long_2addr: /* 0xbb */ 5615/* File: mips64/op_add_long_2addr.S */ 5616/* File: mips64/binopWide2addr.S */ 5617 /* 5618 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5619 * that specifies an instruction that performs "result = a0 op a1". 5620 * This could be a MIPS instruction or a function call. (If the result 5621 * comes back in a register other than a0, you can override "result".) 5622 * 5623 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5624 * vB (a1). Useful for integer division and modulus. Note that we 5625 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5626 * correctly. 5627 * 5628 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5629 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5630 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5631 */ 5632 /* binop/2addr vA, vB */ 5633 ext a2, rINST, 8, 4 # a2 <- A 5634 ext a3, rINST, 12, 4 # a3 <- B 5635 GET_VREG_WIDE a0, a2 # a0 <- vA 5636 GET_VREG_WIDE a1, a3 # a1 <- vB 5637 .if 0 5638 beqz a1, common_errDivideByZero # is second operand zero? 5639 .endif 5640 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5641 # optional op 5642 daddu a0, a0, a1 # a0 <- op, a0-a3 changed 5643 GET_INST_OPCODE v0 # extract opcode from rINST 5644 SET_VREG_WIDE a0, a2 # vA <- a0 5645 GOTO_OPCODE v0 # jump to next instruction 5646 5647 5648/* ------------------------------ */ 5649 .balign 128 5650.L_op_sub_long_2addr: /* 0xbc */ 5651/* File: mips64/op_sub_long_2addr.S */ 5652/* File: mips64/binopWide2addr.S */ 5653 /* 5654 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5655 * that specifies an instruction that performs "result = a0 op a1". 5656 * This could be a MIPS instruction or a function call. (If the result 5657 * comes back in a register other than a0, you can override "result".) 5658 * 5659 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5660 * vB (a1). Useful for integer division and modulus. Note that we 5661 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5662 * correctly. 5663 * 5664 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5665 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5666 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5667 */ 5668 /* binop/2addr vA, vB */ 5669 ext a2, rINST, 8, 4 # a2 <- A 5670 ext a3, rINST, 12, 4 # a3 <- B 5671 GET_VREG_WIDE a0, a2 # a0 <- vA 5672 GET_VREG_WIDE a1, a3 # a1 <- vB 5673 .if 0 5674 beqz a1, common_errDivideByZero # is second operand zero? 5675 .endif 5676 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5677 # optional op 5678 dsubu a0, a0, a1 # a0 <- op, a0-a3 changed 5679 GET_INST_OPCODE v0 # extract opcode from rINST 5680 SET_VREG_WIDE a0, a2 # vA <- a0 5681 GOTO_OPCODE v0 # jump to next instruction 5682 5683 5684/* ------------------------------ */ 5685 .balign 128 5686.L_op_mul_long_2addr: /* 0xbd */ 5687/* File: mips64/op_mul_long_2addr.S */ 5688/* File: mips64/binopWide2addr.S */ 5689 /* 5690 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5691 * that specifies an instruction that performs "result = a0 op a1". 5692 * This could be a MIPS instruction or a function call. (If the result 5693 * comes back in a register other than a0, you can override "result".) 5694 * 5695 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5696 * vB (a1). Useful for integer division and modulus. Note that we 5697 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5698 * correctly. 5699 * 5700 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5701 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5702 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5703 */ 5704 /* binop/2addr vA, vB */ 5705 ext a2, rINST, 8, 4 # a2 <- A 5706 ext a3, rINST, 12, 4 # a3 <- B 5707 GET_VREG_WIDE a0, a2 # a0 <- vA 5708 GET_VREG_WIDE a1, a3 # a1 <- vB 5709 .if 0 5710 beqz a1, common_errDivideByZero # is second operand zero? 5711 .endif 5712 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5713 # optional op 5714 dmul a0, a0, a1 # a0 <- op, a0-a3 changed 5715 GET_INST_OPCODE v0 # extract opcode from rINST 5716 SET_VREG_WIDE a0, a2 # vA <- a0 5717 GOTO_OPCODE v0 # jump to next instruction 5718 5719 5720/* ------------------------------ */ 5721 .balign 128 5722.L_op_div_long_2addr: /* 0xbe */ 5723/* File: mips64/op_div_long_2addr.S */ 5724/* File: mips64/binopWide2addr.S */ 5725 /* 5726 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5727 * that specifies an instruction that performs "result = a0 op a1". 5728 * This could be a MIPS instruction or a function call. (If the result 5729 * comes back in a register other than a0, you can override "result".) 5730 * 5731 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5732 * vB (a1). Useful for integer division and modulus. Note that we 5733 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5734 * correctly. 5735 * 5736 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5737 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5738 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5739 */ 5740 /* binop/2addr vA, vB */ 5741 ext a2, rINST, 8, 4 # a2 <- A 5742 ext a3, rINST, 12, 4 # a3 <- B 5743 GET_VREG_WIDE a0, a2 # a0 <- vA 5744 GET_VREG_WIDE a1, a3 # a1 <- vB 5745 .if 1 5746 beqz a1, common_errDivideByZero # is second operand zero? 5747 .endif 5748 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5749 # optional op 5750 ddiv a0, a0, a1 # a0 <- op, a0-a3 changed 5751 GET_INST_OPCODE v0 # extract opcode from rINST 5752 SET_VREG_WIDE a0, a2 # vA <- a0 5753 GOTO_OPCODE v0 # jump to next instruction 5754 5755 5756/* ------------------------------ */ 5757 .balign 128 5758.L_op_rem_long_2addr: /* 0xbf */ 5759/* File: mips64/op_rem_long_2addr.S */ 5760/* File: mips64/binopWide2addr.S */ 5761 /* 5762 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5763 * that specifies an instruction that performs "result = a0 op a1". 5764 * This could be a MIPS instruction or a function call. (If the result 5765 * comes back in a register other than a0, you can override "result".) 5766 * 5767 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5768 * vB (a1). Useful for integer division and modulus. Note that we 5769 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5770 * correctly. 5771 * 5772 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5773 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5774 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5775 */ 5776 /* binop/2addr vA, vB */ 5777 ext a2, rINST, 8, 4 # a2 <- A 5778 ext a3, rINST, 12, 4 # a3 <- B 5779 GET_VREG_WIDE a0, a2 # a0 <- vA 5780 GET_VREG_WIDE a1, a3 # a1 <- vB 5781 .if 1 5782 beqz a1, common_errDivideByZero # is second operand zero? 5783 .endif 5784 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5785 # optional op 5786 dmod a0, a0, a1 # a0 <- op, a0-a3 changed 5787 GET_INST_OPCODE v0 # extract opcode from rINST 5788 SET_VREG_WIDE a0, a2 # vA <- a0 5789 GOTO_OPCODE v0 # jump to next instruction 5790 5791 5792/* ------------------------------ */ 5793 .balign 128 5794.L_op_and_long_2addr: /* 0xc0 */ 5795/* File: mips64/op_and_long_2addr.S */ 5796/* File: mips64/binopWide2addr.S */ 5797 /* 5798 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5799 * that specifies an instruction that performs "result = a0 op a1". 5800 * This could be a MIPS instruction or a function call. (If the result 5801 * comes back in a register other than a0, you can override "result".) 5802 * 5803 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5804 * vB (a1). Useful for integer division and modulus. Note that we 5805 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5806 * correctly. 5807 * 5808 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5809 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5810 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5811 */ 5812 /* binop/2addr vA, vB */ 5813 ext a2, rINST, 8, 4 # a2 <- A 5814 ext a3, rINST, 12, 4 # a3 <- B 5815 GET_VREG_WIDE a0, a2 # a0 <- vA 5816 GET_VREG_WIDE a1, a3 # a1 <- vB 5817 .if 0 5818 beqz a1, common_errDivideByZero # is second operand zero? 5819 .endif 5820 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5821 # optional op 5822 and a0, a0, a1 # a0 <- op, a0-a3 changed 5823 GET_INST_OPCODE v0 # extract opcode from rINST 5824 SET_VREG_WIDE a0, a2 # vA <- a0 5825 GOTO_OPCODE v0 # jump to next instruction 5826 5827 5828/* ------------------------------ */ 5829 .balign 128 5830.L_op_or_long_2addr: /* 0xc1 */ 5831/* File: mips64/op_or_long_2addr.S */ 5832/* File: mips64/binopWide2addr.S */ 5833 /* 5834 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5835 * that specifies an instruction that performs "result = a0 op a1". 5836 * This could be a MIPS instruction or a function call. (If the result 5837 * comes back in a register other than a0, you can override "result".) 5838 * 5839 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5840 * vB (a1). Useful for integer division and modulus. Note that we 5841 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5842 * correctly. 5843 * 5844 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5845 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5846 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5847 */ 5848 /* binop/2addr vA, vB */ 5849 ext a2, rINST, 8, 4 # a2 <- A 5850 ext a3, rINST, 12, 4 # a3 <- B 5851 GET_VREG_WIDE a0, a2 # a0 <- vA 5852 GET_VREG_WIDE a1, a3 # a1 <- vB 5853 .if 0 5854 beqz a1, common_errDivideByZero # is second operand zero? 5855 .endif 5856 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5857 # optional op 5858 or a0, a0, a1 # a0 <- op, a0-a3 changed 5859 GET_INST_OPCODE v0 # extract opcode from rINST 5860 SET_VREG_WIDE a0, a2 # vA <- a0 5861 GOTO_OPCODE v0 # jump to next instruction 5862 5863 5864/* ------------------------------ */ 5865 .balign 128 5866.L_op_xor_long_2addr: /* 0xc2 */ 5867/* File: mips64/op_xor_long_2addr.S */ 5868/* File: mips64/binopWide2addr.S */ 5869 /* 5870 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5871 * that specifies an instruction that performs "result = a0 op a1". 5872 * This could be a MIPS instruction or a function call. (If the result 5873 * comes back in a register other than a0, you can override "result".) 5874 * 5875 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5876 * vB (a1). Useful for integer division and modulus. Note that we 5877 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5878 * correctly. 5879 * 5880 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5881 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5882 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5883 */ 5884 /* binop/2addr vA, vB */ 5885 ext a2, rINST, 8, 4 # a2 <- A 5886 ext a3, rINST, 12, 4 # a3 <- B 5887 GET_VREG_WIDE a0, a2 # a0 <- vA 5888 GET_VREG_WIDE a1, a3 # a1 <- vB 5889 .if 0 5890 beqz a1, common_errDivideByZero # is second operand zero? 5891 .endif 5892 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5893 # optional op 5894 xor a0, a0, a1 # a0 <- op, a0-a3 changed 5895 GET_INST_OPCODE v0 # extract opcode from rINST 5896 SET_VREG_WIDE a0, a2 # vA <- a0 5897 GOTO_OPCODE v0 # jump to next instruction 5898 5899 5900/* ------------------------------ */ 5901 .balign 128 5902.L_op_shl_long_2addr: /* 0xc3 */ 5903/* File: mips64/op_shl_long_2addr.S */ 5904/* File: mips64/binopWide2addr.S */ 5905 /* 5906 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5907 * that specifies an instruction that performs "result = a0 op a1". 5908 * This could be a MIPS instruction or a function call. (If the result 5909 * comes back in a register other than a0, you can override "result".) 5910 * 5911 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5912 * vB (a1). Useful for integer division and modulus. Note that we 5913 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5914 * correctly. 5915 * 5916 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5917 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5918 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5919 */ 5920 /* binop/2addr vA, vB */ 5921 ext a2, rINST, 8, 4 # a2 <- A 5922 ext a3, rINST, 12, 4 # a3 <- B 5923 GET_VREG_WIDE a0, a2 # a0 <- vA 5924 GET_VREG_WIDE a1, a3 # a1 <- vB 5925 .if 0 5926 beqz a1, common_errDivideByZero # is second operand zero? 5927 .endif 5928 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5929 # optional op 5930 dsll a0, a0, a1 # a0 <- op, a0-a3 changed 5931 GET_INST_OPCODE v0 # extract opcode from rINST 5932 SET_VREG_WIDE a0, a2 # vA <- a0 5933 GOTO_OPCODE v0 # jump to next instruction 5934 5935 5936/* ------------------------------ */ 5937 .balign 128 5938.L_op_shr_long_2addr: /* 0xc4 */ 5939/* File: mips64/op_shr_long_2addr.S */ 5940/* File: mips64/binopWide2addr.S */ 5941 /* 5942 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5943 * that specifies an instruction that performs "result = a0 op a1". 5944 * This could be a MIPS instruction or a function call. (If the result 5945 * comes back in a register other than a0, you can override "result".) 5946 * 5947 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5948 * vB (a1). Useful for integer division and modulus. Note that we 5949 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5950 * correctly. 5951 * 5952 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5953 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5954 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5955 */ 5956 /* binop/2addr vA, vB */ 5957 ext a2, rINST, 8, 4 # a2 <- A 5958 ext a3, rINST, 12, 4 # a3 <- B 5959 GET_VREG_WIDE a0, a2 # a0 <- vA 5960 GET_VREG_WIDE a1, a3 # a1 <- vB 5961 .if 0 5962 beqz a1, common_errDivideByZero # is second operand zero? 5963 .endif 5964 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5965 # optional op 5966 dsra a0, a0, a1 # a0 <- op, a0-a3 changed 5967 GET_INST_OPCODE v0 # extract opcode from rINST 5968 SET_VREG_WIDE a0, a2 # vA <- a0 5969 GOTO_OPCODE v0 # jump to next instruction 5970 5971 5972/* ------------------------------ */ 5973 .balign 128 5974.L_op_ushr_long_2addr: /* 0xc5 */ 5975/* File: mips64/op_ushr_long_2addr.S */ 5976/* File: mips64/binopWide2addr.S */ 5977 /* 5978 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5979 * that specifies an instruction that performs "result = a0 op a1". 5980 * This could be a MIPS instruction or a function call. (If the result 5981 * comes back in a register other than a0, you can override "result".) 5982 * 5983 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5984 * vB (a1). Useful for integer division and modulus. Note that we 5985 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5986 * correctly. 5987 * 5988 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5989 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5990 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5991 */ 5992 /* binop/2addr vA, vB */ 5993 ext a2, rINST, 8, 4 # a2 <- A 5994 ext a3, rINST, 12, 4 # a3 <- B 5995 GET_VREG_WIDE a0, a2 # a0 <- vA 5996 GET_VREG_WIDE a1, a3 # a1 <- vB 5997 .if 0 5998 beqz a1, common_errDivideByZero # is second operand zero? 5999 .endif 6000 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6001 # optional op 6002 dsrl a0, a0, a1 # a0 <- op, a0-a3 changed 6003 GET_INST_OPCODE v0 # extract opcode from rINST 6004 SET_VREG_WIDE a0, a2 # vA <- a0 6005 GOTO_OPCODE v0 # jump to next instruction 6006 6007 6008/* ------------------------------ */ 6009 .balign 128 6010.L_op_add_float_2addr: /* 0xc6 */ 6011/* File: mips64/op_add_float_2addr.S */ 6012/* File: mips64/fbinop2addr.S */ 6013 /*: 6014 * Generic 32-bit "/2addr" floating-point operation. 6015 * 6016 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 6017 * form: <op> f0, f0, f1 6018 */ 6019 /* binop/2addr vA, vB */ 6020 ext a2, rINST, 8, 4 # a2 <- A 6021 ext a3, rINST, 12, 4 # a3 <- B 6022 GET_VREG_FLOAT f0, a2 # f0 <- vA 6023 GET_VREG_FLOAT f1, a3 # f1 <- vB 6024 add.s f0, f0, f1 # f0 <- f0 op f1 6025 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6026 GET_INST_OPCODE v0 # extract opcode from rINST 6027 SET_VREG_FLOAT f0, a2 # vA <- f0 6028 GOTO_OPCODE v0 # jump to next instruction 6029 6030 6031/* ------------------------------ */ 6032 .balign 128 6033.L_op_sub_float_2addr: /* 0xc7 */ 6034/* File: mips64/op_sub_float_2addr.S */ 6035/* File: mips64/fbinop2addr.S */ 6036 /*: 6037 * Generic 32-bit "/2addr" floating-point operation. 6038 * 6039 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 6040 * form: <op> f0, f0, f1 6041 */ 6042 /* binop/2addr vA, vB */ 6043 ext a2, rINST, 8, 4 # a2 <- A 6044 ext a3, rINST, 12, 4 # a3 <- B 6045 GET_VREG_FLOAT f0, a2 # f0 <- vA 6046 GET_VREG_FLOAT f1, a3 # f1 <- vB 6047 sub.s f0, f0, f1 # f0 <- f0 op f1 6048 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6049 GET_INST_OPCODE v0 # extract opcode from rINST 6050 SET_VREG_FLOAT f0, a2 # vA <- f0 6051 GOTO_OPCODE v0 # jump to next instruction 6052 6053 6054/* ------------------------------ */ 6055 .balign 128 6056.L_op_mul_float_2addr: /* 0xc8 */ 6057/* File: mips64/op_mul_float_2addr.S */ 6058/* File: mips64/fbinop2addr.S */ 6059 /*: 6060 * Generic 32-bit "/2addr" floating-point operation. 6061 * 6062 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 6063 * form: <op> f0, f0, f1 6064 */ 6065 /* binop/2addr vA, vB */ 6066 ext a2, rINST, 8, 4 # a2 <- A 6067 ext a3, rINST, 12, 4 # a3 <- B 6068 GET_VREG_FLOAT f0, a2 # f0 <- vA 6069 GET_VREG_FLOAT f1, a3 # f1 <- vB 6070 mul.s f0, f0, f1 # f0 <- f0 op f1 6071 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6072 GET_INST_OPCODE v0 # extract opcode from rINST 6073 SET_VREG_FLOAT f0, a2 # vA <- f0 6074 GOTO_OPCODE v0 # jump to next instruction 6075 6076 6077/* ------------------------------ */ 6078 .balign 128 6079.L_op_div_float_2addr: /* 0xc9 */ 6080/* File: mips64/op_div_float_2addr.S */ 6081/* File: mips64/fbinop2addr.S */ 6082 /*: 6083 * Generic 32-bit "/2addr" floating-point operation. 6084 * 6085 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 6086 * form: <op> f0, f0, f1 6087 */ 6088 /* binop/2addr vA, vB */ 6089 ext a2, rINST, 8, 4 # a2 <- A 6090 ext a3, rINST, 12, 4 # a3 <- B 6091 GET_VREG_FLOAT f0, a2 # f0 <- vA 6092 GET_VREG_FLOAT f1, a3 # f1 <- vB 6093 div.s f0, f0, f1 # f0 <- f0 op f1 6094 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6095 GET_INST_OPCODE v0 # extract opcode from rINST 6096 SET_VREG_FLOAT f0, a2 # vA <- f0 6097 GOTO_OPCODE v0 # jump to next instruction 6098 6099 6100/* ------------------------------ */ 6101 .balign 128 6102.L_op_rem_float_2addr: /* 0xca */ 6103/* File: mips64/op_rem_float_2addr.S */ 6104 /* rem-float/2addr vA, vB */ 6105 .extern fmodf 6106 ext a2, rINST, 8, 4 # a2 <- A 6107 ext a3, rINST, 12, 4 # a3 <- B 6108 GET_VREG_FLOAT f12, a2 # f12 <- vA 6109 GET_VREG_FLOAT f13, a3 # f13 <- vB 6110 jal fmodf # f0 <- f12 op f13 6111 ext a2, rINST, 8, 4 # a2 <- A 6112 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6113 GET_INST_OPCODE v0 # extract opcode from rINST 6114 SET_VREG_FLOAT f0, a2 # vA <- f0 6115 GOTO_OPCODE v0 # jump to next instruction 6116 6117/* ------------------------------ */ 6118 .balign 128 6119.L_op_add_double_2addr: /* 0xcb */ 6120/* File: mips64/op_add_double_2addr.S */ 6121/* File: mips64/fbinopWide2addr.S */ 6122 /*: 6123 * Generic 64-bit "/2addr" floating-point operation. 6124 * 6125 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 6126 * form: <op> f0, f0, f1 6127 */ 6128 /* binop/2addr vA, vB */ 6129 ext a2, rINST, 8, 4 # a2 <- A 6130 ext a3, rINST, 12, 4 # a3 <- B 6131 GET_VREG_DOUBLE f0, a2 # f0 <- vA 6132 GET_VREG_DOUBLE f1, a3 # f1 <- vB 6133 add.d f0, f0, f1 # f0 <- f0 op f1 6134 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6135 GET_INST_OPCODE v0 # extract opcode from rINST 6136 SET_VREG_DOUBLE f0, a2 # vA <- f0 6137 GOTO_OPCODE v0 # jump to next instruction 6138 6139 6140/* ------------------------------ */ 6141 .balign 128 6142.L_op_sub_double_2addr: /* 0xcc */ 6143/* File: mips64/op_sub_double_2addr.S */ 6144/* File: mips64/fbinopWide2addr.S */ 6145 /*: 6146 * Generic 64-bit "/2addr" floating-point operation. 6147 * 6148 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 6149 * form: <op> f0, f0, f1 6150 */ 6151 /* binop/2addr vA, vB */ 6152 ext a2, rINST, 8, 4 # a2 <- A 6153 ext a3, rINST, 12, 4 # a3 <- B 6154 GET_VREG_DOUBLE f0, a2 # f0 <- vA 6155 GET_VREG_DOUBLE f1, a3 # f1 <- vB 6156 sub.d f0, f0, f1 # f0 <- f0 op f1 6157 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6158 GET_INST_OPCODE v0 # extract opcode from rINST 6159 SET_VREG_DOUBLE f0, a2 # vA <- f0 6160 GOTO_OPCODE v0 # jump to next instruction 6161 6162 6163/* ------------------------------ */ 6164 .balign 128 6165.L_op_mul_double_2addr: /* 0xcd */ 6166/* File: mips64/op_mul_double_2addr.S */ 6167/* File: mips64/fbinopWide2addr.S */ 6168 /*: 6169 * Generic 64-bit "/2addr" floating-point operation. 6170 * 6171 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 6172 * form: <op> f0, f0, f1 6173 */ 6174 /* binop/2addr vA, vB */ 6175 ext a2, rINST, 8, 4 # a2 <- A 6176 ext a3, rINST, 12, 4 # a3 <- B 6177 GET_VREG_DOUBLE f0, a2 # f0 <- vA 6178 GET_VREG_DOUBLE f1, a3 # f1 <- vB 6179 mul.d f0, f0, f1 # f0 <- f0 op f1 6180 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6181 GET_INST_OPCODE v0 # extract opcode from rINST 6182 SET_VREG_DOUBLE f0, a2 # vA <- f0 6183 GOTO_OPCODE v0 # jump to next instruction 6184 6185 6186/* ------------------------------ */ 6187 .balign 128 6188.L_op_div_double_2addr: /* 0xce */ 6189/* File: mips64/op_div_double_2addr.S */ 6190/* File: mips64/fbinopWide2addr.S */ 6191 /*: 6192 * Generic 64-bit "/2addr" floating-point operation. 6193 * 6194 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 6195 * form: <op> f0, f0, f1 6196 */ 6197 /* binop/2addr vA, vB */ 6198 ext a2, rINST, 8, 4 # a2 <- A 6199 ext a3, rINST, 12, 4 # a3 <- B 6200 GET_VREG_DOUBLE f0, a2 # f0 <- vA 6201 GET_VREG_DOUBLE f1, a3 # f1 <- vB 6202 div.d f0, f0, f1 # f0 <- f0 op f1 6203 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6204 GET_INST_OPCODE v0 # extract opcode from rINST 6205 SET_VREG_DOUBLE f0, a2 # vA <- f0 6206 GOTO_OPCODE v0 # jump to next instruction 6207 6208 6209/* ------------------------------ */ 6210 .balign 128 6211.L_op_rem_double_2addr: /* 0xcf */ 6212/* File: mips64/op_rem_double_2addr.S */ 6213 /* rem-double/2addr vA, vB */ 6214 .extern fmod 6215 ext a2, rINST, 8, 4 # a2 <- A 6216 ext a3, rINST, 12, 4 # a3 <- B 6217 GET_VREG_DOUBLE f12, a2 # f12 <- vA 6218 GET_VREG_DOUBLE f13, a3 # f13 <- vB 6219 jal fmod # f0 <- f12 op f13 6220 ext a2, rINST, 8, 4 # a2 <- A 6221 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6222 GET_INST_OPCODE v0 # extract opcode from rINST 6223 SET_VREG_DOUBLE f0, a2 # vA <- f0 6224 GOTO_OPCODE v0 # jump to next instruction 6225 6226/* ------------------------------ */ 6227 .balign 128 6228.L_op_add_int_lit16: /* 0xd0 */ 6229/* File: mips64/op_add_int_lit16.S */ 6230/* File: mips64/binopLit16.S */ 6231 /* 6232 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6233 * that specifies an instruction that performs "result = a0 op a1". 6234 * This could be an MIPS instruction or a function call. (If the result 6235 * comes back in a register other than a0, you can override "result".) 6236 * 6237 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6238 * CCCC (a1). Useful for integer division and modulus. 6239 * 6240 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6241 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6242 */ 6243 /* binop/lit16 vA, vB, #+CCCC */ 6244 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6245 ext a2, rINST, 8, 4 # a2 <- A 6246 ext a3, rINST, 12, 4 # a3 <- B 6247 GET_VREG a0, a3 # a0 <- vB 6248 .if 0 6249 beqz a1, common_errDivideByZero # is second operand zero? 6250 .endif 6251 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6252 # optional op 6253 addu a0, a0, a1 # a0 <- op, a0-a3 changed 6254 GET_INST_OPCODE v0 # extract opcode from rINST 6255 SET_VREG a0, a2 # vA <- a0 6256 GOTO_OPCODE v0 # jump to next instruction 6257 6258 6259 6260/* ------------------------------ */ 6261 .balign 128 6262.L_op_rsub_int: /* 0xd1 */ 6263/* File: mips64/op_rsub_int.S */ 6264/* File: mips64/binopLit16.S */ 6265 /* 6266 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6267 * that specifies an instruction that performs "result = a0 op a1". 6268 * This could be an MIPS instruction or a function call. (If the result 6269 * comes back in a register other than a0, you can override "result".) 6270 * 6271 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6272 * CCCC (a1). Useful for integer division and modulus. 6273 * 6274 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6275 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6276 */ 6277 /* binop/lit16 vA, vB, #+CCCC */ 6278 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6279 ext a2, rINST, 8, 4 # a2 <- A 6280 ext a3, rINST, 12, 4 # a3 <- B 6281 GET_VREG a0, a3 # a0 <- vB 6282 .if 0 6283 beqz a1, common_errDivideByZero # is second operand zero? 6284 .endif 6285 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6286 # optional op 6287 subu a0, a1, a0 # a0 <- op, a0-a3 changed 6288 GET_INST_OPCODE v0 # extract opcode from rINST 6289 SET_VREG a0, a2 # vA <- a0 6290 GOTO_OPCODE v0 # jump to next instruction 6291 6292 6293 6294/* ------------------------------ */ 6295 .balign 128 6296.L_op_mul_int_lit16: /* 0xd2 */ 6297/* File: mips64/op_mul_int_lit16.S */ 6298/* File: mips64/binopLit16.S */ 6299 /* 6300 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6301 * that specifies an instruction that performs "result = a0 op a1". 6302 * This could be an MIPS instruction or a function call. (If the result 6303 * comes back in a register other than a0, you can override "result".) 6304 * 6305 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6306 * CCCC (a1). Useful for integer division and modulus. 6307 * 6308 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6309 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6310 */ 6311 /* binop/lit16 vA, vB, #+CCCC */ 6312 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6313 ext a2, rINST, 8, 4 # a2 <- A 6314 ext a3, rINST, 12, 4 # a3 <- B 6315 GET_VREG a0, a3 # a0 <- vB 6316 .if 0 6317 beqz a1, common_errDivideByZero # is second operand zero? 6318 .endif 6319 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6320 # optional op 6321 mul a0, a0, a1 # a0 <- op, a0-a3 changed 6322 GET_INST_OPCODE v0 # extract opcode from rINST 6323 SET_VREG a0, a2 # vA <- a0 6324 GOTO_OPCODE v0 # jump to next instruction 6325 6326 6327 6328/* ------------------------------ */ 6329 .balign 128 6330.L_op_div_int_lit16: /* 0xd3 */ 6331/* File: mips64/op_div_int_lit16.S */ 6332/* File: mips64/binopLit16.S */ 6333 /* 6334 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6335 * that specifies an instruction that performs "result = a0 op a1". 6336 * This could be an MIPS instruction or a function call. (If the result 6337 * comes back in a register other than a0, you can override "result".) 6338 * 6339 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6340 * CCCC (a1). Useful for integer division and modulus. 6341 * 6342 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6343 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6344 */ 6345 /* binop/lit16 vA, vB, #+CCCC */ 6346 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6347 ext a2, rINST, 8, 4 # a2 <- A 6348 ext a3, rINST, 12, 4 # a3 <- B 6349 GET_VREG a0, a3 # a0 <- vB 6350 .if 1 6351 beqz a1, common_errDivideByZero # is second operand zero? 6352 .endif 6353 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6354 # optional op 6355 div a0, a0, a1 # a0 <- op, a0-a3 changed 6356 GET_INST_OPCODE v0 # extract opcode from rINST 6357 SET_VREG a0, a2 # vA <- a0 6358 GOTO_OPCODE v0 # jump to next instruction 6359 6360 6361 6362/* ------------------------------ */ 6363 .balign 128 6364.L_op_rem_int_lit16: /* 0xd4 */ 6365/* File: mips64/op_rem_int_lit16.S */ 6366/* File: mips64/binopLit16.S */ 6367 /* 6368 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6369 * that specifies an instruction that performs "result = a0 op a1". 6370 * This could be an MIPS instruction or a function call. (If the result 6371 * comes back in a register other than a0, you can override "result".) 6372 * 6373 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6374 * CCCC (a1). Useful for integer division and modulus. 6375 * 6376 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6377 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6378 */ 6379 /* binop/lit16 vA, vB, #+CCCC */ 6380 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6381 ext a2, rINST, 8, 4 # a2 <- A 6382 ext a3, rINST, 12, 4 # a3 <- B 6383 GET_VREG a0, a3 # a0 <- vB 6384 .if 1 6385 beqz a1, common_errDivideByZero # is second operand zero? 6386 .endif 6387 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6388 # optional op 6389 mod a0, a0, a1 # a0 <- op, a0-a3 changed 6390 GET_INST_OPCODE v0 # extract opcode from rINST 6391 SET_VREG a0, a2 # vA <- a0 6392 GOTO_OPCODE v0 # jump to next instruction 6393 6394 6395 6396/* ------------------------------ */ 6397 .balign 128 6398.L_op_and_int_lit16: /* 0xd5 */ 6399/* File: mips64/op_and_int_lit16.S */ 6400/* File: mips64/binopLit16.S */ 6401 /* 6402 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6403 * that specifies an instruction that performs "result = a0 op a1". 6404 * This could be an MIPS instruction or a function call. (If the result 6405 * comes back in a register other than a0, you can override "result".) 6406 * 6407 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6408 * CCCC (a1). Useful for integer division and modulus. 6409 * 6410 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6411 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6412 */ 6413 /* binop/lit16 vA, vB, #+CCCC */ 6414 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6415 ext a2, rINST, 8, 4 # a2 <- A 6416 ext a3, rINST, 12, 4 # a3 <- B 6417 GET_VREG a0, a3 # a0 <- vB 6418 .if 0 6419 beqz a1, common_errDivideByZero # is second operand zero? 6420 .endif 6421 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6422 # optional op 6423 and a0, a0, a1 # a0 <- op, a0-a3 changed 6424 GET_INST_OPCODE v0 # extract opcode from rINST 6425 SET_VREG a0, a2 # vA <- a0 6426 GOTO_OPCODE v0 # jump to next instruction 6427 6428 6429 6430/* ------------------------------ */ 6431 .balign 128 6432.L_op_or_int_lit16: /* 0xd6 */ 6433/* File: mips64/op_or_int_lit16.S */ 6434/* File: mips64/binopLit16.S */ 6435 /* 6436 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6437 * that specifies an instruction that performs "result = a0 op a1". 6438 * This could be an MIPS instruction or a function call. (If the result 6439 * comes back in a register other than a0, you can override "result".) 6440 * 6441 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6442 * CCCC (a1). Useful for integer division and modulus. 6443 * 6444 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6445 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6446 */ 6447 /* binop/lit16 vA, vB, #+CCCC */ 6448 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6449 ext a2, rINST, 8, 4 # a2 <- A 6450 ext a3, rINST, 12, 4 # a3 <- B 6451 GET_VREG a0, a3 # a0 <- vB 6452 .if 0 6453 beqz a1, common_errDivideByZero # is second operand zero? 6454 .endif 6455 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6456 # optional op 6457 or a0, a0, a1 # a0 <- op, a0-a3 changed 6458 GET_INST_OPCODE v0 # extract opcode from rINST 6459 SET_VREG a0, a2 # vA <- a0 6460 GOTO_OPCODE v0 # jump to next instruction 6461 6462 6463 6464/* ------------------------------ */ 6465 .balign 128 6466.L_op_xor_int_lit16: /* 0xd7 */ 6467/* File: mips64/op_xor_int_lit16.S */ 6468/* File: mips64/binopLit16.S */ 6469 /* 6470 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6471 * that specifies an instruction that performs "result = a0 op a1". 6472 * This could be an MIPS instruction or a function call. (If the result 6473 * comes back in a register other than a0, you can override "result".) 6474 * 6475 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6476 * CCCC (a1). Useful for integer division and modulus. 6477 * 6478 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6479 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6480 */ 6481 /* binop/lit16 vA, vB, #+CCCC */ 6482 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6483 ext a2, rINST, 8, 4 # a2 <- A 6484 ext a3, rINST, 12, 4 # a3 <- B 6485 GET_VREG a0, a3 # a0 <- vB 6486 .if 0 6487 beqz a1, common_errDivideByZero # is second operand zero? 6488 .endif 6489 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6490 # optional op 6491 xor a0, a0, a1 # a0 <- op, a0-a3 changed 6492 GET_INST_OPCODE v0 # extract opcode from rINST 6493 SET_VREG a0, a2 # vA <- a0 6494 GOTO_OPCODE v0 # jump to next instruction 6495 6496 6497 6498/* ------------------------------ */ 6499 .balign 128 6500.L_op_add_int_lit8: /* 0xd8 */ 6501/* File: mips64/op_add_int_lit8.S */ 6502/* File: mips64/binopLit8.S */ 6503 /* 6504 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6505 * that specifies an instruction that performs "result = a0 op a1". 6506 * This could be an MIPS instruction or a function call. (If the result 6507 * comes back in a register other than a0, you can override "result".) 6508 * 6509 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6510 * CC (a1). Useful for integer division and modulus. 6511 * 6512 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6513 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6514 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6515 */ 6516 /* binop/lit8 vAA, vBB, #+CC */ 6517 lbu a3, 2(rPC) # a3 <- BB 6518 lb a1, 3(rPC) # a1 <- sign-extended CC 6519 srl a2, rINST, 8 # a2 <- AA 6520 GET_VREG a0, a3 # a0 <- vBB 6521 .if 0 6522 beqz a1, common_errDivideByZero # is second operand zero? 6523 .endif 6524 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6525 # optional op 6526 addu a0, a0, a1 # a0 <- op, a0-a3 changed 6527 GET_INST_OPCODE v0 # extract opcode from rINST 6528 SET_VREG a0, a2 # vAA <- a0 6529 GOTO_OPCODE v0 # jump to next instruction 6530 6531 6532 6533/* ------------------------------ */ 6534 .balign 128 6535.L_op_rsub_int_lit8: /* 0xd9 */ 6536/* File: mips64/op_rsub_int_lit8.S */ 6537/* File: mips64/binopLit8.S */ 6538 /* 6539 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6540 * that specifies an instruction that performs "result = a0 op a1". 6541 * This could be an MIPS instruction or a function call. (If the result 6542 * comes back in a register other than a0, you can override "result".) 6543 * 6544 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6545 * CC (a1). Useful for integer division and modulus. 6546 * 6547 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6548 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6549 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6550 */ 6551 /* binop/lit8 vAA, vBB, #+CC */ 6552 lbu a3, 2(rPC) # a3 <- BB 6553 lb a1, 3(rPC) # a1 <- sign-extended CC 6554 srl a2, rINST, 8 # a2 <- AA 6555 GET_VREG a0, a3 # a0 <- vBB 6556 .if 0 6557 beqz a1, common_errDivideByZero # is second operand zero? 6558 .endif 6559 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6560 # optional op 6561 subu a0, a1, a0 # a0 <- op, a0-a3 changed 6562 GET_INST_OPCODE v0 # extract opcode from rINST 6563 SET_VREG a0, a2 # vAA <- a0 6564 GOTO_OPCODE v0 # jump to next instruction 6565 6566 6567 6568/* ------------------------------ */ 6569 .balign 128 6570.L_op_mul_int_lit8: /* 0xda */ 6571/* File: mips64/op_mul_int_lit8.S */ 6572/* File: mips64/binopLit8.S */ 6573 /* 6574 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6575 * that specifies an instruction that performs "result = a0 op a1". 6576 * This could be an MIPS instruction or a function call. (If the result 6577 * comes back in a register other than a0, you can override "result".) 6578 * 6579 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6580 * CC (a1). Useful for integer division and modulus. 6581 * 6582 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6583 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6584 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6585 */ 6586 /* binop/lit8 vAA, vBB, #+CC */ 6587 lbu a3, 2(rPC) # a3 <- BB 6588 lb a1, 3(rPC) # a1 <- sign-extended CC 6589 srl a2, rINST, 8 # a2 <- AA 6590 GET_VREG a0, a3 # a0 <- vBB 6591 .if 0 6592 beqz a1, common_errDivideByZero # is second operand zero? 6593 .endif 6594 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6595 # optional op 6596 mul a0, a0, a1 # a0 <- op, a0-a3 changed 6597 GET_INST_OPCODE v0 # extract opcode from rINST 6598 SET_VREG a0, a2 # vAA <- a0 6599 GOTO_OPCODE v0 # jump to next instruction 6600 6601 6602 6603/* ------------------------------ */ 6604 .balign 128 6605.L_op_div_int_lit8: /* 0xdb */ 6606/* File: mips64/op_div_int_lit8.S */ 6607/* File: mips64/binopLit8.S */ 6608 /* 6609 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6610 * that specifies an instruction that performs "result = a0 op a1". 6611 * This could be an MIPS instruction or a function call. (If the result 6612 * comes back in a register other than a0, you can override "result".) 6613 * 6614 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6615 * CC (a1). Useful for integer division and modulus. 6616 * 6617 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6618 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6619 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6620 */ 6621 /* binop/lit8 vAA, vBB, #+CC */ 6622 lbu a3, 2(rPC) # a3 <- BB 6623 lb a1, 3(rPC) # a1 <- sign-extended CC 6624 srl a2, rINST, 8 # a2 <- AA 6625 GET_VREG a0, a3 # a0 <- vBB 6626 .if 1 6627 beqz a1, common_errDivideByZero # is second operand zero? 6628 .endif 6629 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6630 # optional op 6631 div a0, a0, a1 # a0 <- op, a0-a3 changed 6632 GET_INST_OPCODE v0 # extract opcode from rINST 6633 SET_VREG a0, a2 # vAA <- a0 6634 GOTO_OPCODE v0 # jump to next instruction 6635 6636 6637 6638/* ------------------------------ */ 6639 .balign 128 6640.L_op_rem_int_lit8: /* 0xdc */ 6641/* File: mips64/op_rem_int_lit8.S */ 6642/* File: mips64/binopLit8.S */ 6643 /* 6644 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6645 * that specifies an instruction that performs "result = a0 op a1". 6646 * This could be an MIPS instruction or a function call. (If the result 6647 * comes back in a register other than a0, you can override "result".) 6648 * 6649 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6650 * CC (a1). Useful for integer division and modulus. 6651 * 6652 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6653 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6654 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6655 */ 6656 /* binop/lit8 vAA, vBB, #+CC */ 6657 lbu a3, 2(rPC) # a3 <- BB 6658 lb a1, 3(rPC) # a1 <- sign-extended CC 6659 srl a2, rINST, 8 # a2 <- AA 6660 GET_VREG a0, a3 # a0 <- vBB 6661 .if 1 6662 beqz a1, common_errDivideByZero # is second operand zero? 6663 .endif 6664 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6665 # optional op 6666 mod a0, a0, a1 # a0 <- op, a0-a3 changed 6667 GET_INST_OPCODE v0 # extract opcode from rINST 6668 SET_VREG a0, a2 # vAA <- a0 6669 GOTO_OPCODE v0 # jump to next instruction 6670 6671 6672 6673/* ------------------------------ */ 6674 .balign 128 6675.L_op_and_int_lit8: /* 0xdd */ 6676/* File: mips64/op_and_int_lit8.S */ 6677/* File: mips64/binopLit8.S */ 6678 /* 6679 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6680 * that specifies an instruction that performs "result = a0 op a1". 6681 * This could be an MIPS instruction or a function call. (If the result 6682 * comes back in a register other than a0, you can override "result".) 6683 * 6684 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6685 * CC (a1). Useful for integer division and modulus. 6686 * 6687 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6688 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6689 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6690 */ 6691 /* binop/lit8 vAA, vBB, #+CC */ 6692 lbu a3, 2(rPC) # a3 <- BB 6693 lb a1, 3(rPC) # a1 <- sign-extended CC 6694 srl a2, rINST, 8 # a2 <- AA 6695 GET_VREG a0, a3 # a0 <- vBB 6696 .if 0 6697 beqz a1, common_errDivideByZero # is second operand zero? 6698 .endif 6699 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6700 # optional op 6701 and a0, a0, a1 # a0 <- op, a0-a3 changed 6702 GET_INST_OPCODE v0 # extract opcode from rINST 6703 SET_VREG a0, a2 # vAA <- a0 6704 GOTO_OPCODE v0 # jump to next instruction 6705 6706 6707 6708/* ------------------------------ */ 6709 .balign 128 6710.L_op_or_int_lit8: /* 0xde */ 6711/* File: mips64/op_or_int_lit8.S */ 6712/* File: mips64/binopLit8.S */ 6713 /* 6714 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6715 * that specifies an instruction that performs "result = a0 op a1". 6716 * This could be an MIPS instruction or a function call. (If the result 6717 * comes back in a register other than a0, you can override "result".) 6718 * 6719 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6720 * CC (a1). Useful for integer division and modulus. 6721 * 6722 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6723 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6724 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6725 */ 6726 /* binop/lit8 vAA, vBB, #+CC */ 6727 lbu a3, 2(rPC) # a3 <- BB 6728 lb a1, 3(rPC) # a1 <- sign-extended CC 6729 srl a2, rINST, 8 # a2 <- AA 6730 GET_VREG a0, a3 # a0 <- vBB 6731 .if 0 6732 beqz a1, common_errDivideByZero # is second operand zero? 6733 .endif 6734 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6735 # optional op 6736 or a0, a0, a1 # a0 <- op, a0-a3 changed 6737 GET_INST_OPCODE v0 # extract opcode from rINST 6738 SET_VREG a0, a2 # vAA <- a0 6739 GOTO_OPCODE v0 # jump to next instruction 6740 6741 6742 6743/* ------------------------------ */ 6744 .balign 128 6745.L_op_xor_int_lit8: /* 0xdf */ 6746/* File: mips64/op_xor_int_lit8.S */ 6747/* File: mips64/binopLit8.S */ 6748 /* 6749 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6750 * that specifies an instruction that performs "result = a0 op a1". 6751 * This could be an MIPS instruction or a function call. (If the result 6752 * comes back in a register other than a0, you can override "result".) 6753 * 6754 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6755 * CC (a1). Useful for integer division and modulus. 6756 * 6757 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6758 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6759 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6760 */ 6761 /* binop/lit8 vAA, vBB, #+CC */ 6762 lbu a3, 2(rPC) # a3 <- BB 6763 lb a1, 3(rPC) # a1 <- sign-extended CC 6764 srl a2, rINST, 8 # a2 <- AA 6765 GET_VREG a0, a3 # a0 <- vBB 6766 .if 0 6767 beqz a1, common_errDivideByZero # is second operand zero? 6768 .endif 6769 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6770 # optional op 6771 xor a0, a0, a1 # a0 <- op, a0-a3 changed 6772 GET_INST_OPCODE v0 # extract opcode from rINST 6773 SET_VREG a0, a2 # vAA <- a0 6774 GOTO_OPCODE v0 # jump to next instruction 6775 6776 6777 6778/* ------------------------------ */ 6779 .balign 128 6780.L_op_shl_int_lit8: /* 0xe0 */ 6781/* File: mips64/op_shl_int_lit8.S */ 6782/* File: mips64/binopLit8.S */ 6783 /* 6784 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6785 * that specifies an instruction that performs "result = a0 op a1". 6786 * This could be an MIPS instruction or a function call. (If the result 6787 * comes back in a register other than a0, you can override "result".) 6788 * 6789 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6790 * CC (a1). Useful for integer division and modulus. 6791 * 6792 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6793 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6794 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6795 */ 6796 /* binop/lit8 vAA, vBB, #+CC */ 6797 lbu a3, 2(rPC) # a3 <- BB 6798 lb a1, 3(rPC) # a1 <- sign-extended CC 6799 srl a2, rINST, 8 # a2 <- AA 6800 GET_VREG a0, a3 # a0 <- vBB 6801 .if 0 6802 beqz a1, common_errDivideByZero # is second operand zero? 6803 .endif 6804 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6805 # optional op 6806 sll a0, a0, a1 # a0 <- op, a0-a3 changed 6807 GET_INST_OPCODE v0 # extract opcode from rINST 6808 SET_VREG a0, a2 # vAA <- a0 6809 GOTO_OPCODE v0 # jump to next instruction 6810 6811 6812 6813/* ------------------------------ */ 6814 .balign 128 6815.L_op_shr_int_lit8: /* 0xe1 */ 6816/* File: mips64/op_shr_int_lit8.S */ 6817/* File: mips64/binopLit8.S */ 6818 /* 6819 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6820 * that specifies an instruction that performs "result = a0 op a1". 6821 * This could be an MIPS instruction or a function call. (If the result 6822 * comes back in a register other than a0, you can override "result".) 6823 * 6824 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6825 * CC (a1). Useful for integer division and modulus. 6826 * 6827 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6828 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6829 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6830 */ 6831 /* binop/lit8 vAA, vBB, #+CC */ 6832 lbu a3, 2(rPC) # a3 <- BB 6833 lb a1, 3(rPC) # a1 <- sign-extended CC 6834 srl a2, rINST, 8 # a2 <- AA 6835 GET_VREG a0, a3 # a0 <- vBB 6836 .if 0 6837 beqz a1, common_errDivideByZero # is second operand zero? 6838 .endif 6839 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6840 # optional op 6841 sra a0, a0, a1 # a0 <- op, a0-a3 changed 6842 GET_INST_OPCODE v0 # extract opcode from rINST 6843 SET_VREG a0, a2 # vAA <- a0 6844 GOTO_OPCODE v0 # jump to next instruction 6845 6846 6847 6848/* ------------------------------ */ 6849 .balign 128 6850.L_op_ushr_int_lit8: /* 0xe2 */ 6851/* File: mips64/op_ushr_int_lit8.S */ 6852/* File: mips64/binopLit8.S */ 6853 /* 6854 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6855 * that specifies an instruction that performs "result = a0 op a1". 6856 * This could be an MIPS instruction or a function call. (If the result 6857 * comes back in a register other than a0, you can override "result".) 6858 * 6859 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6860 * CC (a1). Useful for integer division and modulus. 6861 * 6862 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6863 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6864 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6865 */ 6866 /* binop/lit8 vAA, vBB, #+CC */ 6867 lbu a3, 2(rPC) # a3 <- BB 6868 lb a1, 3(rPC) # a1 <- sign-extended CC 6869 srl a2, rINST, 8 # a2 <- AA 6870 GET_VREG a0, a3 # a0 <- vBB 6871 .if 0 6872 beqz a1, common_errDivideByZero # is second operand zero? 6873 .endif 6874 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6875 # optional op 6876 srl a0, a0, a1 # a0 <- op, a0-a3 changed 6877 GET_INST_OPCODE v0 # extract opcode from rINST 6878 SET_VREG a0, a2 # vAA <- a0 6879 GOTO_OPCODE v0 # jump to next instruction 6880 6881 6882 6883/* ------------------------------ */ 6884 .balign 128 6885.L_op_iget_quick: /* 0xe3 */ 6886/* File: mips64/op_iget_quick.S */ 6887 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6888 /* op vA, vB, offset//CCCC */ 6889 srl a2, rINST, 12 # a2 <- B 6890 lhu a1, 2(rPC) # a1 <- field byte offset 6891 GET_VREG_U a3, a2 # a3 <- object we're operating on 6892 ext a4, rINST, 8, 4 # a4 <- A 6893 daddu a1, a1, a3 6894 beqz a3, common_errNullObject # object was null 6895 lw a0, 0(a1) # a0 <- obj.field 6896 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6897 SET_VREG a0, a4 # fp[A] <- a0 6898 GET_INST_OPCODE v0 # extract opcode from rINST 6899 GOTO_OPCODE v0 # jump to next instruction 6900 6901/* ------------------------------ */ 6902 .balign 128 6903.L_op_iget_wide_quick: /* 0xe4 */ 6904/* File: mips64/op_iget_wide_quick.S */ 6905 /* iget-wide-quick vA, vB, offset//CCCC */ 6906 srl a2, rINST, 12 # a2 <- B 6907 lhu a4, 2(rPC) # a4 <- field byte offset 6908 GET_VREG_U a3, a2 # a3 <- object we're operating on 6909 ext a2, rINST, 8, 4 # a2 <- A 6910 beqz a3, common_errNullObject # object was null 6911 daddu a4, a3, a4 # create direct pointer 6912 lw a0, 0(a4) 6913 lw a1, 4(a4) 6914 dinsu a0, a1, 32, 32 6915 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6916 SET_VREG_WIDE a0, a2 6917 GET_INST_OPCODE v0 # extract opcode from rINST 6918 GOTO_OPCODE v0 # jump to next instruction 6919 6920/* ------------------------------ */ 6921 .balign 128 6922.L_op_iget_object_quick: /* 0xe5 */ 6923/* File: mips64/op_iget_object_quick.S */ 6924 /* For: iget-object-quick */ 6925 /* op vA, vB, offset//CCCC */ 6926 .extern artIGetObjectFromMterp 6927 srl a2, rINST, 12 # a2 <- B 6928 lhu a1, 2(rPC) # a1 <- field byte offset 6929 EXPORT_PC 6930 GET_VREG_U a0, a2 # a0 <- object we're operating on 6931 jal artIGetObjectFromMterp # (obj, offset) 6932 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 6933 ext a2, rINST, 8, 4 # a2 <- A 6934 PREFETCH_INST 2 6935 bnez a3, MterpPossibleException # bail out 6936 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 6937 ADVANCE 2 # advance rPC 6938 GET_INST_OPCODE v0 # extract opcode from rINST 6939 GOTO_OPCODE v0 # jump to next instruction 6940 6941/* ------------------------------ */ 6942 .balign 128 6943.L_op_iput_quick: /* 0xe6 */ 6944/* File: mips64/op_iput_quick.S */ 6945 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6946 /* op vA, vB, offset//CCCC */ 6947 srl a2, rINST, 12 # a2 <- B 6948 lhu a1, 2(rPC) # a1 <- field byte offset 6949 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6950 ext a2, rINST, 8, 4 # a2 <- A 6951 beqz a3, common_errNullObject # object was null 6952 GET_VREG a0, a2 # a0 <- fp[A] 6953 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6954 daddu a1, a1, a3 6955 sw a0, 0(a1) # obj.field <- a0 6956 GET_INST_OPCODE v0 # extract opcode from rINST 6957 GOTO_OPCODE v0 # jump to next instruction 6958 6959/* ------------------------------ */ 6960 .balign 128 6961.L_op_iput_wide_quick: /* 0xe7 */ 6962/* File: mips64/op_iput_wide_quick.S */ 6963 /* iput-wide-quick vA, vB, offset//CCCC */ 6964 srl a2, rINST, 12 # a2 <- B 6965 lhu a3, 2(rPC) # a3 <- field byte offset 6966 GET_VREG_U a2, a2 # a2 <- fp[B], the object pointer 6967 ext a0, rINST, 8, 4 # a0 <- A 6968 beqz a2, common_errNullObject # object was null 6969 GET_VREG_WIDE a0, a0 # a0 <- fp[A] 6970 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6971 daddu a1, a2, a3 # create a direct pointer 6972 sw a0, 0(a1) 6973 dsrl32 a0, a0, 0 6974 sw a0, 4(a1) 6975 GET_INST_OPCODE v0 # extract opcode from rINST 6976 GOTO_OPCODE v0 # jump to next instruction 6977 6978/* ------------------------------ */ 6979 .balign 128 6980.L_op_iput_object_quick: /* 0xe8 */ 6981/* File: mips64/op_iput_object_quick.S */ 6982 .extern MterpIputObjectQuick 6983 EXPORT_PC 6984 daddu a0, rFP, OFF_FP_SHADOWFRAME 6985 move a1, rPC 6986 move a2, rINST 6987 jal MterpIputObjectQuick 6988 beqzc v0, MterpException 6989 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6990 GET_INST_OPCODE v0 # extract opcode from rINST 6991 GOTO_OPCODE v0 # jump to next instruction 6992 6993/* ------------------------------ */ 6994 .balign 128 6995.L_op_invoke_virtual_quick: /* 0xe9 */ 6996/* File: mips64/op_invoke_virtual_quick.S */ 6997/* File: mips64/invoke.S */ 6998 /* 6999 * Generic invoke handler wrapper. 7000 */ 7001 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7002 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7003 .extern MterpInvokeVirtualQuick 7004 .extern MterpShouldSwitchInterpreters 7005 EXPORT_PC 7006 move a0, rSELF 7007 daddu a1, rFP, OFF_FP_SHADOWFRAME 7008 move a2, rPC 7009 move a3, rINST 7010 jal MterpInvokeVirtualQuick 7011 beqzc v0, MterpException 7012 FETCH_ADVANCE_INST 3 7013 jal MterpShouldSwitchInterpreters 7014 bnezc v0, MterpFallback 7015 GET_INST_OPCODE v0 7016 GOTO_OPCODE v0 7017 7018 7019/* ------------------------------ */ 7020 .balign 128 7021.L_op_invoke_virtual_range_quick: /* 0xea */ 7022/* File: mips64/op_invoke_virtual_range_quick.S */ 7023/* File: mips64/invoke.S */ 7024 /* 7025 * Generic invoke handler wrapper. 7026 */ 7027 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7028 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7029 .extern MterpInvokeVirtualQuickRange 7030 .extern MterpShouldSwitchInterpreters 7031 EXPORT_PC 7032 move a0, rSELF 7033 daddu a1, rFP, OFF_FP_SHADOWFRAME 7034 move a2, rPC 7035 move a3, rINST 7036 jal MterpInvokeVirtualQuickRange 7037 beqzc v0, MterpException 7038 FETCH_ADVANCE_INST 3 7039 jal MterpShouldSwitchInterpreters 7040 bnezc v0, MterpFallback 7041 GET_INST_OPCODE v0 7042 GOTO_OPCODE v0 7043 7044 7045/* ------------------------------ */ 7046 .balign 128 7047.L_op_iput_boolean_quick: /* 0xeb */ 7048/* File: mips64/op_iput_boolean_quick.S */ 7049/* File: mips64/op_iput_quick.S */ 7050 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 7051 /* op vA, vB, offset//CCCC */ 7052 srl a2, rINST, 12 # a2 <- B 7053 lhu a1, 2(rPC) # a1 <- field byte offset 7054 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 7055 ext a2, rINST, 8, 4 # a2 <- A 7056 beqz a3, common_errNullObject # object was null 7057 GET_VREG a0, a2 # a0 <- fp[A] 7058 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 7059 daddu a1, a1, a3 7060 sb a0, 0(a1) # obj.field <- a0 7061 GET_INST_OPCODE v0 # extract opcode from rINST 7062 GOTO_OPCODE v0 # jump to next instruction 7063 7064 7065/* ------------------------------ */ 7066 .balign 128 7067.L_op_iput_byte_quick: /* 0xec */ 7068/* File: mips64/op_iput_byte_quick.S */ 7069/* File: mips64/op_iput_quick.S */ 7070 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 7071 /* op vA, vB, offset//CCCC */ 7072 srl a2, rINST, 12 # a2 <- B 7073 lhu a1, 2(rPC) # a1 <- field byte offset 7074 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 7075 ext a2, rINST, 8, 4 # a2 <- A 7076 beqz a3, common_errNullObject # object was null 7077 GET_VREG a0, a2 # a0 <- fp[A] 7078 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 7079 daddu a1, a1, a3 7080 sb a0, 0(a1) # obj.field <- a0 7081 GET_INST_OPCODE v0 # extract opcode from rINST 7082 GOTO_OPCODE v0 # jump to next instruction 7083 7084 7085/* ------------------------------ */ 7086 .balign 128 7087.L_op_iput_char_quick: /* 0xed */ 7088/* File: mips64/op_iput_char_quick.S */ 7089/* File: mips64/op_iput_quick.S */ 7090 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 7091 /* op vA, vB, offset//CCCC */ 7092 srl a2, rINST, 12 # a2 <- B 7093 lhu a1, 2(rPC) # a1 <- field byte offset 7094 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 7095 ext a2, rINST, 8, 4 # a2 <- A 7096 beqz a3, common_errNullObject # object was null 7097 GET_VREG a0, a2 # a0 <- fp[A] 7098 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 7099 daddu a1, a1, a3 7100 sh a0, 0(a1) # obj.field <- a0 7101 GET_INST_OPCODE v0 # extract opcode from rINST 7102 GOTO_OPCODE v0 # jump to next instruction 7103 7104 7105/* ------------------------------ */ 7106 .balign 128 7107.L_op_iput_short_quick: /* 0xee */ 7108/* File: mips64/op_iput_short_quick.S */ 7109/* File: mips64/op_iput_quick.S */ 7110 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 7111 /* op vA, vB, offset//CCCC */ 7112 srl a2, rINST, 12 # a2 <- B 7113 lhu a1, 2(rPC) # a1 <- field byte offset 7114 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 7115 ext a2, rINST, 8, 4 # a2 <- A 7116 beqz a3, common_errNullObject # object was null 7117 GET_VREG a0, a2 # a0 <- fp[A] 7118 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 7119 daddu a1, a1, a3 7120 sh a0, 0(a1) # obj.field <- a0 7121 GET_INST_OPCODE v0 # extract opcode from rINST 7122 GOTO_OPCODE v0 # jump to next instruction 7123 7124 7125/* ------------------------------ */ 7126 .balign 128 7127.L_op_iget_boolean_quick: /* 0xef */ 7128/* File: mips64/op_iget_boolean_quick.S */ 7129/* File: mips64/op_iget_quick.S */ 7130 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7131 /* op vA, vB, offset//CCCC */ 7132 srl a2, rINST, 12 # a2 <- B 7133 lhu a1, 2(rPC) # a1 <- field byte offset 7134 GET_VREG_U a3, a2 # a3 <- object we're operating on 7135 ext a4, rINST, 8, 4 # a4 <- A 7136 daddu a1, a1, a3 7137 beqz a3, common_errNullObject # object was null 7138 lbu a0, 0(a1) # a0 <- obj.field 7139 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 7140 SET_VREG a0, a4 # fp[A] <- a0 7141 GET_INST_OPCODE v0 # extract opcode from rINST 7142 GOTO_OPCODE v0 # jump to next instruction 7143 7144 7145/* ------------------------------ */ 7146 .balign 128 7147.L_op_iget_byte_quick: /* 0xf0 */ 7148/* File: mips64/op_iget_byte_quick.S */ 7149/* File: mips64/op_iget_quick.S */ 7150 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7151 /* op vA, vB, offset//CCCC */ 7152 srl a2, rINST, 12 # a2 <- B 7153 lhu a1, 2(rPC) # a1 <- field byte offset 7154 GET_VREG_U a3, a2 # a3 <- object we're operating on 7155 ext a4, rINST, 8, 4 # a4 <- A 7156 daddu a1, a1, a3 7157 beqz a3, common_errNullObject # object was null 7158 lb a0, 0(a1) # a0 <- obj.field 7159 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 7160 SET_VREG a0, a4 # fp[A] <- a0 7161 GET_INST_OPCODE v0 # extract opcode from rINST 7162 GOTO_OPCODE v0 # jump to next instruction 7163 7164 7165/* ------------------------------ */ 7166 .balign 128 7167.L_op_iget_char_quick: /* 0xf1 */ 7168/* File: mips64/op_iget_char_quick.S */ 7169/* File: mips64/op_iget_quick.S */ 7170 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7171 /* op vA, vB, offset//CCCC */ 7172 srl a2, rINST, 12 # a2 <- B 7173 lhu a1, 2(rPC) # a1 <- field byte offset 7174 GET_VREG_U a3, a2 # a3 <- object we're operating on 7175 ext a4, rINST, 8, 4 # a4 <- A 7176 daddu a1, a1, a3 7177 beqz a3, common_errNullObject # object was null 7178 lhu a0, 0(a1) # a0 <- obj.field 7179 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 7180 SET_VREG a0, a4 # fp[A] <- a0 7181 GET_INST_OPCODE v0 # extract opcode from rINST 7182 GOTO_OPCODE v0 # jump to next instruction 7183 7184 7185/* ------------------------------ */ 7186 .balign 128 7187.L_op_iget_short_quick: /* 0xf2 */ 7188/* File: mips64/op_iget_short_quick.S */ 7189/* File: mips64/op_iget_quick.S */ 7190 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7191 /* op vA, vB, offset//CCCC */ 7192 srl a2, rINST, 12 # a2 <- B 7193 lhu a1, 2(rPC) # a1 <- field byte offset 7194 GET_VREG_U a3, a2 # a3 <- object we're operating on 7195 ext a4, rINST, 8, 4 # a4 <- A 7196 daddu a1, a1, a3 7197 beqz a3, common_errNullObject # object was null 7198 lh a0, 0(a1) # a0 <- obj.field 7199 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 7200 SET_VREG a0, a4 # fp[A] <- a0 7201 GET_INST_OPCODE v0 # extract opcode from rINST 7202 GOTO_OPCODE v0 # jump to next instruction 7203 7204 7205/* ------------------------------ */ 7206 .balign 128 7207.L_op_invoke_lambda: /* 0xf3 */ 7208/* Transfer stub to alternate interpreter */ 7209 b MterpFallback 7210 7211/* ------------------------------ */ 7212 .balign 128 7213.L_op_unused_f4: /* 0xf4 */ 7214/* File: mips64/op_unused_f4.S */ 7215/* File: mips64/unused.S */ 7216/* 7217 * Bail to reference interpreter to throw. 7218 */ 7219 b MterpFallback 7220 7221 7222/* ------------------------------ */ 7223 .balign 128 7224.L_op_capture_variable: /* 0xf5 */ 7225/* Transfer stub to alternate interpreter */ 7226 b MterpFallback 7227 7228/* ------------------------------ */ 7229 .balign 128 7230.L_op_create_lambda: /* 0xf6 */ 7231/* Transfer stub to alternate interpreter */ 7232 b MterpFallback 7233 7234/* ------------------------------ */ 7235 .balign 128 7236.L_op_liberate_variable: /* 0xf7 */ 7237/* Transfer stub to alternate interpreter */ 7238 b MterpFallback 7239 7240/* ------------------------------ */ 7241 .balign 128 7242.L_op_box_lambda: /* 0xf8 */ 7243/* Transfer stub to alternate interpreter */ 7244 b MterpFallback 7245 7246/* ------------------------------ */ 7247 .balign 128 7248.L_op_unbox_lambda: /* 0xf9 */ 7249/* Transfer stub to alternate interpreter */ 7250 b MterpFallback 7251 7252/* ------------------------------ */ 7253 .balign 128 7254.L_op_unused_fa: /* 0xfa */ 7255/* File: mips64/op_unused_fa.S */ 7256/* File: mips64/unused.S */ 7257/* 7258 * Bail to reference interpreter to throw. 7259 */ 7260 b MterpFallback 7261 7262 7263/* ------------------------------ */ 7264 .balign 128 7265.L_op_unused_fb: /* 0xfb */ 7266/* File: mips64/op_unused_fb.S */ 7267/* File: mips64/unused.S */ 7268/* 7269 * Bail to reference interpreter to throw. 7270 */ 7271 b MterpFallback 7272 7273 7274/* ------------------------------ */ 7275 .balign 128 7276.L_op_unused_fc: /* 0xfc */ 7277/* File: mips64/op_unused_fc.S */ 7278/* File: mips64/unused.S */ 7279/* 7280 * Bail to reference interpreter to throw. 7281 */ 7282 b MterpFallback 7283 7284 7285/* ------------------------------ */ 7286 .balign 128 7287.L_op_unused_fd: /* 0xfd */ 7288/* File: mips64/op_unused_fd.S */ 7289/* File: mips64/unused.S */ 7290/* 7291 * Bail to reference interpreter to throw. 7292 */ 7293 b MterpFallback 7294 7295 7296/* ------------------------------ */ 7297 .balign 128 7298.L_op_unused_fe: /* 0xfe */ 7299/* File: mips64/op_unused_fe.S */ 7300/* File: mips64/unused.S */ 7301/* 7302 * Bail to reference interpreter to throw. 7303 */ 7304 b MterpFallback 7305 7306 7307/* ------------------------------ */ 7308 .balign 128 7309.L_op_unused_ff: /* 0xff */ 7310/* File: mips64/op_unused_ff.S */ 7311/* File: mips64/unused.S */ 7312/* 7313 * Bail to reference interpreter to throw. 7314 */ 7315 b MterpFallback 7316 7317 7318 .balign 128 7319 .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart 7320 .global artMterpAsmInstructionEnd 7321artMterpAsmInstructionEnd: 7322 7323/* 7324 * =========================================================================== 7325 * Sister implementations 7326 * =========================================================================== 7327 */ 7328 .global artMterpAsmSisterStart 7329 .type artMterpAsmSisterStart, %function 7330 .text 7331 .balign 4 7332artMterpAsmSisterStart: 7333 7334/* continuation for op_float_to_int */ 7335.Lop_float_to_int_trunc: 7336 trunc.w.s f0, f0 7337 mfc1 t0, f0 7338.Lop_float_to_int_done: 7339 /* Can't include fcvtFooter.S after break */ 7340 GET_INST_OPCODE v0 # extract opcode from rINST 7341 SET_VREG t0, a1 7342 GOTO_OPCODE v0 # jump to next instruction 7343 7344/* continuation for op_float_to_long */ 7345.Lop_float_to_long_trunc: 7346 trunc.l.s f0, f0 7347 dmfc1 t0, f0 7348.Lop_float_to_long_done: 7349 /* Can't include fcvtFooter.S after break */ 7350 GET_INST_OPCODE v0 # extract opcode from rINST 7351 SET_VREG_WIDE t0, a1 7352 GOTO_OPCODE v0 # jump to next instruction 7353 7354/* continuation for op_double_to_int */ 7355.Lop_double_to_int_trunc: 7356 trunc.w.d f0, f0 7357 mfc1 t0, f0 7358.Lop_double_to_int_done: 7359 /* Can't include fcvtFooter.S after break */ 7360 GET_INST_OPCODE v0 # extract opcode from rINST 7361 SET_VREG t0, a1 7362 GOTO_OPCODE v0 # jump to next instruction 7363 7364/* continuation for op_double_to_long */ 7365.Lop_double_to_long_trunc: 7366 trunc.l.d f0, f0 7367 dmfc1 t0, f0 7368.Lop_double_to_long_done: 7369 /* Can't include fcvtFooter.S after break */ 7370 GET_INST_OPCODE v0 # extract opcode from rINST 7371 SET_VREG_WIDE t0, a1 7372 GOTO_OPCODE v0 # jump to next instruction 7373 7374 .size artMterpAsmSisterStart, .-artMterpAsmSisterStart 7375 .global artMterpAsmSisterEnd 7376artMterpAsmSisterEnd: 7377 7378 7379 .global artMterpAsmAltInstructionStart 7380 .type artMterpAsmAltInstructionStart, %function 7381 .text 7382 7383artMterpAsmAltInstructionStart = .L_ALT_op_nop 7384/* ------------------------------ */ 7385 .balign 128 7386.L_ALT_op_nop: /* 0x00 */ 7387/* File: mips64/alt_stub.S */ 7388/* 7389 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7390 * any interesting requests and then jump to the real instruction 7391 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7392 */ 7393 .extern MterpCheckBefore 7394 EXPORT_PC 7395 REFRESH_IBASE 7396 dla ra, artMterpAsmInstructionStart 7397 dla t9, MterpCheckBefore 7398 move a0, rSELF 7399 daddu a1, rFP, OFF_FP_SHADOWFRAME 7400 daddu ra, ra, (0 * 128) # Addr of primary handler. 7401 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7402 7403/* ------------------------------ */ 7404 .balign 128 7405.L_ALT_op_move: /* 0x01 */ 7406/* File: mips64/alt_stub.S */ 7407/* 7408 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7409 * any interesting requests and then jump to the real instruction 7410 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7411 */ 7412 .extern MterpCheckBefore 7413 EXPORT_PC 7414 REFRESH_IBASE 7415 dla ra, artMterpAsmInstructionStart 7416 dla t9, MterpCheckBefore 7417 move a0, rSELF 7418 daddu a1, rFP, OFF_FP_SHADOWFRAME 7419 daddu ra, ra, (1 * 128) # Addr of primary handler. 7420 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7421 7422/* ------------------------------ */ 7423 .balign 128 7424.L_ALT_op_move_from16: /* 0x02 */ 7425/* File: mips64/alt_stub.S */ 7426/* 7427 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7428 * any interesting requests and then jump to the real instruction 7429 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7430 */ 7431 .extern MterpCheckBefore 7432 EXPORT_PC 7433 REFRESH_IBASE 7434 dla ra, artMterpAsmInstructionStart 7435 dla t9, MterpCheckBefore 7436 move a0, rSELF 7437 daddu a1, rFP, OFF_FP_SHADOWFRAME 7438 daddu ra, ra, (2 * 128) # Addr of primary handler. 7439 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7440 7441/* ------------------------------ */ 7442 .balign 128 7443.L_ALT_op_move_16: /* 0x03 */ 7444/* File: mips64/alt_stub.S */ 7445/* 7446 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7447 * any interesting requests and then jump to the real instruction 7448 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7449 */ 7450 .extern MterpCheckBefore 7451 EXPORT_PC 7452 REFRESH_IBASE 7453 dla ra, artMterpAsmInstructionStart 7454 dla t9, MterpCheckBefore 7455 move a0, rSELF 7456 daddu a1, rFP, OFF_FP_SHADOWFRAME 7457 daddu ra, ra, (3 * 128) # Addr of primary handler. 7458 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7459 7460/* ------------------------------ */ 7461 .balign 128 7462.L_ALT_op_move_wide: /* 0x04 */ 7463/* File: mips64/alt_stub.S */ 7464/* 7465 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7466 * any interesting requests and then jump to the real instruction 7467 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7468 */ 7469 .extern MterpCheckBefore 7470 EXPORT_PC 7471 REFRESH_IBASE 7472 dla ra, artMterpAsmInstructionStart 7473 dla t9, MterpCheckBefore 7474 move a0, rSELF 7475 daddu a1, rFP, OFF_FP_SHADOWFRAME 7476 daddu ra, ra, (4 * 128) # Addr of primary handler. 7477 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7478 7479/* ------------------------------ */ 7480 .balign 128 7481.L_ALT_op_move_wide_from16: /* 0x05 */ 7482/* File: mips64/alt_stub.S */ 7483/* 7484 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7485 * any interesting requests and then jump to the real instruction 7486 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7487 */ 7488 .extern MterpCheckBefore 7489 EXPORT_PC 7490 REFRESH_IBASE 7491 dla ra, artMterpAsmInstructionStart 7492 dla t9, MterpCheckBefore 7493 move a0, rSELF 7494 daddu a1, rFP, OFF_FP_SHADOWFRAME 7495 daddu ra, ra, (5 * 128) # Addr of primary handler. 7496 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7497 7498/* ------------------------------ */ 7499 .balign 128 7500.L_ALT_op_move_wide_16: /* 0x06 */ 7501/* File: mips64/alt_stub.S */ 7502/* 7503 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7504 * any interesting requests and then jump to the real instruction 7505 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7506 */ 7507 .extern MterpCheckBefore 7508 EXPORT_PC 7509 REFRESH_IBASE 7510 dla ra, artMterpAsmInstructionStart 7511 dla t9, MterpCheckBefore 7512 move a0, rSELF 7513 daddu a1, rFP, OFF_FP_SHADOWFRAME 7514 daddu ra, ra, (6 * 128) # Addr of primary handler. 7515 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7516 7517/* ------------------------------ */ 7518 .balign 128 7519.L_ALT_op_move_object: /* 0x07 */ 7520/* File: mips64/alt_stub.S */ 7521/* 7522 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7523 * any interesting requests and then jump to the real instruction 7524 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7525 */ 7526 .extern MterpCheckBefore 7527 EXPORT_PC 7528 REFRESH_IBASE 7529 dla ra, artMterpAsmInstructionStart 7530 dla t9, MterpCheckBefore 7531 move a0, rSELF 7532 daddu a1, rFP, OFF_FP_SHADOWFRAME 7533 daddu ra, ra, (7 * 128) # Addr of primary handler. 7534 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7535 7536/* ------------------------------ */ 7537 .balign 128 7538.L_ALT_op_move_object_from16: /* 0x08 */ 7539/* File: mips64/alt_stub.S */ 7540/* 7541 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7542 * any interesting requests and then jump to the real instruction 7543 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7544 */ 7545 .extern MterpCheckBefore 7546 EXPORT_PC 7547 REFRESH_IBASE 7548 dla ra, artMterpAsmInstructionStart 7549 dla t9, MterpCheckBefore 7550 move a0, rSELF 7551 daddu a1, rFP, OFF_FP_SHADOWFRAME 7552 daddu ra, ra, (8 * 128) # Addr of primary handler. 7553 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7554 7555/* ------------------------------ */ 7556 .balign 128 7557.L_ALT_op_move_object_16: /* 0x09 */ 7558/* File: mips64/alt_stub.S */ 7559/* 7560 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7561 * any interesting requests and then jump to the real instruction 7562 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7563 */ 7564 .extern MterpCheckBefore 7565 EXPORT_PC 7566 REFRESH_IBASE 7567 dla ra, artMterpAsmInstructionStart 7568 dla t9, MterpCheckBefore 7569 move a0, rSELF 7570 daddu a1, rFP, OFF_FP_SHADOWFRAME 7571 daddu ra, ra, (9 * 128) # Addr of primary handler. 7572 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7573 7574/* ------------------------------ */ 7575 .balign 128 7576.L_ALT_op_move_result: /* 0x0a */ 7577/* File: mips64/alt_stub.S */ 7578/* 7579 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7580 * any interesting requests and then jump to the real instruction 7581 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7582 */ 7583 .extern MterpCheckBefore 7584 EXPORT_PC 7585 REFRESH_IBASE 7586 dla ra, artMterpAsmInstructionStart 7587 dla t9, MterpCheckBefore 7588 move a0, rSELF 7589 daddu a1, rFP, OFF_FP_SHADOWFRAME 7590 daddu ra, ra, (10 * 128) # Addr of primary handler. 7591 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7592 7593/* ------------------------------ */ 7594 .balign 128 7595.L_ALT_op_move_result_wide: /* 0x0b */ 7596/* File: mips64/alt_stub.S */ 7597/* 7598 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7599 * any interesting requests and then jump to the real instruction 7600 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7601 */ 7602 .extern MterpCheckBefore 7603 EXPORT_PC 7604 REFRESH_IBASE 7605 dla ra, artMterpAsmInstructionStart 7606 dla t9, MterpCheckBefore 7607 move a0, rSELF 7608 daddu a1, rFP, OFF_FP_SHADOWFRAME 7609 daddu ra, ra, (11 * 128) # Addr of primary handler. 7610 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7611 7612/* ------------------------------ */ 7613 .balign 128 7614.L_ALT_op_move_result_object: /* 0x0c */ 7615/* File: mips64/alt_stub.S */ 7616/* 7617 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7618 * any interesting requests and then jump to the real instruction 7619 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7620 */ 7621 .extern MterpCheckBefore 7622 EXPORT_PC 7623 REFRESH_IBASE 7624 dla ra, artMterpAsmInstructionStart 7625 dla t9, MterpCheckBefore 7626 move a0, rSELF 7627 daddu a1, rFP, OFF_FP_SHADOWFRAME 7628 daddu ra, ra, (12 * 128) # Addr of primary handler. 7629 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7630 7631/* ------------------------------ */ 7632 .balign 128 7633.L_ALT_op_move_exception: /* 0x0d */ 7634/* File: mips64/alt_stub.S */ 7635/* 7636 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7637 * any interesting requests and then jump to the real instruction 7638 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7639 */ 7640 .extern MterpCheckBefore 7641 EXPORT_PC 7642 REFRESH_IBASE 7643 dla ra, artMterpAsmInstructionStart 7644 dla t9, MterpCheckBefore 7645 move a0, rSELF 7646 daddu a1, rFP, OFF_FP_SHADOWFRAME 7647 daddu ra, ra, (13 * 128) # Addr of primary handler. 7648 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7649 7650/* ------------------------------ */ 7651 .balign 128 7652.L_ALT_op_return_void: /* 0x0e */ 7653/* File: mips64/alt_stub.S */ 7654/* 7655 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7656 * any interesting requests and then jump to the real instruction 7657 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7658 */ 7659 .extern MterpCheckBefore 7660 EXPORT_PC 7661 REFRESH_IBASE 7662 dla ra, artMterpAsmInstructionStart 7663 dla t9, MterpCheckBefore 7664 move a0, rSELF 7665 daddu a1, rFP, OFF_FP_SHADOWFRAME 7666 daddu ra, ra, (14 * 128) # Addr of primary handler. 7667 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7668 7669/* ------------------------------ */ 7670 .balign 128 7671.L_ALT_op_return: /* 0x0f */ 7672/* File: mips64/alt_stub.S */ 7673/* 7674 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7675 * any interesting requests and then jump to the real instruction 7676 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7677 */ 7678 .extern MterpCheckBefore 7679 EXPORT_PC 7680 REFRESH_IBASE 7681 dla ra, artMterpAsmInstructionStart 7682 dla t9, MterpCheckBefore 7683 move a0, rSELF 7684 daddu a1, rFP, OFF_FP_SHADOWFRAME 7685 daddu ra, ra, (15 * 128) # Addr of primary handler. 7686 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7687 7688/* ------------------------------ */ 7689 .balign 128 7690.L_ALT_op_return_wide: /* 0x10 */ 7691/* File: mips64/alt_stub.S */ 7692/* 7693 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7694 * any interesting requests and then jump to the real instruction 7695 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7696 */ 7697 .extern MterpCheckBefore 7698 EXPORT_PC 7699 REFRESH_IBASE 7700 dla ra, artMterpAsmInstructionStart 7701 dla t9, MterpCheckBefore 7702 move a0, rSELF 7703 daddu a1, rFP, OFF_FP_SHADOWFRAME 7704 daddu ra, ra, (16 * 128) # Addr of primary handler. 7705 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7706 7707/* ------------------------------ */ 7708 .balign 128 7709.L_ALT_op_return_object: /* 0x11 */ 7710/* File: mips64/alt_stub.S */ 7711/* 7712 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7713 * any interesting requests and then jump to the real instruction 7714 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7715 */ 7716 .extern MterpCheckBefore 7717 EXPORT_PC 7718 REFRESH_IBASE 7719 dla ra, artMterpAsmInstructionStart 7720 dla t9, MterpCheckBefore 7721 move a0, rSELF 7722 daddu a1, rFP, OFF_FP_SHADOWFRAME 7723 daddu ra, ra, (17 * 128) # Addr of primary handler. 7724 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7725 7726/* ------------------------------ */ 7727 .balign 128 7728.L_ALT_op_const_4: /* 0x12 */ 7729/* File: mips64/alt_stub.S */ 7730/* 7731 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7732 * any interesting requests and then jump to the real instruction 7733 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7734 */ 7735 .extern MterpCheckBefore 7736 EXPORT_PC 7737 REFRESH_IBASE 7738 dla ra, artMterpAsmInstructionStart 7739 dla t9, MterpCheckBefore 7740 move a0, rSELF 7741 daddu a1, rFP, OFF_FP_SHADOWFRAME 7742 daddu ra, ra, (18 * 128) # Addr of primary handler. 7743 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7744 7745/* ------------------------------ */ 7746 .balign 128 7747.L_ALT_op_const_16: /* 0x13 */ 7748/* File: mips64/alt_stub.S */ 7749/* 7750 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7751 * any interesting requests and then jump to the real instruction 7752 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7753 */ 7754 .extern MterpCheckBefore 7755 EXPORT_PC 7756 REFRESH_IBASE 7757 dla ra, artMterpAsmInstructionStart 7758 dla t9, MterpCheckBefore 7759 move a0, rSELF 7760 daddu a1, rFP, OFF_FP_SHADOWFRAME 7761 daddu ra, ra, (19 * 128) # Addr of primary handler. 7762 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7763 7764/* ------------------------------ */ 7765 .balign 128 7766.L_ALT_op_const: /* 0x14 */ 7767/* File: mips64/alt_stub.S */ 7768/* 7769 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7770 * any interesting requests and then jump to the real instruction 7771 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7772 */ 7773 .extern MterpCheckBefore 7774 EXPORT_PC 7775 REFRESH_IBASE 7776 dla ra, artMterpAsmInstructionStart 7777 dla t9, MterpCheckBefore 7778 move a0, rSELF 7779 daddu a1, rFP, OFF_FP_SHADOWFRAME 7780 daddu ra, ra, (20 * 128) # Addr of primary handler. 7781 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7782 7783/* ------------------------------ */ 7784 .balign 128 7785.L_ALT_op_const_high16: /* 0x15 */ 7786/* File: mips64/alt_stub.S */ 7787/* 7788 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7789 * any interesting requests and then jump to the real instruction 7790 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7791 */ 7792 .extern MterpCheckBefore 7793 EXPORT_PC 7794 REFRESH_IBASE 7795 dla ra, artMterpAsmInstructionStart 7796 dla t9, MterpCheckBefore 7797 move a0, rSELF 7798 daddu a1, rFP, OFF_FP_SHADOWFRAME 7799 daddu ra, ra, (21 * 128) # Addr of primary handler. 7800 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7801 7802/* ------------------------------ */ 7803 .balign 128 7804.L_ALT_op_const_wide_16: /* 0x16 */ 7805/* File: mips64/alt_stub.S */ 7806/* 7807 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7808 * any interesting requests and then jump to the real instruction 7809 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7810 */ 7811 .extern MterpCheckBefore 7812 EXPORT_PC 7813 REFRESH_IBASE 7814 dla ra, artMterpAsmInstructionStart 7815 dla t9, MterpCheckBefore 7816 move a0, rSELF 7817 daddu a1, rFP, OFF_FP_SHADOWFRAME 7818 daddu ra, ra, (22 * 128) # Addr of primary handler. 7819 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7820 7821/* ------------------------------ */ 7822 .balign 128 7823.L_ALT_op_const_wide_32: /* 0x17 */ 7824/* File: mips64/alt_stub.S */ 7825/* 7826 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7827 * any interesting requests and then jump to the real instruction 7828 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7829 */ 7830 .extern MterpCheckBefore 7831 EXPORT_PC 7832 REFRESH_IBASE 7833 dla ra, artMterpAsmInstructionStart 7834 dla t9, MterpCheckBefore 7835 move a0, rSELF 7836 daddu a1, rFP, OFF_FP_SHADOWFRAME 7837 daddu ra, ra, (23 * 128) # Addr of primary handler. 7838 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7839 7840/* ------------------------------ */ 7841 .balign 128 7842.L_ALT_op_const_wide: /* 0x18 */ 7843/* File: mips64/alt_stub.S */ 7844/* 7845 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7846 * any interesting requests and then jump to the real instruction 7847 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7848 */ 7849 .extern MterpCheckBefore 7850 EXPORT_PC 7851 REFRESH_IBASE 7852 dla ra, artMterpAsmInstructionStart 7853 dla t9, MterpCheckBefore 7854 move a0, rSELF 7855 daddu a1, rFP, OFF_FP_SHADOWFRAME 7856 daddu ra, ra, (24 * 128) # Addr of primary handler. 7857 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7858 7859/* ------------------------------ */ 7860 .balign 128 7861.L_ALT_op_const_wide_high16: /* 0x19 */ 7862/* File: mips64/alt_stub.S */ 7863/* 7864 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7865 * any interesting requests and then jump to the real instruction 7866 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7867 */ 7868 .extern MterpCheckBefore 7869 EXPORT_PC 7870 REFRESH_IBASE 7871 dla ra, artMterpAsmInstructionStart 7872 dla t9, MterpCheckBefore 7873 move a0, rSELF 7874 daddu a1, rFP, OFF_FP_SHADOWFRAME 7875 daddu ra, ra, (25 * 128) # Addr of primary handler. 7876 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7877 7878/* ------------------------------ */ 7879 .balign 128 7880.L_ALT_op_const_string: /* 0x1a */ 7881/* File: mips64/alt_stub.S */ 7882/* 7883 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7884 * any interesting requests and then jump to the real instruction 7885 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7886 */ 7887 .extern MterpCheckBefore 7888 EXPORT_PC 7889 REFRESH_IBASE 7890 dla ra, artMterpAsmInstructionStart 7891 dla t9, MterpCheckBefore 7892 move a0, rSELF 7893 daddu a1, rFP, OFF_FP_SHADOWFRAME 7894 daddu ra, ra, (26 * 128) # Addr of primary handler. 7895 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7896 7897/* ------------------------------ */ 7898 .balign 128 7899.L_ALT_op_const_string_jumbo: /* 0x1b */ 7900/* File: mips64/alt_stub.S */ 7901/* 7902 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7903 * any interesting requests and then jump to the real instruction 7904 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7905 */ 7906 .extern MterpCheckBefore 7907 EXPORT_PC 7908 REFRESH_IBASE 7909 dla ra, artMterpAsmInstructionStart 7910 dla t9, MterpCheckBefore 7911 move a0, rSELF 7912 daddu a1, rFP, OFF_FP_SHADOWFRAME 7913 daddu ra, ra, (27 * 128) # Addr of primary handler. 7914 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7915 7916/* ------------------------------ */ 7917 .balign 128 7918.L_ALT_op_const_class: /* 0x1c */ 7919/* File: mips64/alt_stub.S */ 7920/* 7921 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7922 * any interesting requests and then jump to the real instruction 7923 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7924 */ 7925 .extern MterpCheckBefore 7926 EXPORT_PC 7927 REFRESH_IBASE 7928 dla ra, artMterpAsmInstructionStart 7929 dla t9, MterpCheckBefore 7930 move a0, rSELF 7931 daddu a1, rFP, OFF_FP_SHADOWFRAME 7932 daddu ra, ra, (28 * 128) # Addr of primary handler. 7933 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7934 7935/* ------------------------------ */ 7936 .balign 128 7937.L_ALT_op_monitor_enter: /* 0x1d */ 7938/* File: mips64/alt_stub.S */ 7939/* 7940 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7941 * any interesting requests and then jump to the real instruction 7942 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7943 */ 7944 .extern MterpCheckBefore 7945 EXPORT_PC 7946 REFRESH_IBASE 7947 dla ra, artMterpAsmInstructionStart 7948 dla t9, MterpCheckBefore 7949 move a0, rSELF 7950 daddu a1, rFP, OFF_FP_SHADOWFRAME 7951 daddu ra, ra, (29 * 128) # Addr of primary handler. 7952 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7953 7954/* ------------------------------ */ 7955 .balign 128 7956.L_ALT_op_monitor_exit: /* 0x1e */ 7957/* File: mips64/alt_stub.S */ 7958/* 7959 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7960 * any interesting requests and then jump to the real instruction 7961 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7962 */ 7963 .extern MterpCheckBefore 7964 EXPORT_PC 7965 REFRESH_IBASE 7966 dla ra, artMterpAsmInstructionStart 7967 dla t9, MterpCheckBefore 7968 move a0, rSELF 7969 daddu a1, rFP, OFF_FP_SHADOWFRAME 7970 daddu ra, ra, (30 * 128) # Addr of primary handler. 7971 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7972 7973/* ------------------------------ */ 7974 .balign 128 7975.L_ALT_op_check_cast: /* 0x1f */ 7976/* File: mips64/alt_stub.S */ 7977/* 7978 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7979 * any interesting requests and then jump to the real instruction 7980 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7981 */ 7982 .extern MterpCheckBefore 7983 EXPORT_PC 7984 REFRESH_IBASE 7985 dla ra, artMterpAsmInstructionStart 7986 dla t9, MterpCheckBefore 7987 move a0, rSELF 7988 daddu a1, rFP, OFF_FP_SHADOWFRAME 7989 daddu ra, ra, (31 * 128) # Addr of primary handler. 7990 jalr zero, t9 # (self, shadow_frame) Note: tail call. 7991 7992/* ------------------------------ */ 7993 .balign 128 7994.L_ALT_op_instance_of: /* 0x20 */ 7995/* File: mips64/alt_stub.S */ 7996/* 7997 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7998 * any interesting requests and then jump to the real instruction 7999 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8000 */ 8001 .extern MterpCheckBefore 8002 EXPORT_PC 8003 REFRESH_IBASE 8004 dla ra, artMterpAsmInstructionStart 8005 dla t9, MterpCheckBefore 8006 move a0, rSELF 8007 daddu a1, rFP, OFF_FP_SHADOWFRAME 8008 daddu ra, ra, (32 * 128) # Addr of primary handler. 8009 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8010 8011/* ------------------------------ */ 8012 .balign 128 8013.L_ALT_op_array_length: /* 0x21 */ 8014/* File: mips64/alt_stub.S */ 8015/* 8016 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8017 * any interesting requests and then jump to the real instruction 8018 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8019 */ 8020 .extern MterpCheckBefore 8021 EXPORT_PC 8022 REFRESH_IBASE 8023 dla ra, artMterpAsmInstructionStart 8024 dla t9, MterpCheckBefore 8025 move a0, rSELF 8026 daddu a1, rFP, OFF_FP_SHADOWFRAME 8027 daddu ra, ra, (33 * 128) # Addr of primary handler. 8028 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8029 8030/* ------------------------------ */ 8031 .balign 128 8032.L_ALT_op_new_instance: /* 0x22 */ 8033/* File: mips64/alt_stub.S */ 8034/* 8035 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8036 * any interesting requests and then jump to the real instruction 8037 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8038 */ 8039 .extern MterpCheckBefore 8040 EXPORT_PC 8041 REFRESH_IBASE 8042 dla ra, artMterpAsmInstructionStart 8043 dla t9, MterpCheckBefore 8044 move a0, rSELF 8045 daddu a1, rFP, OFF_FP_SHADOWFRAME 8046 daddu ra, ra, (34 * 128) # Addr of primary handler. 8047 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8048 8049/* ------------------------------ */ 8050 .balign 128 8051.L_ALT_op_new_array: /* 0x23 */ 8052/* File: mips64/alt_stub.S */ 8053/* 8054 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8055 * any interesting requests and then jump to the real instruction 8056 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8057 */ 8058 .extern MterpCheckBefore 8059 EXPORT_PC 8060 REFRESH_IBASE 8061 dla ra, artMterpAsmInstructionStart 8062 dla t9, MterpCheckBefore 8063 move a0, rSELF 8064 daddu a1, rFP, OFF_FP_SHADOWFRAME 8065 daddu ra, ra, (35 * 128) # Addr of primary handler. 8066 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8067 8068/* ------------------------------ */ 8069 .balign 128 8070.L_ALT_op_filled_new_array: /* 0x24 */ 8071/* File: mips64/alt_stub.S */ 8072/* 8073 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8074 * any interesting requests and then jump to the real instruction 8075 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8076 */ 8077 .extern MterpCheckBefore 8078 EXPORT_PC 8079 REFRESH_IBASE 8080 dla ra, artMterpAsmInstructionStart 8081 dla t9, MterpCheckBefore 8082 move a0, rSELF 8083 daddu a1, rFP, OFF_FP_SHADOWFRAME 8084 daddu ra, ra, (36 * 128) # Addr of primary handler. 8085 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8086 8087/* ------------------------------ */ 8088 .balign 128 8089.L_ALT_op_filled_new_array_range: /* 0x25 */ 8090/* File: mips64/alt_stub.S */ 8091/* 8092 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8093 * any interesting requests and then jump to the real instruction 8094 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8095 */ 8096 .extern MterpCheckBefore 8097 EXPORT_PC 8098 REFRESH_IBASE 8099 dla ra, artMterpAsmInstructionStart 8100 dla t9, MterpCheckBefore 8101 move a0, rSELF 8102 daddu a1, rFP, OFF_FP_SHADOWFRAME 8103 daddu ra, ra, (37 * 128) # Addr of primary handler. 8104 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8105 8106/* ------------------------------ */ 8107 .balign 128 8108.L_ALT_op_fill_array_data: /* 0x26 */ 8109/* File: mips64/alt_stub.S */ 8110/* 8111 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8112 * any interesting requests and then jump to the real instruction 8113 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8114 */ 8115 .extern MterpCheckBefore 8116 EXPORT_PC 8117 REFRESH_IBASE 8118 dla ra, artMterpAsmInstructionStart 8119 dla t9, MterpCheckBefore 8120 move a0, rSELF 8121 daddu a1, rFP, OFF_FP_SHADOWFRAME 8122 daddu ra, ra, (38 * 128) # Addr of primary handler. 8123 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8124 8125/* ------------------------------ */ 8126 .balign 128 8127.L_ALT_op_throw: /* 0x27 */ 8128/* File: mips64/alt_stub.S */ 8129/* 8130 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8131 * any interesting requests and then jump to the real instruction 8132 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8133 */ 8134 .extern MterpCheckBefore 8135 EXPORT_PC 8136 REFRESH_IBASE 8137 dla ra, artMterpAsmInstructionStart 8138 dla t9, MterpCheckBefore 8139 move a0, rSELF 8140 daddu a1, rFP, OFF_FP_SHADOWFRAME 8141 daddu ra, ra, (39 * 128) # Addr of primary handler. 8142 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8143 8144/* ------------------------------ */ 8145 .balign 128 8146.L_ALT_op_goto: /* 0x28 */ 8147/* File: mips64/alt_stub.S */ 8148/* 8149 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8150 * any interesting requests and then jump to the real instruction 8151 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8152 */ 8153 .extern MterpCheckBefore 8154 EXPORT_PC 8155 REFRESH_IBASE 8156 dla ra, artMterpAsmInstructionStart 8157 dla t9, MterpCheckBefore 8158 move a0, rSELF 8159 daddu a1, rFP, OFF_FP_SHADOWFRAME 8160 daddu ra, ra, (40 * 128) # Addr of primary handler. 8161 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8162 8163/* ------------------------------ */ 8164 .balign 128 8165.L_ALT_op_goto_16: /* 0x29 */ 8166/* File: mips64/alt_stub.S */ 8167/* 8168 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8169 * any interesting requests and then jump to the real instruction 8170 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8171 */ 8172 .extern MterpCheckBefore 8173 EXPORT_PC 8174 REFRESH_IBASE 8175 dla ra, artMterpAsmInstructionStart 8176 dla t9, MterpCheckBefore 8177 move a0, rSELF 8178 daddu a1, rFP, OFF_FP_SHADOWFRAME 8179 daddu ra, ra, (41 * 128) # Addr of primary handler. 8180 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8181 8182/* ------------------------------ */ 8183 .balign 128 8184.L_ALT_op_goto_32: /* 0x2a */ 8185/* File: mips64/alt_stub.S */ 8186/* 8187 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8188 * any interesting requests and then jump to the real instruction 8189 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8190 */ 8191 .extern MterpCheckBefore 8192 EXPORT_PC 8193 REFRESH_IBASE 8194 dla ra, artMterpAsmInstructionStart 8195 dla t9, MterpCheckBefore 8196 move a0, rSELF 8197 daddu a1, rFP, OFF_FP_SHADOWFRAME 8198 daddu ra, ra, (42 * 128) # Addr of primary handler. 8199 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8200 8201/* ------------------------------ */ 8202 .balign 128 8203.L_ALT_op_packed_switch: /* 0x2b */ 8204/* File: mips64/alt_stub.S */ 8205/* 8206 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8207 * any interesting requests and then jump to the real instruction 8208 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8209 */ 8210 .extern MterpCheckBefore 8211 EXPORT_PC 8212 REFRESH_IBASE 8213 dla ra, artMterpAsmInstructionStart 8214 dla t9, MterpCheckBefore 8215 move a0, rSELF 8216 daddu a1, rFP, OFF_FP_SHADOWFRAME 8217 daddu ra, ra, (43 * 128) # Addr of primary handler. 8218 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8219 8220/* ------------------------------ */ 8221 .balign 128 8222.L_ALT_op_sparse_switch: /* 0x2c */ 8223/* File: mips64/alt_stub.S */ 8224/* 8225 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8226 * any interesting requests and then jump to the real instruction 8227 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8228 */ 8229 .extern MterpCheckBefore 8230 EXPORT_PC 8231 REFRESH_IBASE 8232 dla ra, artMterpAsmInstructionStart 8233 dla t9, MterpCheckBefore 8234 move a0, rSELF 8235 daddu a1, rFP, OFF_FP_SHADOWFRAME 8236 daddu ra, ra, (44 * 128) # Addr of primary handler. 8237 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8238 8239/* ------------------------------ */ 8240 .balign 128 8241.L_ALT_op_cmpl_float: /* 0x2d */ 8242/* File: mips64/alt_stub.S */ 8243/* 8244 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8245 * any interesting requests and then jump to the real instruction 8246 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8247 */ 8248 .extern MterpCheckBefore 8249 EXPORT_PC 8250 REFRESH_IBASE 8251 dla ra, artMterpAsmInstructionStart 8252 dla t9, MterpCheckBefore 8253 move a0, rSELF 8254 daddu a1, rFP, OFF_FP_SHADOWFRAME 8255 daddu ra, ra, (45 * 128) # Addr of primary handler. 8256 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8257 8258/* ------------------------------ */ 8259 .balign 128 8260.L_ALT_op_cmpg_float: /* 0x2e */ 8261/* File: mips64/alt_stub.S */ 8262/* 8263 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8264 * any interesting requests and then jump to the real instruction 8265 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8266 */ 8267 .extern MterpCheckBefore 8268 EXPORT_PC 8269 REFRESH_IBASE 8270 dla ra, artMterpAsmInstructionStart 8271 dla t9, MterpCheckBefore 8272 move a0, rSELF 8273 daddu a1, rFP, OFF_FP_SHADOWFRAME 8274 daddu ra, ra, (46 * 128) # Addr of primary handler. 8275 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8276 8277/* ------------------------------ */ 8278 .balign 128 8279.L_ALT_op_cmpl_double: /* 0x2f */ 8280/* File: mips64/alt_stub.S */ 8281/* 8282 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8283 * any interesting requests and then jump to the real instruction 8284 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8285 */ 8286 .extern MterpCheckBefore 8287 EXPORT_PC 8288 REFRESH_IBASE 8289 dla ra, artMterpAsmInstructionStart 8290 dla t9, MterpCheckBefore 8291 move a0, rSELF 8292 daddu a1, rFP, OFF_FP_SHADOWFRAME 8293 daddu ra, ra, (47 * 128) # Addr of primary handler. 8294 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8295 8296/* ------------------------------ */ 8297 .balign 128 8298.L_ALT_op_cmpg_double: /* 0x30 */ 8299/* File: mips64/alt_stub.S */ 8300/* 8301 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8302 * any interesting requests and then jump to the real instruction 8303 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8304 */ 8305 .extern MterpCheckBefore 8306 EXPORT_PC 8307 REFRESH_IBASE 8308 dla ra, artMterpAsmInstructionStart 8309 dla t9, MterpCheckBefore 8310 move a0, rSELF 8311 daddu a1, rFP, OFF_FP_SHADOWFRAME 8312 daddu ra, ra, (48 * 128) # Addr of primary handler. 8313 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8314 8315/* ------------------------------ */ 8316 .balign 128 8317.L_ALT_op_cmp_long: /* 0x31 */ 8318/* File: mips64/alt_stub.S */ 8319/* 8320 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8321 * any interesting requests and then jump to the real instruction 8322 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8323 */ 8324 .extern MterpCheckBefore 8325 EXPORT_PC 8326 REFRESH_IBASE 8327 dla ra, artMterpAsmInstructionStart 8328 dla t9, MterpCheckBefore 8329 move a0, rSELF 8330 daddu a1, rFP, OFF_FP_SHADOWFRAME 8331 daddu ra, ra, (49 * 128) # Addr of primary handler. 8332 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8333 8334/* ------------------------------ */ 8335 .balign 128 8336.L_ALT_op_if_eq: /* 0x32 */ 8337/* File: mips64/alt_stub.S */ 8338/* 8339 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8340 * any interesting requests and then jump to the real instruction 8341 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8342 */ 8343 .extern MterpCheckBefore 8344 EXPORT_PC 8345 REFRESH_IBASE 8346 dla ra, artMterpAsmInstructionStart 8347 dla t9, MterpCheckBefore 8348 move a0, rSELF 8349 daddu a1, rFP, OFF_FP_SHADOWFRAME 8350 daddu ra, ra, (50 * 128) # Addr of primary handler. 8351 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8352 8353/* ------------------------------ */ 8354 .balign 128 8355.L_ALT_op_if_ne: /* 0x33 */ 8356/* File: mips64/alt_stub.S */ 8357/* 8358 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8359 * any interesting requests and then jump to the real instruction 8360 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8361 */ 8362 .extern MterpCheckBefore 8363 EXPORT_PC 8364 REFRESH_IBASE 8365 dla ra, artMterpAsmInstructionStart 8366 dla t9, MterpCheckBefore 8367 move a0, rSELF 8368 daddu a1, rFP, OFF_FP_SHADOWFRAME 8369 daddu ra, ra, (51 * 128) # Addr of primary handler. 8370 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8371 8372/* ------------------------------ */ 8373 .balign 128 8374.L_ALT_op_if_lt: /* 0x34 */ 8375/* File: mips64/alt_stub.S */ 8376/* 8377 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8378 * any interesting requests and then jump to the real instruction 8379 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8380 */ 8381 .extern MterpCheckBefore 8382 EXPORT_PC 8383 REFRESH_IBASE 8384 dla ra, artMterpAsmInstructionStart 8385 dla t9, MterpCheckBefore 8386 move a0, rSELF 8387 daddu a1, rFP, OFF_FP_SHADOWFRAME 8388 daddu ra, ra, (52 * 128) # Addr of primary handler. 8389 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8390 8391/* ------------------------------ */ 8392 .balign 128 8393.L_ALT_op_if_ge: /* 0x35 */ 8394/* File: mips64/alt_stub.S */ 8395/* 8396 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8397 * any interesting requests and then jump to the real instruction 8398 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8399 */ 8400 .extern MterpCheckBefore 8401 EXPORT_PC 8402 REFRESH_IBASE 8403 dla ra, artMterpAsmInstructionStart 8404 dla t9, MterpCheckBefore 8405 move a0, rSELF 8406 daddu a1, rFP, OFF_FP_SHADOWFRAME 8407 daddu ra, ra, (53 * 128) # Addr of primary handler. 8408 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8409 8410/* ------------------------------ */ 8411 .balign 128 8412.L_ALT_op_if_gt: /* 0x36 */ 8413/* File: mips64/alt_stub.S */ 8414/* 8415 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8416 * any interesting requests and then jump to the real instruction 8417 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8418 */ 8419 .extern MterpCheckBefore 8420 EXPORT_PC 8421 REFRESH_IBASE 8422 dla ra, artMterpAsmInstructionStart 8423 dla t9, MterpCheckBefore 8424 move a0, rSELF 8425 daddu a1, rFP, OFF_FP_SHADOWFRAME 8426 daddu ra, ra, (54 * 128) # Addr of primary handler. 8427 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8428 8429/* ------------------------------ */ 8430 .balign 128 8431.L_ALT_op_if_le: /* 0x37 */ 8432/* File: mips64/alt_stub.S */ 8433/* 8434 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8435 * any interesting requests and then jump to the real instruction 8436 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8437 */ 8438 .extern MterpCheckBefore 8439 EXPORT_PC 8440 REFRESH_IBASE 8441 dla ra, artMterpAsmInstructionStart 8442 dla t9, MterpCheckBefore 8443 move a0, rSELF 8444 daddu a1, rFP, OFF_FP_SHADOWFRAME 8445 daddu ra, ra, (55 * 128) # Addr of primary handler. 8446 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8447 8448/* ------------------------------ */ 8449 .balign 128 8450.L_ALT_op_if_eqz: /* 0x38 */ 8451/* File: mips64/alt_stub.S */ 8452/* 8453 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8454 * any interesting requests and then jump to the real instruction 8455 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8456 */ 8457 .extern MterpCheckBefore 8458 EXPORT_PC 8459 REFRESH_IBASE 8460 dla ra, artMterpAsmInstructionStart 8461 dla t9, MterpCheckBefore 8462 move a0, rSELF 8463 daddu a1, rFP, OFF_FP_SHADOWFRAME 8464 daddu ra, ra, (56 * 128) # Addr of primary handler. 8465 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8466 8467/* ------------------------------ */ 8468 .balign 128 8469.L_ALT_op_if_nez: /* 0x39 */ 8470/* File: mips64/alt_stub.S */ 8471/* 8472 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8473 * any interesting requests and then jump to the real instruction 8474 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8475 */ 8476 .extern MterpCheckBefore 8477 EXPORT_PC 8478 REFRESH_IBASE 8479 dla ra, artMterpAsmInstructionStart 8480 dla t9, MterpCheckBefore 8481 move a0, rSELF 8482 daddu a1, rFP, OFF_FP_SHADOWFRAME 8483 daddu ra, ra, (57 * 128) # Addr of primary handler. 8484 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8485 8486/* ------------------------------ */ 8487 .balign 128 8488.L_ALT_op_if_ltz: /* 0x3a */ 8489/* File: mips64/alt_stub.S */ 8490/* 8491 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8492 * any interesting requests and then jump to the real instruction 8493 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8494 */ 8495 .extern MterpCheckBefore 8496 EXPORT_PC 8497 REFRESH_IBASE 8498 dla ra, artMterpAsmInstructionStart 8499 dla t9, MterpCheckBefore 8500 move a0, rSELF 8501 daddu a1, rFP, OFF_FP_SHADOWFRAME 8502 daddu ra, ra, (58 * 128) # Addr of primary handler. 8503 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8504 8505/* ------------------------------ */ 8506 .balign 128 8507.L_ALT_op_if_gez: /* 0x3b */ 8508/* File: mips64/alt_stub.S */ 8509/* 8510 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8511 * any interesting requests and then jump to the real instruction 8512 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8513 */ 8514 .extern MterpCheckBefore 8515 EXPORT_PC 8516 REFRESH_IBASE 8517 dla ra, artMterpAsmInstructionStart 8518 dla t9, MterpCheckBefore 8519 move a0, rSELF 8520 daddu a1, rFP, OFF_FP_SHADOWFRAME 8521 daddu ra, ra, (59 * 128) # Addr of primary handler. 8522 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8523 8524/* ------------------------------ */ 8525 .balign 128 8526.L_ALT_op_if_gtz: /* 0x3c */ 8527/* File: mips64/alt_stub.S */ 8528/* 8529 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8530 * any interesting requests and then jump to the real instruction 8531 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8532 */ 8533 .extern MterpCheckBefore 8534 EXPORT_PC 8535 REFRESH_IBASE 8536 dla ra, artMterpAsmInstructionStart 8537 dla t9, MterpCheckBefore 8538 move a0, rSELF 8539 daddu a1, rFP, OFF_FP_SHADOWFRAME 8540 daddu ra, ra, (60 * 128) # Addr of primary handler. 8541 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8542 8543/* ------------------------------ */ 8544 .balign 128 8545.L_ALT_op_if_lez: /* 0x3d */ 8546/* File: mips64/alt_stub.S */ 8547/* 8548 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8549 * any interesting requests and then jump to the real instruction 8550 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8551 */ 8552 .extern MterpCheckBefore 8553 EXPORT_PC 8554 REFRESH_IBASE 8555 dla ra, artMterpAsmInstructionStart 8556 dla t9, MterpCheckBefore 8557 move a0, rSELF 8558 daddu a1, rFP, OFF_FP_SHADOWFRAME 8559 daddu ra, ra, (61 * 128) # Addr of primary handler. 8560 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8561 8562/* ------------------------------ */ 8563 .balign 128 8564.L_ALT_op_unused_3e: /* 0x3e */ 8565/* File: mips64/alt_stub.S */ 8566/* 8567 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8568 * any interesting requests and then jump to the real instruction 8569 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8570 */ 8571 .extern MterpCheckBefore 8572 EXPORT_PC 8573 REFRESH_IBASE 8574 dla ra, artMterpAsmInstructionStart 8575 dla t9, MterpCheckBefore 8576 move a0, rSELF 8577 daddu a1, rFP, OFF_FP_SHADOWFRAME 8578 daddu ra, ra, (62 * 128) # Addr of primary handler. 8579 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8580 8581/* ------------------------------ */ 8582 .balign 128 8583.L_ALT_op_unused_3f: /* 0x3f */ 8584/* File: mips64/alt_stub.S */ 8585/* 8586 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8587 * any interesting requests and then jump to the real instruction 8588 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8589 */ 8590 .extern MterpCheckBefore 8591 EXPORT_PC 8592 REFRESH_IBASE 8593 dla ra, artMterpAsmInstructionStart 8594 dla t9, MterpCheckBefore 8595 move a0, rSELF 8596 daddu a1, rFP, OFF_FP_SHADOWFRAME 8597 daddu ra, ra, (63 * 128) # Addr of primary handler. 8598 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8599 8600/* ------------------------------ */ 8601 .balign 128 8602.L_ALT_op_unused_40: /* 0x40 */ 8603/* File: mips64/alt_stub.S */ 8604/* 8605 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8606 * any interesting requests and then jump to the real instruction 8607 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8608 */ 8609 .extern MterpCheckBefore 8610 EXPORT_PC 8611 REFRESH_IBASE 8612 dla ra, artMterpAsmInstructionStart 8613 dla t9, MterpCheckBefore 8614 move a0, rSELF 8615 daddu a1, rFP, OFF_FP_SHADOWFRAME 8616 daddu ra, ra, (64 * 128) # Addr of primary handler. 8617 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8618 8619/* ------------------------------ */ 8620 .balign 128 8621.L_ALT_op_unused_41: /* 0x41 */ 8622/* File: mips64/alt_stub.S */ 8623/* 8624 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8625 * any interesting requests and then jump to the real instruction 8626 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8627 */ 8628 .extern MterpCheckBefore 8629 EXPORT_PC 8630 REFRESH_IBASE 8631 dla ra, artMterpAsmInstructionStart 8632 dla t9, MterpCheckBefore 8633 move a0, rSELF 8634 daddu a1, rFP, OFF_FP_SHADOWFRAME 8635 daddu ra, ra, (65 * 128) # Addr of primary handler. 8636 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8637 8638/* ------------------------------ */ 8639 .balign 128 8640.L_ALT_op_unused_42: /* 0x42 */ 8641/* File: mips64/alt_stub.S */ 8642/* 8643 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8644 * any interesting requests and then jump to the real instruction 8645 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8646 */ 8647 .extern MterpCheckBefore 8648 EXPORT_PC 8649 REFRESH_IBASE 8650 dla ra, artMterpAsmInstructionStart 8651 dla t9, MterpCheckBefore 8652 move a0, rSELF 8653 daddu a1, rFP, OFF_FP_SHADOWFRAME 8654 daddu ra, ra, (66 * 128) # Addr of primary handler. 8655 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8656 8657/* ------------------------------ */ 8658 .balign 128 8659.L_ALT_op_unused_43: /* 0x43 */ 8660/* File: mips64/alt_stub.S */ 8661/* 8662 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8663 * any interesting requests and then jump to the real instruction 8664 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8665 */ 8666 .extern MterpCheckBefore 8667 EXPORT_PC 8668 REFRESH_IBASE 8669 dla ra, artMterpAsmInstructionStart 8670 dla t9, MterpCheckBefore 8671 move a0, rSELF 8672 daddu a1, rFP, OFF_FP_SHADOWFRAME 8673 daddu ra, ra, (67 * 128) # Addr of primary handler. 8674 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8675 8676/* ------------------------------ */ 8677 .balign 128 8678.L_ALT_op_aget: /* 0x44 */ 8679/* File: mips64/alt_stub.S */ 8680/* 8681 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8682 * any interesting requests and then jump to the real instruction 8683 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8684 */ 8685 .extern MterpCheckBefore 8686 EXPORT_PC 8687 REFRESH_IBASE 8688 dla ra, artMterpAsmInstructionStart 8689 dla t9, MterpCheckBefore 8690 move a0, rSELF 8691 daddu a1, rFP, OFF_FP_SHADOWFRAME 8692 daddu ra, ra, (68 * 128) # Addr of primary handler. 8693 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8694 8695/* ------------------------------ */ 8696 .balign 128 8697.L_ALT_op_aget_wide: /* 0x45 */ 8698/* File: mips64/alt_stub.S */ 8699/* 8700 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8701 * any interesting requests and then jump to the real instruction 8702 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8703 */ 8704 .extern MterpCheckBefore 8705 EXPORT_PC 8706 REFRESH_IBASE 8707 dla ra, artMterpAsmInstructionStart 8708 dla t9, MterpCheckBefore 8709 move a0, rSELF 8710 daddu a1, rFP, OFF_FP_SHADOWFRAME 8711 daddu ra, ra, (69 * 128) # Addr of primary handler. 8712 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8713 8714/* ------------------------------ */ 8715 .balign 128 8716.L_ALT_op_aget_object: /* 0x46 */ 8717/* File: mips64/alt_stub.S */ 8718/* 8719 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8720 * any interesting requests and then jump to the real instruction 8721 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8722 */ 8723 .extern MterpCheckBefore 8724 EXPORT_PC 8725 REFRESH_IBASE 8726 dla ra, artMterpAsmInstructionStart 8727 dla t9, MterpCheckBefore 8728 move a0, rSELF 8729 daddu a1, rFP, OFF_FP_SHADOWFRAME 8730 daddu ra, ra, (70 * 128) # Addr of primary handler. 8731 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8732 8733/* ------------------------------ */ 8734 .balign 128 8735.L_ALT_op_aget_boolean: /* 0x47 */ 8736/* File: mips64/alt_stub.S */ 8737/* 8738 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8739 * any interesting requests and then jump to the real instruction 8740 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8741 */ 8742 .extern MterpCheckBefore 8743 EXPORT_PC 8744 REFRESH_IBASE 8745 dla ra, artMterpAsmInstructionStart 8746 dla t9, MterpCheckBefore 8747 move a0, rSELF 8748 daddu a1, rFP, OFF_FP_SHADOWFRAME 8749 daddu ra, ra, (71 * 128) # Addr of primary handler. 8750 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8751 8752/* ------------------------------ */ 8753 .balign 128 8754.L_ALT_op_aget_byte: /* 0x48 */ 8755/* File: mips64/alt_stub.S */ 8756/* 8757 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8758 * any interesting requests and then jump to the real instruction 8759 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8760 */ 8761 .extern MterpCheckBefore 8762 EXPORT_PC 8763 REFRESH_IBASE 8764 dla ra, artMterpAsmInstructionStart 8765 dla t9, MterpCheckBefore 8766 move a0, rSELF 8767 daddu a1, rFP, OFF_FP_SHADOWFRAME 8768 daddu ra, ra, (72 * 128) # Addr of primary handler. 8769 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8770 8771/* ------------------------------ */ 8772 .balign 128 8773.L_ALT_op_aget_char: /* 0x49 */ 8774/* File: mips64/alt_stub.S */ 8775/* 8776 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8777 * any interesting requests and then jump to the real instruction 8778 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8779 */ 8780 .extern MterpCheckBefore 8781 EXPORT_PC 8782 REFRESH_IBASE 8783 dla ra, artMterpAsmInstructionStart 8784 dla t9, MterpCheckBefore 8785 move a0, rSELF 8786 daddu a1, rFP, OFF_FP_SHADOWFRAME 8787 daddu ra, ra, (73 * 128) # Addr of primary handler. 8788 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8789 8790/* ------------------------------ */ 8791 .balign 128 8792.L_ALT_op_aget_short: /* 0x4a */ 8793/* File: mips64/alt_stub.S */ 8794/* 8795 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8796 * any interesting requests and then jump to the real instruction 8797 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8798 */ 8799 .extern MterpCheckBefore 8800 EXPORT_PC 8801 REFRESH_IBASE 8802 dla ra, artMterpAsmInstructionStart 8803 dla t9, MterpCheckBefore 8804 move a0, rSELF 8805 daddu a1, rFP, OFF_FP_SHADOWFRAME 8806 daddu ra, ra, (74 * 128) # Addr of primary handler. 8807 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8808 8809/* ------------------------------ */ 8810 .balign 128 8811.L_ALT_op_aput: /* 0x4b */ 8812/* File: mips64/alt_stub.S */ 8813/* 8814 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8815 * any interesting requests and then jump to the real instruction 8816 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8817 */ 8818 .extern MterpCheckBefore 8819 EXPORT_PC 8820 REFRESH_IBASE 8821 dla ra, artMterpAsmInstructionStart 8822 dla t9, MterpCheckBefore 8823 move a0, rSELF 8824 daddu a1, rFP, OFF_FP_SHADOWFRAME 8825 daddu ra, ra, (75 * 128) # Addr of primary handler. 8826 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8827 8828/* ------------------------------ */ 8829 .balign 128 8830.L_ALT_op_aput_wide: /* 0x4c */ 8831/* File: mips64/alt_stub.S */ 8832/* 8833 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8834 * any interesting requests and then jump to the real instruction 8835 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8836 */ 8837 .extern MterpCheckBefore 8838 EXPORT_PC 8839 REFRESH_IBASE 8840 dla ra, artMterpAsmInstructionStart 8841 dla t9, MterpCheckBefore 8842 move a0, rSELF 8843 daddu a1, rFP, OFF_FP_SHADOWFRAME 8844 daddu ra, ra, (76 * 128) # Addr of primary handler. 8845 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8846 8847/* ------------------------------ */ 8848 .balign 128 8849.L_ALT_op_aput_object: /* 0x4d */ 8850/* File: mips64/alt_stub.S */ 8851/* 8852 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8853 * any interesting requests and then jump to the real instruction 8854 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8855 */ 8856 .extern MterpCheckBefore 8857 EXPORT_PC 8858 REFRESH_IBASE 8859 dla ra, artMterpAsmInstructionStart 8860 dla t9, MterpCheckBefore 8861 move a0, rSELF 8862 daddu a1, rFP, OFF_FP_SHADOWFRAME 8863 daddu ra, ra, (77 * 128) # Addr of primary handler. 8864 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8865 8866/* ------------------------------ */ 8867 .balign 128 8868.L_ALT_op_aput_boolean: /* 0x4e */ 8869/* File: mips64/alt_stub.S */ 8870/* 8871 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8872 * any interesting requests and then jump to the real instruction 8873 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8874 */ 8875 .extern MterpCheckBefore 8876 EXPORT_PC 8877 REFRESH_IBASE 8878 dla ra, artMterpAsmInstructionStart 8879 dla t9, MterpCheckBefore 8880 move a0, rSELF 8881 daddu a1, rFP, OFF_FP_SHADOWFRAME 8882 daddu ra, ra, (78 * 128) # Addr of primary handler. 8883 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8884 8885/* ------------------------------ */ 8886 .balign 128 8887.L_ALT_op_aput_byte: /* 0x4f */ 8888/* File: mips64/alt_stub.S */ 8889/* 8890 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8891 * any interesting requests and then jump to the real instruction 8892 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8893 */ 8894 .extern MterpCheckBefore 8895 EXPORT_PC 8896 REFRESH_IBASE 8897 dla ra, artMterpAsmInstructionStart 8898 dla t9, MterpCheckBefore 8899 move a0, rSELF 8900 daddu a1, rFP, OFF_FP_SHADOWFRAME 8901 daddu ra, ra, (79 * 128) # Addr of primary handler. 8902 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8903 8904/* ------------------------------ */ 8905 .balign 128 8906.L_ALT_op_aput_char: /* 0x50 */ 8907/* File: mips64/alt_stub.S */ 8908/* 8909 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8910 * any interesting requests and then jump to the real instruction 8911 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8912 */ 8913 .extern MterpCheckBefore 8914 EXPORT_PC 8915 REFRESH_IBASE 8916 dla ra, artMterpAsmInstructionStart 8917 dla t9, MterpCheckBefore 8918 move a0, rSELF 8919 daddu a1, rFP, OFF_FP_SHADOWFRAME 8920 daddu ra, ra, (80 * 128) # Addr of primary handler. 8921 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8922 8923/* ------------------------------ */ 8924 .balign 128 8925.L_ALT_op_aput_short: /* 0x51 */ 8926/* File: mips64/alt_stub.S */ 8927/* 8928 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8929 * any interesting requests and then jump to the real instruction 8930 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8931 */ 8932 .extern MterpCheckBefore 8933 EXPORT_PC 8934 REFRESH_IBASE 8935 dla ra, artMterpAsmInstructionStart 8936 dla t9, MterpCheckBefore 8937 move a0, rSELF 8938 daddu a1, rFP, OFF_FP_SHADOWFRAME 8939 daddu ra, ra, (81 * 128) # Addr of primary handler. 8940 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8941 8942/* ------------------------------ */ 8943 .balign 128 8944.L_ALT_op_iget: /* 0x52 */ 8945/* File: mips64/alt_stub.S */ 8946/* 8947 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8948 * any interesting requests and then jump to the real instruction 8949 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8950 */ 8951 .extern MterpCheckBefore 8952 EXPORT_PC 8953 REFRESH_IBASE 8954 dla ra, artMterpAsmInstructionStart 8955 dla t9, MterpCheckBefore 8956 move a0, rSELF 8957 daddu a1, rFP, OFF_FP_SHADOWFRAME 8958 daddu ra, ra, (82 * 128) # Addr of primary handler. 8959 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8960 8961/* ------------------------------ */ 8962 .balign 128 8963.L_ALT_op_iget_wide: /* 0x53 */ 8964/* File: mips64/alt_stub.S */ 8965/* 8966 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8967 * any interesting requests and then jump to the real instruction 8968 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8969 */ 8970 .extern MterpCheckBefore 8971 EXPORT_PC 8972 REFRESH_IBASE 8973 dla ra, artMterpAsmInstructionStart 8974 dla t9, MterpCheckBefore 8975 move a0, rSELF 8976 daddu a1, rFP, OFF_FP_SHADOWFRAME 8977 daddu ra, ra, (83 * 128) # Addr of primary handler. 8978 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8979 8980/* ------------------------------ */ 8981 .balign 128 8982.L_ALT_op_iget_object: /* 0x54 */ 8983/* File: mips64/alt_stub.S */ 8984/* 8985 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8986 * any interesting requests and then jump to the real instruction 8987 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8988 */ 8989 .extern MterpCheckBefore 8990 EXPORT_PC 8991 REFRESH_IBASE 8992 dla ra, artMterpAsmInstructionStart 8993 dla t9, MterpCheckBefore 8994 move a0, rSELF 8995 daddu a1, rFP, OFF_FP_SHADOWFRAME 8996 daddu ra, ra, (84 * 128) # Addr of primary handler. 8997 jalr zero, t9 # (self, shadow_frame) Note: tail call. 8998 8999/* ------------------------------ */ 9000 .balign 128 9001.L_ALT_op_iget_boolean: /* 0x55 */ 9002/* File: mips64/alt_stub.S */ 9003/* 9004 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9005 * any interesting requests and then jump to the real instruction 9006 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9007 */ 9008 .extern MterpCheckBefore 9009 EXPORT_PC 9010 REFRESH_IBASE 9011 dla ra, artMterpAsmInstructionStart 9012 dla t9, MterpCheckBefore 9013 move a0, rSELF 9014 daddu a1, rFP, OFF_FP_SHADOWFRAME 9015 daddu ra, ra, (85 * 128) # Addr of primary handler. 9016 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9017 9018/* ------------------------------ */ 9019 .balign 128 9020.L_ALT_op_iget_byte: /* 0x56 */ 9021/* File: mips64/alt_stub.S */ 9022/* 9023 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9024 * any interesting requests and then jump to the real instruction 9025 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9026 */ 9027 .extern MterpCheckBefore 9028 EXPORT_PC 9029 REFRESH_IBASE 9030 dla ra, artMterpAsmInstructionStart 9031 dla t9, MterpCheckBefore 9032 move a0, rSELF 9033 daddu a1, rFP, OFF_FP_SHADOWFRAME 9034 daddu ra, ra, (86 * 128) # Addr of primary handler. 9035 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9036 9037/* ------------------------------ */ 9038 .balign 128 9039.L_ALT_op_iget_char: /* 0x57 */ 9040/* File: mips64/alt_stub.S */ 9041/* 9042 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9043 * any interesting requests and then jump to the real instruction 9044 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9045 */ 9046 .extern MterpCheckBefore 9047 EXPORT_PC 9048 REFRESH_IBASE 9049 dla ra, artMterpAsmInstructionStart 9050 dla t9, MterpCheckBefore 9051 move a0, rSELF 9052 daddu a1, rFP, OFF_FP_SHADOWFRAME 9053 daddu ra, ra, (87 * 128) # Addr of primary handler. 9054 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9055 9056/* ------------------------------ */ 9057 .balign 128 9058.L_ALT_op_iget_short: /* 0x58 */ 9059/* File: mips64/alt_stub.S */ 9060/* 9061 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9062 * any interesting requests and then jump to the real instruction 9063 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9064 */ 9065 .extern MterpCheckBefore 9066 EXPORT_PC 9067 REFRESH_IBASE 9068 dla ra, artMterpAsmInstructionStart 9069 dla t9, MterpCheckBefore 9070 move a0, rSELF 9071 daddu a1, rFP, OFF_FP_SHADOWFRAME 9072 daddu ra, ra, (88 * 128) # Addr of primary handler. 9073 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9074 9075/* ------------------------------ */ 9076 .balign 128 9077.L_ALT_op_iput: /* 0x59 */ 9078/* File: mips64/alt_stub.S */ 9079/* 9080 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9081 * any interesting requests and then jump to the real instruction 9082 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9083 */ 9084 .extern MterpCheckBefore 9085 EXPORT_PC 9086 REFRESH_IBASE 9087 dla ra, artMterpAsmInstructionStart 9088 dla t9, MterpCheckBefore 9089 move a0, rSELF 9090 daddu a1, rFP, OFF_FP_SHADOWFRAME 9091 daddu ra, ra, (89 * 128) # Addr of primary handler. 9092 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9093 9094/* ------------------------------ */ 9095 .balign 128 9096.L_ALT_op_iput_wide: /* 0x5a */ 9097/* File: mips64/alt_stub.S */ 9098/* 9099 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9100 * any interesting requests and then jump to the real instruction 9101 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9102 */ 9103 .extern MterpCheckBefore 9104 EXPORT_PC 9105 REFRESH_IBASE 9106 dla ra, artMterpAsmInstructionStart 9107 dla t9, MterpCheckBefore 9108 move a0, rSELF 9109 daddu a1, rFP, OFF_FP_SHADOWFRAME 9110 daddu ra, ra, (90 * 128) # Addr of primary handler. 9111 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9112 9113/* ------------------------------ */ 9114 .balign 128 9115.L_ALT_op_iput_object: /* 0x5b */ 9116/* File: mips64/alt_stub.S */ 9117/* 9118 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9119 * any interesting requests and then jump to the real instruction 9120 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9121 */ 9122 .extern MterpCheckBefore 9123 EXPORT_PC 9124 REFRESH_IBASE 9125 dla ra, artMterpAsmInstructionStart 9126 dla t9, MterpCheckBefore 9127 move a0, rSELF 9128 daddu a1, rFP, OFF_FP_SHADOWFRAME 9129 daddu ra, ra, (91 * 128) # Addr of primary handler. 9130 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9131 9132/* ------------------------------ */ 9133 .balign 128 9134.L_ALT_op_iput_boolean: /* 0x5c */ 9135/* File: mips64/alt_stub.S */ 9136/* 9137 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9138 * any interesting requests and then jump to the real instruction 9139 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9140 */ 9141 .extern MterpCheckBefore 9142 EXPORT_PC 9143 REFRESH_IBASE 9144 dla ra, artMterpAsmInstructionStart 9145 dla t9, MterpCheckBefore 9146 move a0, rSELF 9147 daddu a1, rFP, OFF_FP_SHADOWFRAME 9148 daddu ra, ra, (92 * 128) # Addr of primary handler. 9149 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9150 9151/* ------------------------------ */ 9152 .balign 128 9153.L_ALT_op_iput_byte: /* 0x5d */ 9154/* File: mips64/alt_stub.S */ 9155/* 9156 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9157 * any interesting requests and then jump to the real instruction 9158 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9159 */ 9160 .extern MterpCheckBefore 9161 EXPORT_PC 9162 REFRESH_IBASE 9163 dla ra, artMterpAsmInstructionStart 9164 dla t9, MterpCheckBefore 9165 move a0, rSELF 9166 daddu a1, rFP, OFF_FP_SHADOWFRAME 9167 daddu ra, ra, (93 * 128) # Addr of primary handler. 9168 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9169 9170/* ------------------------------ */ 9171 .balign 128 9172.L_ALT_op_iput_char: /* 0x5e */ 9173/* File: mips64/alt_stub.S */ 9174/* 9175 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9176 * any interesting requests and then jump to the real instruction 9177 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9178 */ 9179 .extern MterpCheckBefore 9180 EXPORT_PC 9181 REFRESH_IBASE 9182 dla ra, artMterpAsmInstructionStart 9183 dla t9, MterpCheckBefore 9184 move a0, rSELF 9185 daddu a1, rFP, OFF_FP_SHADOWFRAME 9186 daddu ra, ra, (94 * 128) # Addr of primary handler. 9187 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9188 9189/* ------------------------------ */ 9190 .balign 128 9191.L_ALT_op_iput_short: /* 0x5f */ 9192/* File: mips64/alt_stub.S */ 9193/* 9194 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9195 * any interesting requests and then jump to the real instruction 9196 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9197 */ 9198 .extern MterpCheckBefore 9199 EXPORT_PC 9200 REFRESH_IBASE 9201 dla ra, artMterpAsmInstructionStart 9202 dla t9, MterpCheckBefore 9203 move a0, rSELF 9204 daddu a1, rFP, OFF_FP_SHADOWFRAME 9205 daddu ra, ra, (95 * 128) # Addr of primary handler. 9206 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9207 9208/* ------------------------------ */ 9209 .balign 128 9210.L_ALT_op_sget: /* 0x60 */ 9211/* File: mips64/alt_stub.S */ 9212/* 9213 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9214 * any interesting requests and then jump to the real instruction 9215 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9216 */ 9217 .extern MterpCheckBefore 9218 EXPORT_PC 9219 REFRESH_IBASE 9220 dla ra, artMterpAsmInstructionStart 9221 dla t9, MterpCheckBefore 9222 move a0, rSELF 9223 daddu a1, rFP, OFF_FP_SHADOWFRAME 9224 daddu ra, ra, (96 * 128) # Addr of primary handler. 9225 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9226 9227/* ------------------------------ */ 9228 .balign 128 9229.L_ALT_op_sget_wide: /* 0x61 */ 9230/* File: mips64/alt_stub.S */ 9231/* 9232 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9233 * any interesting requests and then jump to the real instruction 9234 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9235 */ 9236 .extern MterpCheckBefore 9237 EXPORT_PC 9238 REFRESH_IBASE 9239 dla ra, artMterpAsmInstructionStart 9240 dla t9, MterpCheckBefore 9241 move a0, rSELF 9242 daddu a1, rFP, OFF_FP_SHADOWFRAME 9243 daddu ra, ra, (97 * 128) # Addr of primary handler. 9244 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9245 9246/* ------------------------------ */ 9247 .balign 128 9248.L_ALT_op_sget_object: /* 0x62 */ 9249/* File: mips64/alt_stub.S */ 9250/* 9251 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9252 * any interesting requests and then jump to the real instruction 9253 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9254 */ 9255 .extern MterpCheckBefore 9256 EXPORT_PC 9257 REFRESH_IBASE 9258 dla ra, artMterpAsmInstructionStart 9259 dla t9, MterpCheckBefore 9260 move a0, rSELF 9261 daddu a1, rFP, OFF_FP_SHADOWFRAME 9262 daddu ra, ra, (98 * 128) # Addr of primary handler. 9263 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9264 9265/* ------------------------------ */ 9266 .balign 128 9267.L_ALT_op_sget_boolean: /* 0x63 */ 9268/* File: mips64/alt_stub.S */ 9269/* 9270 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9271 * any interesting requests and then jump to the real instruction 9272 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9273 */ 9274 .extern MterpCheckBefore 9275 EXPORT_PC 9276 REFRESH_IBASE 9277 dla ra, artMterpAsmInstructionStart 9278 dla t9, MterpCheckBefore 9279 move a0, rSELF 9280 daddu a1, rFP, OFF_FP_SHADOWFRAME 9281 daddu ra, ra, (99 * 128) # Addr of primary handler. 9282 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9283 9284/* ------------------------------ */ 9285 .balign 128 9286.L_ALT_op_sget_byte: /* 0x64 */ 9287/* File: mips64/alt_stub.S */ 9288/* 9289 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9290 * any interesting requests and then jump to the real instruction 9291 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9292 */ 9293 .extern MterpCheckBefore 9294 EXPORT_PC 9295 REFRESH_IBASE 9296 dla ra, artMterpAsmInstructionStart 9297 dla t9, MterpCheckBefore 9298 move a0, rSELF 9299 daddu a1, rFP, OFF_FP_SHADOWFRAME 9300 daddu ra, ra, (100 * 128) # Addr of primary handler. 9301 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9302 9303/* ------------------------------ */ 9304 .balign 128 9305.L_ALT_op_sget_char: /* 0x65 */ 9306/* File: mips64/alt_stub.S */ 9307/* 9308 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9309 * any interesting requests and then jump to the real instruction 9310 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9311 */ 9312 .extern MterpCheckBefore 9313 EXPORT_PC 9314 REFRESH_IBASE 9315 dla ra, artMterpAsmInstructionStart 9316 dla t9, MterpCheckBefore 9317 move a0, rSELF 9318 daddu a1, rFP, OFF_FP_SHADOWFRAME 9319 daddu ra, ra, (101 * 128) # Addr of primary handler. 9320 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9321 9322/* ------------------------------ */ 9323 .balign 128 9324.L_ALT_op_sget_short: /* 0x66 */ 9325/* File: mips64/alt_stub.S */ 9326/* 9327 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9328 * any interesting requests and then jump to the real instruction 9329 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9330 */ 9331 .extern MterpCheckBefore 9332 EXPORT_PC 9333 REFRESH_IBASE 9334 dla ra, artMterpAsmInstructionStart 9335 dla t9, MterpCheckBefore 9336 move a0, rSELF 9337 daddu a1, rFP, OFF_FP_SHADOWFRAME 9338 daddu ra, ra, (102 * 128) # Addr of primary handler. 9339 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9340 9341/* ------------------------------ */ 9342 .balign 128 9343.L_ALT_op_sput: /* 0x67 */ 9344/* File: mips64/alt_stub.S */ 9345/* 9346 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9347 * any interesting requests and then jump to the real instruction 9348 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9349 */ 9350 .extern MterpCheckBefore 9351 EXPORT_PC 9352 REFRESH_IBASE 9353 dla ra, artMterpAsmInstructionStart 9354 dla t9, MterpCheckBefore 9355 move a0, rSELF 9356 daddu a1, rFP, OFF_FP_SHADOWFRAME 9357 daddu ra, ra, (103 * 128) # Addr of primary handler. 9358 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9359 9360/* ------------------------------ */ 9361 .balign 128 9362.L_ALT_op_sput_wide: /* 0x68 */ 9363/* File: mips64/alt_stub.S */ 9364/* 9365 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9366 * any interesting requests and then jump to the real instruction 9367 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9368 */ 9369 .extern MterpCheckBefore 9370 EXPORT_PC 9371 REFRESH_IBASE 9372 dla ra, artMterpAsmInstructionStart 9373 dla t9, MterpCheckBefore 9374 move a0, rSELF 9375 daddu a1, rFP, OFF_FP_SHADOWFRAME 9376 daddu ra, ra, (104 * 128) # Addr of primary handler. 9377 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9378 9379/* ------------------------------ */ 9380 .balign 128 9381.L_ALT_op_sput_object: /* 0x69 */ 9382/* File: mips64/alt_stub.S */ 9383/* 9384 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9385 * any interesting requests and then jump to the real instruction 9386 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9387 */ 9388 .extern MterpCheckBefore 9389 EXPORT_PC 9390 REFRESH_IBASE 9391 dla ra, artMterpAsmInstructionStart 9392 dla t9, MterpCheckBefore 9393 move a0, rSELF 9394 daddu a1, rFP, OFF_FP_SHADOWFRAME 9395 daddu ra, ra, (105 * 128) # Addr of primary handler. 9396 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9397 9398/* ------------------------------ */ 9399 .balign 128 9400.L_ALT_op_sput_boolean: /* 0x6a */ 9401/* File: mips64/alt_stub.S */ 9402/* 9403 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9404 * any interesting requests and then jump to the real instruction 9405 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9406 */ 9407 .extern MterpCheckBefore 9408 EXPORT_PC 9409 REFRESH_IBASE 9410 dla ra, artMterpAsmInstructionStart 9411 dla t9, MterpCheckBefore 9412 move a0, rSELF 9413 daddu a1, rFP, OFF_FP_SHADOWFRAME 9414 daddu ra, ra, (106 * 128) # Addr of primary handler. 9415 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9416 9417/* ------------------------------ */ 9418 .balign 128 9419.L_ALT_op_sput_byte: /* 0x6b */ 9420/* File: mips64/alt_stub.S */ 9421/* 9422 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9423 * any interesting requests and then jump to the real instruction 9424 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9425 */ 9426 .extern MterpCheckBefore 9427 EXPORT_PC 9428 REFRESH_IBASE 9429 dla ra, artMterpAsmInstructionStart 9430 dla t9, MterpCheckBefore 9431 move a0, rSELF 9432 daddu a1, rFP, OFF_FP_SHADOWFRAME 9433 daddu ra, ra, (107 * 128) # Addr of primary handler. 9434 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9435 9436/* ------------------------------ */ 9437 .balign 128 9438.L_ALT_op_sput_char: /* 0x6c */ 9439/* File: mips64/alt_stub.S */ 9440/* 9441 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9442 * any interesting requests and then jump to the real instruction 9443 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9444 */ 9445 .extern MterpCheckBefore 9446 EXPORT_PC 9447 REFRESH_IBASE 9448 dla ra, artMterpAsmInstructionStart 9449 dla t9, MterpCheckBefore 9450 move a0, rSELF 9451 daddu a1, rFP, OFF_FP_SHADOWFRAME 9452 daddu ra, ra, (108 * 128) # Addr of primary handler. 9453 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9454 9455/* ------------------------------ */ 9456 .balign 128 9457.L_ALT_op_sput_short: /* 0x6d */ 9458/* File: mips64/alt_stub.S */ 9459/* 9460 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9461 * any interesting requests and then jump to the real instruction 9462 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9463 */ 9464 .extern MterpCheckBefore 9465 EXPORT_PC 9466 REFRESH_IBASE 9467 dla ra, artMterpAsmInstructionStart 9468 dla t9, MterpCheckBefore 9469 move a0, rSELF 9470 daddu a1, rFP, OFF_FP_SHADOWFRAME 9471 daddu ra, ra, (109 * 128) # Addr of primary handler. 9472 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9473 9474/* ------------------------------ */ 9475 .balign 128 9476.L_ALT_op_invoke_virtual: /* 0x6e */ 9477/* File: mips64/alt_stub.S */ 9478/* 9479 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9480 * any interesting requests and then jump to the real instruction 9481 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9482 */ 9483 .extern MterpCheckBefore 9484 EXPORT_PC 9485 REFRESH_IBASE 9486 dla ra, artMterpAsmInstructionStart 9487 dla t9, MterpCheckBefore 9488 move a0, rSELF 9489 daddu a1, rFP, OFF_FP_SHADOWFRAME 9490 daddu ra, ra, (110 * 128) # Addr of primary handler. 9491 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9492 9493/* ------------------------------ */ 9494 .balign 128 9495.L_ALT_op_invoke_super: /* 0x6f */ 9496/* File: mips64/alt_stub.S */ 9497/* 9498 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9499 * any interesting requests and then jump to the real instruction 9500 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9501 */ 9502 .extern MterpCheckBefore 9503 EXPORT_PC 9504 REFRESH_IBASE 9505 dla ra, artMterpAsmInstructionStart 9506 dla t9, MterpCheckBefore 9507 move a0, rSELF 9508 daddu a1, rFP, OFF_FP_SHADOWFRAME 9509 daddu ra, ra, (111 * 128) # Addr of primary handler. 9510 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9511 9512/* ------------------------------ */ 9513 .balign 128 9514.L_ALT_op_invoke_direct: /* 0x70 */ 9515/* File: mips64/alt_stub.S */ 9516/* 9517 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9518 * any interesting requests and then jump to the real instruction 9519 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9520 */ 9521 .extern MterpCheckBefore 9522 EXPORT_PC 9523 REFRESH_IBASE 9524 dla ra, artMterpAsmInstructionStart 9525 dla t9, MterpCheckBefore 9526 move a0, rSELF 9527 daddu a1, rFP, OFF_FP_SHADOWFRAME 9528 daddu ra, ra, (112 * 128) # Addr of primary handler. 9529 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9530 9531/* ------------------------------ */ 9532 .balign 128 9533.L_ALT_op_invoke_static: /* 0x71 */ 9534/* File: mips64/alt_stub.S */ 9535/* 9536 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9537 * any interesting requests and then jump to the real instruction 9538 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9539 */ 9540 .extern MterpCheckBefore 9541 EXPORT_PC 9542 REFRESH_IBASE 9543 dla ra, artMterpAsmInstructionStart 9544 dla t9, MterpCheckBefore 9545 move a0, rSELF 9546 daddu a1, rFP, OFF_FP_SHADOWFRAME 9547 daddu ra, ra, (113 * 128) # Addr of primary handler. 9548 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9549 9550/* ------------------------------ */ 9551 .balign 128 9552.L_ALT_op_invoke_interface: /* 0x72 */ 9553/* File: mips64/alt_stub.S */ 9554/* 9555 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9556 * any interesting requests and then jump to the real instruction 9557 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9558 */ 9559 .extern MterpCheckBefore 9560 EXPORT_PC 9561 REFRESH_IBASE 9562 dla ra, artMterpAsmInstructionStart 9563 dla t9, MterpCheckBefore 9564 move a0, rSELF 9565 daddu a1, rFP, OFF_FP_SHADOWFRAME 9566 daddu ra, ra, (114 * 128) # Addr of primary handler. 9567 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9568 9569/* ------------------------------ */ 9570 .balign 128 9571.L_ALT_op_return_void_no_barrier: /* 0x73 */ 9572/* File: mips64/alt_stub.S */ 9573/* 9574 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9575 * any interesting requests and then jump to the real instruction 9576 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9577 */ 9578 .extern MterpCheckBefore 9579 EXPORT_PC 9580 REFRESH_IBASE 9581 dla ra, artMterpAsmInstructionStart 9582 dla t9, MterpCheckBefore 9583 move a0, rSELF 9584 daddu a1, rFP, OFF_FP_SHADOWFRAME 9585 daddu ra, ra, (115 * 128) # Addr of primary handler. 9586 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9587 9588/* ------------------------------ */ 9589 .balign 128 9590.L_ALT_op_invoke_virtual_range: /* 0x74 */ 9591/* File: mips64/alt_stub.S */ 9592/* 9593 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9594 * any interesting requests and then jump to the real instruction 9595 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9596 */ 9597 .extern MterpCheckBefore 9598 EXPORT_PC 9599 REFRESH_IBASE 9600 dla ra, artMterpAsmInstructionStart 9601 dla t9, MterpCheckBefore 9602 move a0, rSELF 9603 daddu a1, rFP, OFF_FP_SHADOWFRAME 9604 daddu ra, ra, (116 * 128) # Addr of primary handler. 9605 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9606 9607/* ------------------------------ */ 9608 .balign 128 9609.L_ALT_op_invoke_super_range: /* 0x75 */ 9610/* File: mips64/alt_stub.S */ 9611/* 9612 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9613 * any interesting requests and then jump to the real instruction 9614 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9615 */ 9616 .extern MterpCheckBefore 9617 EXPORT_PC 9618 REFRESH_IBASE 9619 dla ra, artMterpAsmInstructionStart 9620 dla t9, MterpCheckBefore 9621 move a0, rSELF 9622 daddu a1, rFP, OFF_FP_SHADOWFRAME 9623 daddu ra, ra, (117 * 128) # Addr of primary handler. 9624 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9625 9626/* ------------------------------ */ 9627 .balign 128 9628.L_ALT_op_invoke_direct_range: /* 0x76 */ 9629/* File: mips64/alt_stub.S */ 9630/* 9631 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9632 * any interesting requests and then jump to the real instruction 9633 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9634 */ 9635 .extern MterpCheckBefore 9636 EXPORT_PC 9637 REFRESH_IBASE 9638 dla ra, artMterpAsmInstructionStart 9639 dla t9, MterpCheckBefore 9640 move a0, rSELF 9641 daddu a1, rFP, OFF_FP_SHADOWFRAME 9642 daddu ra, ra, (118 * 128) # Addr of primary handler. 9643 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9644 9645/* ------------------------------ */ 9646 .balign 128 9647.L_ALT_op_invoke_static_range: /* 0x77 */ 9648/* File: mips64/alt_stub.S */ 9649/* 9650 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9651 * any interesting requests and then jump to the real instruction 9652 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9653 */ 9654 .extern MterpCheckBefore 9655 EXPORT_PC 9656 REFRESH_IBASE 9657 dla ra, artMterpAsmInstructionStart 9658 dla t9, MterpCheckBefore 9659 move a0, rSELF 9660 daddu a1, rFP, OFF_FP_SHADOWFRAME 9661 daddu ra, ra, (119 * 128) # Addr of primary handler. 9662 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9663 9664/* ------------------------------ */ 9665 .balign 128 9666.L_ALT_op_invoke_interface_range: /* 0x78 */ 9667/* File: mips64/alt_stub.S */ 9668/* 9669 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9670 * any interesting requests and then jump to the real instruction 9671 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9672 */ 9673 .extern MterpCheckBefore 9674 EXPORT_PC 9675 REFRESH_IBASE 9676 dla ra, artMterpAsmInstructionStart 9677 dla t9, MterpCheckBefore 9678 move a0, rSELF 9679 daddu a1, rFP, OFF_FP_SHADOWFRAME 9680 daddu ra, ra, (120 * 128) # Addr of primary handler. 9681 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9682 9683/* ------------------------------ */ 9684 .balign 128 9685.L_ALT_op_unused_79: /* 0x79 */ 9686/* File: mips64/alt_stub.S */ 9687/* 9688 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9689 * any interesting requests and then jump to the real instruction 9690 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9691 */ 9692 .extern MterpCheckBefore 9693 EXPORT_PC 9694 REFRESH_IBASE 9695 dla ra, artMterpAsmInstructionStart 9696 dla t9, MterpCheckBefore 9697 move a0, rSELF 9698 daddu a1, rFP, OFF_FP_SHADOWFRAME 9699 daddu ra, ra, (121 * 128) # Addr of primary handler. 9700 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9701 9702/* ------------------------------ */ 9703 .balign 128 9704.L_ALT_op_unused_7a: /* 0x7a */ 9705/* File: mips64/alt_stub.S */ 9706/* 9707 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9708 * any interesting requests and then jump to the real instruction 9709 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9710 */ 9711 .extern MterpCheckBefore 9712 EXPORT_PC 9713 REFRESH_IBASE 9714 dla ra, artMterpAsmInstructionStart 9715 dla t9, MterpCheckBefore 9716 move a0, rSELF 9717 daddu a1, rFP, OFF_FP_SHADOWFRAME 9718 daddu ra, ra, (122 * 128) # Addr of primary handler. 9719 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9720 9721/* ------------------------------ */ 9722 .balign 128 9723.L_ALT_op_neg_int: /* 0x7b */ 9724/* File: mips64/alt_stub.S */ 9725/* 9726 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9727 * any interesting requests and then jump to the real instruction 9728 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9729 */ 9730 .extern MterpCheckBefore 9731 EXPORT_PC 9732 REFRESH_IBASE 9733 dla ra, artMterpAsmInstructionStart 9734 dla t9, MterpCheckBefore 9735 move a0, rSELF 9736 daddu a1, rFP, OFF_FP_SHADOWFRAME 9737 daddu ra, ra, (123 * 128) # Addr of primary handler. 9738 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9739 9740/* ------------------------------ */ 9741 .balign 128 9742.L_ALT_op_not_int: /* 0x7c */ 9743/* File: mips64/alt_stub.S */ 9744/* 9745 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9746 * any interesting requests and then jump to the real instruction 9747 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9748 */ 9749 .extern MterpCheckBefore 9750 EXPORT_PC 9751 REFRESH_IBASE 9752 dla ra, artMterpAsmInstructionStart 9753 dla t9, MterpCheckBefore 9754 move a0, rSELF 9755 daddu a1, rFP, OFF_FP_SHADOWFRAME 9756 daddu ra, ra, (124 * 128) # Addr of primary handler. 9757 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9758 9759/* ------------------------------ */ 9760 .balign 128 9761.L_ALT_op_neg_long: /* 0x7d */ 9762/* File: mips64/alt_stub.S */ 9763/* 9764 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9765 * any interesting requests and then jump to the real instruction 9766 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9767 */ 9768 .extern MterpCheckBefore 9769 EXPORT_PC 9770 REFRESH_IBASE 9771 dla ra, artMterpAsmInstructionStart 9772 dla t9, MterpCheckBefore 9773 move a0, rSELF 9774 daddu a1, rFP, OFF_FP_SHADOWFRAME 9775 daddu ra, ra, (125 * 128) # Addr of primary handler. 9776 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9777 9778/* ------------------------------ */ 9779 .balign 128 9780.L_ALT_op_not_long: /* 0x7e */ 9781/* File: mips64/alt_stub.S */ 9782/* 9783 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9784 * any interesting requests and then jump to the real instruction 9785 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9786 */ 9787 .extern MterpCheckBefore 9788 EXPORT_PC 9789 REFRESH_IBASE 9790 dla ra, artMterpAsmInstructionStart 9791 dla t9, MterpCheckBefore 9792 move a0, rSELF 9793 daddu a1, rFP, OFF_FP_SHADOWFRAME 9794 daddu ra, ra, (126 * 128) # Addr of primary handler. 9795 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9796 9797/* ------------------------------ */ 9798 .balign 128 9799.L_ALT_op_neg_float: /* 0x7f */ 9800/* File: mips64/alt_stub.S */ 9801/* 9802 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9803 * any interesting requests and then jump to the real instruction 9804 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9805 */ 9806 .extern MterpCheckBefore 9807 EXPORT_PC 9808 REFRESH_IBASE 9809 dla ra, artMterpAsmInstructionStart 9810 dla t9, MterpCheckBefore 9811 move a0, rSELF 9812 daddu a1, rFP, OFF_FP_SHADOWFRAME 9813 daddu ra, ra, (127 * 128) # Addr of primary handler. 9814 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9815 9816/* ------------------------------ */ 9817 .balign 128 9818.L_ALT_op_neg_double: /* 0x80 */ 9819/* File: mips64/alt_stub.S */ 9820/* 9821 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9822 * any interesting requests and then jump to the real instruction 9823 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9824 */ 9825 .extern MterpCheckBefore 9826 EXPORT_PC 9827 REFRESH_IBASE 9828 dla ra, artMterpAsmInstructionStart 9829 dla t9, MterpCheckBefore 9830 move a0, rSELF 9831 daddu a1, rFP, OFF_FP_SHADOWFRAME 9832 daddu ra, ra, (128 * 128) # Addr of primary handler. 9833 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9834 9835/* ------------------------------ */ 9836 .balign 128 9837.L_ALT_op_int_to_long: /* 0x81 */ 9838/* File: mips64/alt_stub.S */ 9839/* 9840 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9841 * any interesting requests and then jump to the real instruction 9842 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9843 */ 9844 .extern MterpCheckBefore 9845 EXPORT_PC 9846 REFRESH_IBASE 9847 dla ra, artMterpAsmInstructionStart 9848 dla t9, MterpCheckBefore 9849 move a0, rSELF 9850 daddu a1, rFP, OFF_FP_SHADOWFRAME 9851 daddu ra, ra, (129 * 128) # Addr of primary handler. 9852 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9853 9854/* ------------------------------ */ 9855 .balign 128 9856.L_ALT_op_int_to_float: /* 0x82 */ 9857/* File: mips64/alt_stub.S */ 9858/* 9859 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9860 * any interesting requests and then jump to the real instruction 9861 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9862 */ 9863 .extern MterpCheckBefore 9864 EXPORT_PC 9865 REFRESH_IBASE 9866 dla ra, artMterpAsmInstructionStart 9867 dla t9, MterpCheckBefore 9868 move a0, rSELF 9869 daddu a1, rFP, OFF_FP_SHADOWFRAME 9870 daddu ra, ra, (130 * 128) # Addr of primary handler. 9871 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9872 9873/* ------------------------------ */ 9874 .balign 128 9875.L_ALT_op_int_to_double: /* 0x83 */ 9876/* File: mips64/alt_stub.S */ 9877/* 9878 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9879 * any interesting requests and then jump to the real instruction 9880 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9881 */ 9882 .extern MterpCheckBefore 9883 EXPORT_PC 9884 REFRESH_IBASE 9885 dla ra, artMterpAsmInstructionStart 9886 dla t9, MterpCheckBefore 9887 move a0, rSELF 9888 daddu a1, rFP, OFF_FP_SHADOWFRAME 9889 daddu ra, ra, (131 * 128) # Addr of primary handler. 9890 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9891 9892/* ------------------------------ */ 9893 .balign 128 9894.L_ALT_op_long_to_int: /* 0x84 */ 9895/* File: mips64/alt_stub.S */ 9896/* 9897 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9898 * any interesting requests and then jump to the real instruction 9899 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9900 */ 9901 .extern MterpCheckBefore 9902 EXPORT_PC 9903 REFRESH_IBASE 9904 dla ra, artMterpAsmInstructionStart 9905 dla t9, MterpCheckBefore 9906 move a0, rSELF 9907 daddu a1, rFP, OFF_FP_SHADOWFRAME 9908 daddu ra, ra, (132 * 128) # Addr of primary handler. 9909 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9910 9911/* ------------------------------ */ 9912 .balign 128 9913.L_ALT_op_long_to_float: /* 0x85 */ 9914/* File: mips64/alt_stub.S */ 9915/* 9916 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9917 * any interesting requests and then jump to the real instruction 9918 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9919 */ 9920 .extern MterpCheckBefore 9921 EXPORT_PC 9922 REFRESH_IBASE 9923 dla ra, artMterpAsmInstructionStart 9924 dla t9, MterpCheckBefore 9925 move a0, rSELF 9926 daddu a1, rFP, OFF_FP_SHADOWFRAME 9927 daddu ra, ra, (133 * 128) # Addr of primary handler. 9928 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9929 9930/* ------------------------------ */ 9931 .balign 128 9932.L_ALT_op_long_to_double: /* 0x86 */ 9933/* File: mips64/alt_stub.S */ 9934/* 9935 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9936 * any interesting requests and then jump to the real instruction 9937 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9938 */ 9939 .extern MterpCheckBefore 9940 EXPORT_PC 9941 REFRESH_IBASE 9942 dla ra, artMterpAsmInstructionStart 9943 dla t9, MterpCheckBefore 9944 move a0, rSELF 9945 daddu a1, rFP, OFF_FP_SHADOWFRAME 9946 daddu ra, ra, (134 * 128) # Addr of primary handler. 9947 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9948 9949/* ------------------------------ */ 9950 .balign 128 9951.L_ALT_op_float_to_int: /* 0x87 */ 9952/* File: mips64/alt_stub.S */ 9953/* 9954 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9955 * any interesting requests and then jump to the real instruction 9956 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9957 */ 9958 .extern MterpCheckBefore 9959 EXPORT_PC 9960 REFRESH_IBASE 9961 dla ra, artMterpAsmInstructionStart 9962 dla t9, MterpCheckBefore 9963 move a0, rSELF 9964 daddu a1, rFP, OFF_FP_SHADOWFRAME 9965 daddu ra, ra, (135 * 128) # Addr of primary handler. 9966 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9967 9968/* ------------------------------ */ 9969 .balign 128 9970.L_ALT_op_float_to_long: /* 0x88 */ 9971/* File: mips64/alt_stub.S */ 9972/* 9973 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9974 * any interesting requests and then jump to the real instruction 9975 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9976 */ 9977 .extern MterpCheckBefore 9978 EXPORT_PC 9979 REFRESH_IBASE 9980 dla ra, artMterpAsmInstructionStart 9981 dla t9, MterpCheckBefore 9982 move a0, rSELF 9983 daddu a1, rFP, OFF_FP_SHADOWFRAME 9984 daddu ra, ra, (136 * 128) # Addr of primary handler. 9985 jalr zero, t9 # (self, shadow_frame) Note: tail call. 9986 9987/* ------------------------------ */ 9988 .balign 128 9989.L_ALT_op_float_to_double: /* 0x89 */ 9990/* File: mips64/alt_stub.S */ 9991/* 9992 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9993 * any interesting requests and then jump to the real instruction 9994 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9995 */ 9996 .extern MterpCheckBefore 9997 EXPORT_PC 9998 REFRESH_IBASE 9999 dla ra, artMterpAsmInstructionStart 10000 dla t9, MterpCheckBefore 10001 move a0, rSELF 10002 daddu a1, rFP, OFF_FP_SHADOWFRAME 10003 daddu ra, ra, (137 * 128) # Addr of primary handler. 10004 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10005 10006/* ------------------------------ */ 10007 .balign 128 10008.L_ALT_op_double_to_int: /* 0x8a */ 10009/* File: mips64/alt_stub.S */ 10010/* 10011 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10012 * any interesting requests and then jump to the real instruction 10013 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10014 */ 10015 .extern MterpCheckBefore 10016 EXPORT_PC 10017 REFRESH_IBASE 10018 dla ra, artMterpAsmInstructionStart 10019 dla t9, MterpCheckBefore 10020 move a0, rSELF 10021 daddu a1, rFP, OFF_FP_SHADOWFRAME 10022 daddu ra, ra, (138 * 128) # Addr of primary handler. 10023 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10024 10025/* ------------------------------ */ 10026 .balign 128 10027.L_ALT_op_double_to_long: /* 0x8b */ 10028/* File: mips64/alt_stub.S */ 10029/* 10030 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10031 * any interesting requests and then jump to the real instruction 10032 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10033 */ 10034 .extern MterpCheckBefore 10035 EXPORT_PC 10036 REFRESH_IBASE 10037 dla ra, artMterpAsmInstructionStart 10038 dla t9, MterpCheckBefore 10039 move a0, rSELF 10040 daddu a1, rFP, OFF_FP_SHADOWFRAME 10041 daddu ra, ra, (139 * 128) # Addr of primary handler. 10042 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10043 10044/* ------------------------------ */ 10045 .balign 128 10046.L_ALT_op_double_to_float: /* 0x8c */ 10047/* File: mips64/alt_stub.S */ 10048/* 10049 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10050 * any interesting requests and then jump to the real instruction 10051 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10052 */ 10053 .extern MterpCheckBefore 10054 EXPORT_PC 10055 REFRESH_IBASE 10056 dla ra, artMterpAsmInstructionStart 10057 dla t9, MterpCheckBefore 10058 move a0, rSELF 10059 daddu a1, rFP, OFF_FP_SHADOWFRAME 10060 daddu ra, ra, (140 * 128) # Addr of primary handler. 10061 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10062 10063/* ------------------------------ */ 10064 .balign 128 10065.L_ALT_op_int_to_byte: /* 0x8d */ 10066/* File: mips64/alt_stub.S */ 10067/* 10068 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10069 * any interesting requests and then jump to the real instruction 10070 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10071 */ 10072 .extern MterpCheckBefore 10073 EXPORT_PC 10074 REFRESH_IBASE 10075 dla ra, artMterpAsmInstructionStart 10076 dla t9, MterpCheckBefore 10077 move a0, rSELF 10078 daddu a1, rFP, OFF_FP_SHADOWFRAME 10079 daddu ra, ra, (141 * 128) # Addr of primary handler. 10080 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10081 10082/* ------------------------------ */ 10083 .balign 128 10084.L_ALT_op_int_to_char: /* 0x8e */ 10085/* File: mips64/alt_stub.S */ 10086/* 10087 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10088 * any interesting requests and then jump to the real instruction 10089 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10090 */ 10091 .extern MterpCheckBefore 10092 EXPORT_PC 10093 REFRESH_IBASE 10094 dla ra, artMterpAsmInstructionStart 10095 dla t9, MterpCheckBefore 10096 move a0, rSELF 10097 daddu a1, rFP, OFF_FP_SHADOWFRAME 10098 daddu ra, ra, (142 * 128) # Addr of primary handler. 10099 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10100 10101/* ------------------------------ */ 10102 .balign 128 10103.L_ALT_op_int_to_short: /* 0x8f */ 10104/* File: mips64/alt_stub.S */ 10105/* 10106 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10107 * any interesting requests and then jump to the real instruction 10108 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10109 */ 10110 .extern MterpCheckBefore 10111 EXPORT_PC 10112 REFRESH_IBASE 10113 dla ra, artMterpAsmInstructionStart 10114 dla t9, MterpCheckBefore 10115 move a0, rSELF 10116 daddu a1, rFP, OFF_FP_SHADOWFRAME 10117 daddu ra, ra, (143 * 128) # Addr of primary handler. 10118 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10119 10120/* ------------------------------ */ 10121 .balign 128 10122.L_ALT_op_add_int: /* 0x90 */ 10123/* File: mips64/alt_stub.S */ 10124/* 10125 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10126 * any interesting requests and then jump to the real instruction 10127 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10128 */ 10129 .extern MterpCheckBefore 10130 EXPORT_PC 10131 REFRESH_IBASE 10132 dla ra, artMterpAsmInstructionStart 10133 dla t9, MterpCheckBefore 10134 move a0, rSELF 10135 daddu a1, rFP, OFF_FP_SHADOWFRAME 10136 daddu ra, ra, (144 * 128) # Addr of primary handler. 10137 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10138 10139/* ------------------------------ */ 10140 .balign 128 10141.L_ALT_op_sub_int: /* 0x91 */ 10142/* File: mips64/alt_stub.S */ 10143/* 10144 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10145 * any interesting requests and then jump to the real instruction 10146 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10147 */ 10148 .extern MterpCheckBefore 10149 EXPORT_PC 10150 REFRESH_IBASE 10151 dla ra, artMterpAsmInstructionStart 10152 dla t9, MterpCheckBefore 10153 move a0, rSELF 10154 daddu a1, rFP, OFF_FP_SHADOWFRAME 10155 daddu ra, ra, (145 * 128) # Addr of primary handler. 10156 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10157 10158/* ------------------------------ */ 10159 .balign 128 10160.L_ALT_op_mul_int: /* 0x92 */ 10161/* File: mips64/alt_stub.S */ 10162/* 10163 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10164 * any interesting requests and then jump to the real instruction 10165 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10166 */ 10167 .extern MterpCheckBefore 10168 EXPORT_PC 10169 REFRESH_IBASE 10170 dla ra, artMterpAsmInstructionStart 10171 dla t9, MterpCheckBefore 10172 move a0, rSELF 10173 daddu a1, rFP, OFF_FP_SHADOWFRAME 10174 daddu ra, ra, (146 * 128) # Addr of primary handler. 10175 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10176 10177/* ------------------------------ */ 10178 .balign 128 10179.L_ALT_op_div_int: /* 0x93 */ 10180/* File: mips64/alt_stub.S */ 10181/* 10182 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10183 * any interesting requests and then jump to the real instruction 10184 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10185 */ 10186 .extern MterpCheckBefore 10187 EXPORT_PC 10188 REFRESH_IBASE 10189 dla ra, artMterpAsmInstructionStart 10190 dla t9, MterpCheckBefore 10191 move a0, rSELF 10192 daddu a1, rFP, OFF_FP_SHADOWFRAME 10193 daddu ra, ra, (147 * 128) # Addr of primary handler. 10194 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10195 10196/* ------------------------------ */ 10197 .balign 128 10198.L_ALT_op_rem_int: /* 0x94 */ 10199/* File: mips64/alt_stub.S */ 10200/* 10201 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10202 * any interesting requests and then jump to the real instruction 10203 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10204 */ 10205 .extern MterpCheckBefore 10206 EXPORT_PC 10207 REFRESH_IBASE 10208 dla ra, artMterpAsmInstructionStart 10209 dla t9, MterpCheckBefore 10210 move a0, rSELF 10211 daddu a1, rFP, OFF_FP_SHADOWFRAME 10212 daddu ra, ra, (148 * 128) # Addr of primary handler. 10213 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10214 10215/* ------------------------------ */ 10216 .balign 128 10217.L_ALT_op_and_int: /* 0x95 */ 10218/* File: mips64/alt_stub.S */ 10219/* 10220 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10221 * any interesting requests and then jump to the real instruction 10222 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10223 */ 10224 .extern MterpCheckBefore 10225 EXPORT_PC 10226 REFRESH_IBASE 10227 dla ra, artMterpAsmInstructionStart 10228 dla t9, MterpCheckBefore 10229 move a0, rSELF 10230 daddu a1, rFP, OFF_FP_SHADOWFRAME 10231 daddu ra, ra, (149 * 128) # Addr of primary handler. 10232 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10233 10234/* ------------------------------ */ 10235 .balign 128 10236.L_ALT_op_or_int: /* 0x96 */ 10237/* File: mips64/alt_stub.S */ 10238/* 10239 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10240 * any interesting requests and then jump to the real instruction 10241 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10242 */ 10243 .extern MterpCheckBefore 10244 EXPORT_PC 10245 REFRESH_IBASE 10246 dla ra, artMterpAsmInstructionStart 10247 dla t9, MterpCheckBefore 10248 move a0, rSELF 10249 daddu a1, rFP, OFF_FP_SHADOWFRAME 10250 daddu ra, ra, (150 * 128) # Addr of primary handler. 10251 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10252 10253/* ------------------------------ */ 10254 .balign 128 10255.L_ALT_op_xor_int: /* 0x97 */ 10256/* File: mips64/alt_stub.S */ 10257/* 10258 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10259 * any interesting requests and then jump to the real instruction 10260 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10261 */ 10262 .extern MterpCheckBefore 10263 EXPORT_PC 10264 REFRESH_IBASE 10265 dla ra, artMterpAsmInstructionStart 10266 dla t9, MterpCheckBefore 10267 move a0, rSELF 10268 daddu a1, rFP, OFF_FP_SHADOWFRAME 10269 daddu ra, ra, (151 * 128) # Addr of primary handler. 10270 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10271 10272/* ------------------------------ */ 10273 .balign 128 10274.L_ALT_op_shl_int: /* 0x98 */ 10275/* File: mips64/alt_stub.S */ 10276/* 10277 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10278 * any interesting requests and then jump to the real instruction 10279 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10280 */ 10281 .extern MterpCheckBefore 10282 EXPORT_PC 10283 REFRESH_IBASE 10284 dla ra, artMterpAsmInstructionStart 10285 dla t9, MterpCheckBefore 10286 move a0, rSELF 10287 daddu a1, rFP, OFF_FP_SHADOWFRAME 10288 daddu ra, ra, (152 * 128) # Addr of primary handler. 10289 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10290 10291/* ------------------------------ */ 10292 .balign 128 10293.L_ALT_op_shr_int: /* 0x99 */ 10294/* File: mips64/alt_stub.S */ 10295/* 10296 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10297 * any interesting requests and then jump to the real instruction 10298 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10299 */ 10300 .extern MterpCheckBefore 10301 EXPORT_PC 10302 REFRESH_IBASE 10303 dla ra, artMterpAsmInstructionStart 10304 dla t9, MterpCheckBefore 10305 move a0, rSELF 10306 daddu a1, rFP, OFF_FP_SHADOWFRAME 10307 daddu ra, ra, (153 * 128) # Addr of primary handler. 10308 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10309 10310/* ------------------------------ */ 10311 .balign 128 10312.L_ALT_op_ushr_int: /* 0x9a */ 10313/* File: mips64/alt_stub.S */ 10314/* 10315 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10316 * any interesting requests and then jump to the real instruction 10317 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10318 */ 10319 .extern MterpCheckBefore 10320 EXPORT_PC 10321 REFRESH_IBASE 10322 dla ra, artMterpAsmInstructionStart 10323 dla t9, MterpCheckBefore 10324 move a0, rSELF 10325 daddu a1, rFP, OFF_FP_SHADOWFRAME 10326 daddu ra, ra, (154 * 128) # Addr of primary handler. 10327 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10328 10329/* ------------------------------ */ 10330 .balign 128 10331.L_ALT_op_add_long: /* 0x9b */ 10332/* File: mips64/alt_stub.S */ 10333/* 10334 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10335 * any interesting requests and then jump to the real instruction 10336 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10337 */ 10338 .extern MterpCheckBefore 10339 EXPORT_PC 10340 REFRESH_IBASE 10341 dla ra, artMterpAsmInstructionStart 10342 dla t9, MterpCheckBefore 10343 move a0, rSELF 10344 daddu a1, rFP, OFF_FP_SHADOWFRAME 10345 daddu ra, ra, (155 * 128) # Addr of primary handler. 10346 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10347 10348/* ------------------------------ */ 10349 .balign 128 10350.L_ALT_op_sub_long: /* 0x9c */ 10351/* File: mips64/alt_stub.S */ 10352/* 10353 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10354 * any interesting requests and then jump to the real instruction 10355 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10356 */ 10357 .extern MterpCheckBefore 10358 EXPORT_PC 10359 REFRESH_IBASE 10360 dla ra, artMterpAsmInstructionStart 10361 dla t9, MterpCheckBefore 10362 move a0, rSELF 10363 daddu a1, rFP, OFF_FP_SHADOWFRAME 10364 daddu ra, ra, (156 * 128) # Addr of primary handler. 10365 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10366 10367/* ------------------------------ */ 10368 .balign 128 10369.L_ALT_op_mul_long: /* 0x9d */ 10370/* File: mips64/alt_stub.S */ 10371/* 10372 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10373 * any interesting requests and then jump to the real instruction 10374 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10375 */ 10376 .extern MterpCheckBefore 10377 EXPORT_PC 10378 REFRESH_IBASE 10379 dla ra, artMterpAsmInstructionStart 10380 dla t9, MterpCheckBefore 10381 move a0, rSELF 10382 daddu a1, rFP, OFF_FP_SHADOWFRAME 10383 daddu ra, ra, (157 * 128) # Addr of primary handler. 10384 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10385 10386/* ------------------------------ */ 10387 .balign 128 10388.L_ALT_op_div_long: /* 0x9e */ 10389/* File: mips64/alt_stub.S */ 10390/* 10391 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10392 * any interesting requests and then jump to the real instruction 10393 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10394 */ 10395 .extern MterpCheckBefore 10396 EXPORT_PC 10397 REFRESH_IBASE 10398 dla ra, artMterpAsmInstructionStart 10399 dla t9, MterpCheckBefore 10400 move a0, rSELF 10401 daddu a1, rFP, OFF_FP_SHADOWFRAME 10402 daddu ra, ra, (158 * 128) # Addr of primary handler. 10403 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10404 10405/* ------------------------------ */ 10406 .balign 128 10407.L_ALT_op_rem_long: /* 0x9f */ 10408/* File: mips64/alt_stub.S */ 10409/* 10410 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10411 * any interesting requests and then jump to the real instruction 10412 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10413 */ 10414 .extern MterpCheckBefore 10415 EXPORT_PC 10416 REFRESH_IBASE 10417 dla ra, artMterpAsmInstructionStart 10418 dla t9, MterpCheckBefore 10419 move a0, rSELF 10420 daddu a1, rFP, OFF_FP_SHADOWFRAME 10421 daddu ra, ra, (159 * 128) # Addr of primary handler. 10422 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10423 10424/* ------------------------------ */ 10425 .balign 128 10426.L_ALT_op_and_long: /* 0xa0 */ 10427/* File: mips64/alt_stub.S */ 10428/* 10429 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10430 * any interesting requests and then jump to the real instruction 10431 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10432 */ 10433 .extern MterpCheckBefore 10434 EXPORT_PC 10435 REFRESH_IBASE 10436 dla ra, artMterpAsmInstructionStart 10437 dla t9, MterpCheckBefore 10438 move a0, rSELF 10439 daddu a1, rFP, OFF_FP_SHADOWFRAME 10440 daddu ra, ra, (160 * 128) # Addr of primary handler. 10441 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10442 10443/* ------------------------------ */ 10444 .balign 128 10445.L_ALT_op_or_long: /* 0xa1 */ 10446/* File: mips64/alt_stub.S */ 10447/* 10448 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10449 * any interesting requests and then jump to the real instruction 10450 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10451 */ 10452 .extern MterpCheckBefore 10453 EXPORT_PC 10454 REFRESH_IBASE 10455 dla ra, artMterpAsmInstructionStart 10456 dla t9, MterpCheckBefore 10457 move a0, rSELF 10458 daddu a1, rFP, OFF_FP_SHADOWFRAME 10459 daddu ra, ra, (161 * 128) # Addr of primary handler. 10460 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10461 10462/* ------------------------------ */ 10463 .balign 128 10464.L_ALT_op_xor_long: /* 0xa2 */ 10465/* File: mips64/alt_stub.S */ 10466/* 10467 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10468 * any interesting requests and then jump to the real instruction 10469 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10470 */ 10471 .extern MterpCheckBefore 10472 EXPORT_PC 10473 REFRESH_IBASE 10474 dla ra, artMterpAsmInstructionStart 10475 dla t9, MterpCheckBefore 10476 move a0, rSELF 10477 daddu a1, rFP, OFF_FP_SHADOWFRAME 10478 daddu ra, ra, (162 * 128) # Addr of primary handler. 10479 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10480 10481/* ------------------------------ */ 10482 .balign 128 10483.L_ALT_op_shl_long: /* 0xa3 */ 10484/* File: mips64/alt_stub.S */ 10485/* 10486 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10487 * any interesting requests and then jump to the real instruction 10488 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10489 */ 10490 .extern MterpCheckBefore 10491 EXPORT_PC 10492 REFRESH_IBASE 10493 dla ra, artMterpAsmInstructionStart 10494 dla t9, MterpCheckBefore 10495 move a0, rSELF 10496 daddu a1, rFP, OFF_FP_SHADOWFRAME 10497 daddu ra, ra, (163 * 128) # Addr of primary handler. 10498 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10499 10500/* ------------------------------ */ 10501 .balign 128 10502.L_ALT_op_shr_long: /* 0xa4 */ 10503/* File: mips64/alt_stub.S */ 10504/* 10505 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10506 * any interesting requests and then jump to the real instruction 10507 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10508 */ 10509 .extern MterpCheckBefore 10510 EXPORT_PC 10511 REFRESH_IBASE 10512 dla ra, artMterpAsmInstructionStart 10513 dla t9, MterpCheckBefore 10514 move a0, rSELF 10515 daddu a1, rFP, OFF_FP_SHADOWFRAME 10516 daddu ra, ra, (164 * 128) # Addr of primary handler. 10517 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10518 10519/* ------------------------------ */ 10520 .balign 128 10521.L_ALT_op_ushr_long: /* 0xa5 */ 10522/* File: mips64/alt_stub.S */ 10523/* 10524 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10525 * any interesting requests and then jump to the real instruction 10526 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10527 */ 10528 .extern MterpCheckBefore 10529 EXPORT_PC 10530 REFRESH_IBASE 10531 dla ra, artMterpAsmInstructionStart 10532 dla t9, MterpCheckBefore 10533 move a0, rSELF 10534 daddu a1, rFP, OFF_FP_SHADOWFRAME 10535 daddu ra, ra, (165 * 128) # Addr of primary handler. 10536 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10537 10538/* ------------------------------ */ 10539 .balign 128 10540.L_ALT_op_add_float: /* 0xa6 */ 10541/* File: mips64/alt_stub.S */ 10542/* 10543 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10544 * any interesting requests and then jump to the real instruction 10545 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10546 */ 10547 .extern MterpCheckBefore 10548 EXPORT_PC 10549 REFRESH_IBASE 10550 dla ra, artMterpAsmInstructionStart 10551 dla t9, MterpCheckBefore 10552 move a0, rSELF 10553 daddu a1, rFP, OFF_FP_SHADOWFRAME 10554 daddu ra, ra, (166 * 128) # Addr of primary handler. 10555 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10556 10557/* ------------------------------ */ 10558 .balign 128 10559.L_ALT_op_sub_float: /* 0xa7 */ 10560/* File: mips64/alt_stub.S */ 10561/* 10562 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10563 * any interesting requests and then jump to the real instruction 10564 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10565 */ 10566 .extern MterpCheckBefore 10567 EXPORT_PC 10568 REFRESH_IBASE 10569 dla ra, artMterpAsmInstructionStart 10570 dla t9, MterpCheckBefore 10571 move a0, rSELF 10572 daddu a1, rFP, OFF_FP_SHADOWFRAME 10573 daddu ra, ra, (167 * 128) # Addr of primary handler. 10574 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10575 10576/* ------------------------------ */ 10577 .balign 128 10578.L_ALT_op_mul_float: /* 0xa8 */ 10579/* File: mips64/alt_stub.S */ 10580/* 10581 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10582 * any interesting requests and then jump to the real instruction 10583 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10584 */ 10585 .extern MterpCheckBefore 10586 EXPORT_PC 10587 REFRESH_IBASE 10588 dla ra, artMterpAsmInstructionStart 10589 dla t9, MterpCheckBefore 10590 move a0, rSELF 10591 daddu a1, rFP, OFF_FP_SHADOWFRAME 10592 daddu ra, ra, (168 * 128) # Addr of primary handler. 10593 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10594 10595/* ------------------------------ */ 10596 .balign 128 10597.L_ALT_op_div_float: /* 0xa9 */ 10598/* File: mips64/alt_stub.S */ 10599/* 10600 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10601 * any interesting requests and then jump to the real instruction 10602 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10603 */ 10604 .extern MterpCheckBefore 10605 EXPORT_PC 10606 REFRESH_IBASE 10607 dla ra, artMterpAsmInstructionStart 10608 dla t9, MterpCheckBefore 10609 move a0, rSELF 10610 daddu a1, rFP, OFF_FP_SHADOWFRAME 10611 daddu ra, ra, (169 * 128) # Addr of primary handler. 10612 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10613 10614/* ------------------------------ */ 10615 .balign 128 10616.L_ALT_op_rem_float: /* 0xaa */ 10617/* File: mips64/alt_stub.S */ 10618/* 10619 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10620 * any interesting requests and then jump to the real instruction 10621 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10622 */ 10623 .extern MterpCheckBefore 10624 EXPORT_PC 10625 REFRESH_IBASE 10626 dla ra, artMterpAsmInstructionStart 10627 dla t9, MterpCheckBefore 10628 move a0, rSELF 10629 daddu a1, rFP, OFF_FP_SHADOWFRAME 10630 daddu ra, ra, (170 * 128) # Addr of primary handler. 10631 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10632 10633/* ------------------------------ */ 10634 .balign 128 10635.L_ALT_op_add_double: /* 0xab */ 10636/* File: mips64/alt_stub.S */ 10637/* 10638 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10639 * any interesting requests and then jump to the real instruction 10640 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10641 */ 10642 .extern MterpCheckBefore 10643 EXPORT_PC 10644 REFRESH_IBASE 10645 dla ra, artMterpAsmInstructionStart 10646 dla t9, MterpCheckBefore 10647 move a0, rSELF 10648 daddu a1, rFP, OFF_FP_SHADOWFRAME 10649 daddu ra, ra, (171 * 128) # Addr of primary handler. 10650 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10651 10652/* ------------------------------ */ 10653 .balign 128 10654.L_ALT_op_sub_double: /* 0xac */ 10655/* File: mips64/alt_stub.S */ 10656/* 10657 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10658 * any interesting requests and then jump to the real instruction 10659 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10660 */ 10661 .extern MterpCheckBefore 10662 EXPORT_PC 10663 REFRESH_IBASE 10664 dla ra, artMterpAsmInstructionStart 10665 dla t9, MterpCheckBefore 10666 move a0, rSELF 10667 daddu a1, rFP, OFF_FP_SHADOWFRAME 10668 daddu ra, ra, (172 * 128) # Addr of primary handler. 10669 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10670 10671/* ------------------------------ */ 10672 .balign 128 10673.L_ALT_op_mul_double: /* 0xad */ 10674/* File: mips64/alt_stub.S */ 10675/* 10676 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10677 * any interesting requests and then jump to the real instruction 10678 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10679 */ 10680 .extern MterpCheckBefore 10681 EXPORT_PC 10682 REFRESH_IBASE 10683 dla ra, artMterpAsmInstructionStart 10684 dla t9, MterpCheckBefore 10685 move a0, rSELF 10686 daddu a1, rFP, OFF_FP_SHADOWFRAME 10687 daddu ra, ra, (173 * 128) # Addr of primary handler. 10688 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10689 10690/* ------------------------------ */ 10691 .balign 128 10692.L_ALT_op_div_double: /* 0xae */ 10693/* File: mips64/alt_stub.S */ 10694/* 10695 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10696 * any interesting requests and then jump to the real instruction 10697 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10698 */ 10699 .extern MterpCheckBefore 10700 EXPORT_PC 10701 REFRESH_IBASE 10702 dla ra, artMterpAsmInstructionStart 10703 dla t9, MterpCheckBefore 10704 move a0, rSELF 10705 daddu a1, rFP, OFF_FP_SHADOWFRAME 10706 daddu ra, ra, (174 * 128) # Addr of primary handler. 10707 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10708 10709/* ------------------------------ */ 10710 .balign 128 10711.L_ALT_op_rem_double: /* 0xaf */ 10712/* File: mips64/alt_stub.S */ 10713/* 10714 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10715 * any interesting requests and then jump to the real instruction 10716 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10717 */ 10718 .extern MterpCheckBefore 10719 EXPORT_PC 10720 REFRESH_IBASE 10721 dla ra, artMterpAsmInstructionStart 10722 dla t9, MterpCheckBefore 10723 move a0, rSELF 10724 daddu a1, rFP, OFF_FP_SHADOWFRAME 10725 daddu ra, ra, (175 * 128) # Addr of primary handler. 10726 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10727 10728/* ------------------------------ */ 10729 .balign 128 10730.L_ALT_op_add_int_2addr: /* 0xb0 */ 10731/* File: mips64/alt_stub.S */ 10732/* 10733 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10734 * any interesting requests and then jump to the real instruction 10735 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10736 */ 10737 .extern MterpCheckBefore 10738 EXPORT_PC 10739 REFRESH_IBASE 10740 dla ra, artMterpAsmInstructionStart 10741 dla t9, MterpCheckBefore 10742 move a0, rSELF 10743 daddu a1, rFP, OFF_FP_SHADOWFRAME 10744 daddu ra, ra, (176 * 128) # Addr of primary handler. 10745 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10746 10747/* ------------------------------ */ 10748 .balign 128 10749.L_ALT_op_sub_int_2addr: /* 0xb1 */ 10750/* File: mips64/alt_stub.S */ 10751/* 10752 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10753 * any interesting requests and then jump to the real instruction 10754 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10755 */ 10756 .extern MterpCheckBefore 10757 EXPORT_PC 10758 REFRESH_IBASE 10759 dla ra, artMterpAsmInstructionStart 10760 dla t9, MterpCheckBefore 10761 move a0, rSELF 10762 daddu a1, rFP, OFF_FP_SHADOWFRAME 10763 daddu ra, ra, (177 * 128) # Addr of primary handler. 10764 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10765 10766/* ------------------------------ */ 10767 .balign 128 10768.L_ALT_op_mul_int_2addr: /* 0xb2 */ 10769/* File: mips64/alt_stub.S */ 10770/* 10771 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10772 * any interesting requests and then jump to the real instruction 10773 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10774 */ 10775 .extern MterpCheckBefore 10776 EXPORT_PC 10777 REFRESH_IBASE 10778 dla ra, artMterpAsmInstructionStart 10779 dla t9, MterpCheckBefore 10780 move a0, rSELF 10781 daddu a1, rFP, OFF_FP_SHADOWFRAME 10782 daddu ra, ra, (178 * 128) # Addr of primary handler. 10783 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10784 10785/* ------------------------------ */ 10786 .balign 128 10787.L_ALT_op_div_int_2addr: /* 0xb3 */ 10788/* File: mips64/alt_stub.S */ 10789/* 10790 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10791 * any interesting requests and then jump to the real instruction 10792 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10793 */ 10794 .extern MterpCheckBefore 10795 EXPORT_PC 10796 REFRESH_IBASE 10797 dla ra, artMterpAsmInstructionStart 10798 dla t9, MterpCheckBefore 10799 move a0, rSELF 10800 daddu a1, rFP, OFF_FP_SHADOWFRAME 10801 daddu ra, ra, (179 * 128) # Addr of primary handler. 10802 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10803 10804/* ------------------------------ */ 10805 .balign 128 10806.L_ALT_op_rem_int_2addr: /* 0xb4 */ 10807/* File: mips64/alt_stub.S */ 10808/* 10809 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10810 * any interesting requests and then jump to the real instruction 10811 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10812 */ 10813 .extern MterpCheckBefore 10814 EXPORT_PC 10815 REFRESH_IBASE 10816 dla ra, artMterpAsmInstructionStart 10817 dla t9, MterpCheckBefore 10818 move a0, rSELF 10819 daddu a1, rFP, OFF_FP_SHADOWFRAME 10820 daddu ra, ra, (180 * 128) # Addr of primary handler. 10821 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10822 10823/* ------------------------------ */ 10824 .balign 128 10825.L_ALT_op_and_int_2addr: /* 0xb5 */ 10826/* File: mips64/alt_stub.S */ 10827/* 10828 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10829 * any interesting requests and then jump to the real instruction 10830 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10831 */ 10832 .extern MterpCheckBefore 10833 EXPORT_PC 10834 REFRESH_IBASE 10835 dla ra, artMterpAsmInstructionStart 10836 dla t9, MterpCheckBefore 10837 move a0, rSELF 10838 daddu a1, rFP, OFF_FP_SHADOWFRAME 10839 daddu ra, ra, (181 * 128) # Addr of primary handler. 10840 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10841 10842/* ------------------------------ */ 10843 .balign 128 10844.L_ALT_op_or_int_2addr: /* 0xb6 */ 10845/* File: mips64/alt_stub.S */ 10846/* 10847 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10848 * any interesting requests and then jump to the real instruction 10849 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10850 */ 10851 .extern MterpCheckBefore 10852 EXPORT_PC 10853 REFRESH_IBASE 10854 dla ra, artMterpAsmInstructionStart 10855 dla t9, MterpCheckBefore 10856 move a0, rSELF 10857 daddu a1, rFP, OFF_FP_SHADOWFRAME 10858 daddu ra, ra, (182 * 128) # Addr of primary handler. 10859 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10860 10861/* ------------------------------ */ 10862 .balign 128 10863.L_ALT_op_xor_int_2addr: /* 0xb7 */ 10864/* File: mips64/alt_stub.S */ 10865/* 10866 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10867 * any interesting requests and then jump to the real instruction 10868 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10869 */ 10870 .extern MterpCheckBefore 10871 EXPORT_PC 10872 REFRESH_IBASE 10873 dla ra, artMterpAsmInstructionStart 10874 dla t9, MterpCheckBefore 10875 move a0, rSELF 10876 daddu a1, rFP, OFF_FP_SHADOWFRAME 10877 daddu ra, ra, (183 * 128) # Addr of primary handler. 10878 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10879 10880/* ------------------------------ */ 10881 .balign 128 10882.L_ALT_op_shl_int_2addr: /* 0xb8 */ 10883/* File: mips64/alt_stub.S */ 10884/* 10885 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10886 * any interesting requests and then jump to the real instruction 10887 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10888 */ 10889 .extern MterpCheckBefore 10890 EXPORT_PC 10891 REFRESH_IBASE 10892 dla ra, artMterpAsmInstructionStart 10893 dla t9, MterpCheckBefore 10894 move a0, rSELF 10895 daddu a1, rFP, OFF_FP_SHADOWFRAME 10896 daddu ra, ra, (184 * 128) # Addr of primary handler. 10897 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10898 10899/* ------------------------------ */ 10900 .balign 128 10901.L_ALT_op_shr_int_2addr: /* 0xb9 */ 10902/* File: mips64/alt_stub.S */ 10903/* 10904 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10905 * any interesting requests and then jump to the real instruction 10906 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10907 */ 10908 .extern MterpCheckBefore 10909 EXPORT_PC 10910 REFRESH_IBASE 10911 dla ra, artMterpAsmInstructionStart 10912 dla t9, MterpCheckBefore 10913 move a0, rSELF 10914 daddu a1, rFP, OFF_FP_SHADOWFRAME 10915 daddu ra, ra, (185 * 128) # Addr of primary handler. 10916 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10917 10918/* ------------------------------ */ 10919 .balign 128 10920.L_ALT_op_ushr_int_2addr: /* 0xba */ 10921/* File: mips64/alt_stub.S */ 10922/* 10923 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10924 * any interesting requests and then jump to the real instruction 10925 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10926 */ 10927 .extern MterpCheckBefore 10928 EXPORT_PC 10929 REFRESH_IBASE 10930 dla ra, artMterpAsmInstructionStart 10931 dla t9, MterpCheckBefore 10932 move a0, rSELF 10933 daddu a1, rFP, OFF_FP_SHADOWFRAME 10934 daddu ra, ra, (186 * 128) # Addr of primary handler. 10935 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10936 10937/* ------------------------------ */ 10938 .balign 128 10939.L_ALT_op_add_long_2addr: /* 0xbb */ 10940/* File: mips64/alt_stub.S */ 10941/* 10942 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10943 * any interesting requests and then jump to the real instruction 10944 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10945 */ 10946 .extern MterpCheckBefore 10947 EXPORT_PC 10948 REFRESH_IBASE 10949 dla ra, artMterpAsmInstructionStart 10950 dla t9, MterpCheckBefore 10951 move a0, rSELF 10952 daddu a1, rFP, OFF_FP_SHADOWFRAME 10953 daddu ra, ra, (187 * 128) # Addr of primary handler. 10954 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10955 10956/* ------------------------------ */ 10957 .balign 128 10958.L_ALT_op_sub_long_2addr: /* 0xbc */ 10959/* File: mips64/alt_stub.S */ 10960/* 10961 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10962 * any interesting requests and then jump to the real instruction 10963 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10964 */ 10965 .extern MterpCheckBefore 10966 EXPORT_PC 10967 REFRESH_IBASE 10968 dla ra, artMterpAsmInstructionStart 10969 dla t9, MterpCheckBefore 10970 move a0, rSELF 10971 daddu a1, rFP, OFF_FP_SHADOWFRAME 10972 daddu ra, ra, (188 * 128) # Addr of primary handler. 10973 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10974 10975/* ------------------------------ */ 10976 .balign 128 10977.L_ALT_op_mul_long_2addr: /* 0xbd */ 10978/* File: mips64/alt_stub.S */ 10979/* 10980 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10981 * any interesting requests and then jump to the real instruction 10982 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10983 */ 10984 .extern MterpCheckBefore 10985 EXPORT_PC 10986 REFRESH_IBASE 10987 dla ra, artMterpAsmInstructionStart 10988 dla t9, MterpCheckBefore 10989 move a0, rSELF 10990 daddu a1, rFP, OFF_FP_SHADOWFRAME 10991 daddu ra, ra, (189 * 128) # Addr of primary handler. 10992 jalr zero, t9 # (self, shadow_frame) Note: tail call. 10993 10994/* ------------------------------ */ 10995 .balign 128 10996.L_ALT_op_div_long_2addr: /* 0xbe */ 10997/* File: mips64/alt_stub.S */ 10998/* 10999 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11000 * any interesting requests and then jump to the real instruction 11001 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11002 */ 11003 .extern MterpCheckBefore 11004 EXPORT_PC 11005 REFRESH_IBASE 11006 dla ra, artMterpAsmInstructionStart 11007 dla t9, MterpCheckBefore 11008 move a0, rSELF 11009 daddu a1, rFP, OFF_FP_SHADOWFRAME 11010 daddu ra, ra, (190 * 128) # Addr of primary handler. 11011 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11012 11013/* ------------------------------ */ 11014 .balign 128 11015.L_ALT_op_rem_long_2addr: /* 0xbf */ 11016/* File: mips64/alt_stub.S */ 11017/* 11018 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11019 * any interesting requests and then jump to the real instruction 11020 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11021 */ 11022 .extern MterpCheckBefore 11023 EXPORT_PC 11024 REFRESH_IBASE 11025 dla ra, artMterpAsmInstructionStart 11026 dla t9, MterpCheckBefore 11027 move a0, rSELF 11028 daddu a1, rFP, OFF_FP_SHADOWFRAME 11029 daddu ra, ra, (191 * 128) # Addr of primary handler. 11030 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11031 11032/* ------------------------------ */ 11033 .balign 128 11034.L_ALT_op_and_long_2addr: /* 0xc0 */ 11035/* File: mips64/alt_stub.S */ 11036/* 11037 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11038 * any interesting requests and then jump to the real instruction 11039 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11040 */ 11041 .extern MterpCheckBefore 11042 EXPORT_PC 11043 REFRESH_IBASE 11044 dla ra, artMterpAsmInstructionStart 11045 dla t9, MterpCheckBefore 11046 move a0, rSELF 11047 daddu a1, rFP, OFF_FP_SHADOWFRAME 11048 daddu ra, ra, (192 * 128) # Addr of primary handler. 11049 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11050 11051/* ------------------------------ */ 11052 .balign 128 11053.L_ALT_op_or_long_2addr: /* 0xc1 */ 11054/* File: mips64/alt_stub.S */ 11055/* 11056 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11057 * any interesting requests and then jump to the real instruction 11058 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11059 */ 11060 .extern MterpCheckBefore 11061 EXPORT_PC 11062 REFRESH_IBASE 11063 dla ra, artMterpAsmInstructionStart 11064 dla t9, MterpCheckBefore 11065 move a0, rSELF 11066 daddu a1, rFP, OFF_FP_SHADOWFRAME 11067 daddu ra, ra, (193 * 128) # Addr of primary handler. 11068 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11069 11070/* ------------------------------ */ 11071 .balign 128 11072.L_ALT_op_xor_long_2addr: /* 0xc2 */ 11073/* File: mips64/alt_stub.S */ 11074/* 11075 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11076 * any interesting requests and then jump to the real instruction 11077 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11078 */ 11079 .extern MterpCheckBefore 11080 EXPORT_PC 11081 REFRESH_IBASE 11082 dla ra, artMterpAsmInstructionStart 11083 dla t9, MterpCheckBefore 11084 move a0, rSELF 11085 daddu a1, rFP, OFF_FP_SHADOWFRAME 11086 daddu ra, ra, (194 * 128) # Addr of primary handler. 11087 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11088 11089/* ------------------------------ */ 11090 .balign 128 11091.L_ALT_op_shl_long_2addr: /* 0xc3 */ 11092/* File: mips64/alt_stub.S */ 11093/* 11094 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11095 * any interesting requests and then jump to the real instruction 11096 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11097 */ 11098 .extern MterpCheckBefore 11099 EXPORT_PC 11100 REFRESH_IBASE 11101 dla ra, artMterpAsmInstructionStart 11102 dla t9, MterpCheckBefore 11103 move a0, rSELF 11104 daddu a1, rFP, OFF_FP_SHADOWFRAME 11105 daddu ra, ra, (195 * 128) # Addr of primary handler. 11106 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11107 11108/* ------------------------------ */ 11109 .balign 128 11110.L_ALT_op_shr_long_2addr: /* 0xc4 */ 11111/* File: mips64/alt_stub.S */ 11112/* 11113 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11114 * any interesting requests and then jump to the real instruction 11115 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11116 */ 11117 .extern MterpCheckBefore 11118 EXPORT_PC 11119 REFRESH_IBASE 11120 dla ra, artMterpAsmInstructionStart 11121 dla t9, MterpCheckBefore 11122 move a0, rSELF 11123 daddu a1, rFP, OFF_FP_SHADOWFRAME 11124 daddu ra, ra, (196 * 128) # Addr of primary handler. 11125 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11126 11127/* ------------------------------ */ 11128 .balign 128 11129.L_ALT_op_ushr_long_2addr: /* 0xc5 */ 11130/* File: mips64/alt_stub.S */ 11131/* 11132 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11133 * any interesting requests and then jump to the real instruction 11134 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11135 */ 11136 .extern MterpCheckBefore 11137 EXPORT_PC 11138 REFRESH_IBASE 11139 dla ra, artMterpAsmInstructionStart 11140 dla t9, MterpCheckBefore 11141 move a0, rSELF 11142 daddu a1, rFP, OFF_FP_SHADOWFRAME 11143 daddu ra, ra, (197 * 128) # Addr of primary handler. 11144 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11145 11146/* ------------------------------ */ 11147 .balign 128 11148.L_ALT_op_add_float_2addr: /* 0xc6 */ 11149/* File: mips64/alt_stub.S */ 11150/* 11151 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11152 * any interesting requests and then jump to the real instruction 11153 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11154 */ 11155 .extern MterpCheckBefore 11156 EXPORT_PC 11157 REFRESH_IBASE 11158 dla ra, artMterpAsmInstructionStart 11159 dla t9, MterpCheckBefore 11160 move a0, rSELF 11161 daddu a1, rFP, OFF_FP_SHADOWFRAME 11162 daddu ra, ra, (198 * 128) # Addr of primary handler. 11163 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11164 11165/* ------------------------------ */ 11166 .balign 128 11167.L_ALT_op_sub_float_2addr: /* 0xc7 */ 11168/* File: mips64/alt_stub.S */ 11169/* 11170 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11171 * any interesting requests and then jump to the real instruction 11172 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11173 */ 11174 .extern MterpCheckBefore 11175 EXPORT_PC 11176 REFRESH_IBASE 11177 dla ra, artMterpAsmInstructionStart 11178 dla t9, MterpCheckBefore 11179 move a0, rSELF 11180 daddu a1, rFP, OFF_FP_SHADOWFRAME 11181 daddu ra, ra, (199 * 128) # Addr of primary handler. 11182 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11183 11184/* ------------------------------ */ 11185 .balign 128 11186.L_ALT_op_mul_float_2addr: /* 0xc8 */ 11187/* File: mips64/alt_stub.S */ 11188/* 11189 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11190 * any interesting requests and then jump to the real instruction 11191 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11192 */ 11193 .extern MterpCheckBefore 11194 EXPORT_PC 11195 REFRESH_IBASE 11196 dla ra, artMterpAsmInstructionStart 11197 dla t9, MterpCheckBefore 11198 move a0, rSELF 11199 daddu a1, rFP, OFF_FP_SHADOWFRAME 11200 daddu ra, ra, (200 * 128) # Addr of primary handler. 11201 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11202 11203/* ------------------------------ */ 11204 .balign 128 11205.L_ALT_op_div_float_2addr: /* 0xc9 */ 11206/* File: mips64/alt_stub.S */ 11207/* 11208 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11209 * any interesting requests and then jump to the real instruction 11210 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11211 */ 11212 .extern MterpCheckBefore 11213 EXPORT_PC 11214 REFRESH_IBASE 11215 dla ra, artMterpAsmInstructionStart 11216 dla t9, MterpCheckBefore 11217 move a0, rSELF 11218 daddu a1, rFP, OFF_FP_SHADOWFRAME 11219 daddu ra, ra, (201 * 128) # Addr of primary handler. 11220 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11221 11222/* ------------------------------ */ 11223 .balign 128 11224.L_ALT_op_rem_float_2addr: /* 0xca */ 11225/* File: mips64/alt_stub.S */ 11226/* 11227 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11228 * any interesting requests and then jump to the real instruction 11229 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11230 */ 11231 .extern MterpCheckBefore 11232 EXPORT_PC 11233 REFRESH_IBASE 11234 dla ra, artMterpAsmInstructionStart 11235 dla t9, MterpCheckBefore 11236 move a0, rSELF 11237 daddu a1, rFP, OFF_FP_SHADOWFRAME 11238 daddu ra, ra, (202 * 128) # Addr of primary handler. 11239 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11240 11241/* ------------------------------ */ 11242 .balign 128 11243.L_ALT_op_add_double_2addr: /* 0xcb */ 11244/* File: mips64/alt_stub.S */ 11245/* 11246 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11247 * any interesting requests and then jump to the real instruction 11248 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11249 */ 11250 .extern MterpCheckBefore 11251 EXPORT_PC 11252 REFRESH_IBASE 11253 dla ra, artMterpAsmInstructionStart 11254 dla t9, MterpCheckBefore 11255 move a0, rSELF 11256 daddu a1, rFP, OFF_FP_SHADOWFRAME 11257 daddu ra, ra, (203 * 128) # Addr of primary handler. 11258 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11259 11260/* ------------------------------ */ 11261 .balign 128 11262.L_ALT_op_sub_double_2addr: /* 0xcc */ 11263/* File: mips64/alt_stub.S */ 11264/* 11265 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11266 * any interesting requests and then jump to the real instruction 11267 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11268 */ 11269 .extern MterpCheckBefore 11270 EXPORT_PC 11271 REFRESH_IBASE 11272 dla ra, artMterpAsmInstructionStart 11273 dla t9, MterpCheckBefore 11274 move a0, rSELF 11275 daddu a1, rFP, OFF_FP_SHADOWFRAME 11276 daddu ra, ra, (204 * 128) # Addr of primary handler. 11277 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11278 11279/* ------------------------------ */ 11280 .balign 128 11281.L_ALT_op_mul_double_2addr: /* 0xcd */ 11282/* File: mips64/alt_stub.S */ 11283/* 11284 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11285 * any interesting requests and then jump to the real instruction 11286 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11287 */ 11288 .extern MterpCheckBefore 11289 EXPORT_PC 11290 REFRESH_IBASE 11291 dla ra, artMterpAsmInstructionStart 11292 dla t9, MterpCheckBefore 11293 move a0, rSELF 11294 daddu a1, rFP, OFF_FP_SHADOWFRAME 11295 daddu ra, ra, (205 * 128) # Addr of primary handler. 11296 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11297 11298/* ------------------------------ */ 11299 .balign 128 11300.L_ALT_op_div_double_2addr: /* 0xce */ 11301/* File: mips64/alt_stub.S */ 11302/* 11303 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11304 * any interesting requests and then jump to the real instruction 11305 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11306 */ 11307 .extern MterpCheckBefore 11308 EXPORT_PC 11309 REFRESH_IBASE 11310 dla ra, artMterpAsmInstructionStart 11311 dla t9, MterpCheckBefore 11312 move a0, rSELF 11313 daddu a1, rFP, OFF_FP_SHADOWFRAME 11314 daddu ra, ra, (206 * 128) # Addr of primary handler. 11315 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11316 11317/* ------------------------------ */ 11318 .balign 128 11319.L_ALT_op_rem_double_2addr: /* 0xcf */ 11320/* File: mips64/alt_stub.S */ 11321/* 11322 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11323 * any interesting requests and then jump to the real instruction 11324 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11325 */ 11326 .extern MterpCheckBefore 11327 EXPORT_PC 11328 REFRESH_IBASE 11329 dla ra, artMterpAsmInstructionStart 11330 dla t9, MterpCheckBefore 11331 move a0, rSELF 11332 daddu a1, rFP, OFF_FP_SHADOWFRAME 11333 daddu ra, ra, (207 * 128) # Addr of primary handler. 11334 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11335 11336/* ------------------------------ */ 11337 .balign 128 11338.L_ALT_op_add_int_lit16: /* 0xd0 */ 11339/* File: mips64/alt_stub.S */ 11340/* 11341 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11342 * any interesting requests and then jump to the real instruction 11343 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11344 */ 11345 .extern MterpCheckBefore 11346 EXPORT_PC 11347 REFRESH_IBASE 11348 dla ra, artMterpAsmInstructionStart 11349 dla t9, MterpCheckBefore 11350 move a0, rSELF 11351 daddu a1, rFP, OFF_FP_SHADOWFRAME 11352 daddu ra, ra, (208 * 128) # Addr of primary handler. 11353 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11354 11355/* ------------------------------ */ 11356 .balign 128 11357.L_ALT_op_rsub_int: /* 0xd1 */ 11358/* File: mips64/alt_stub.S */ 11359/* 11360 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11361 * any interesting requests and then jump to the real instruction 11362 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11363 */ 11364 .extern MterpCheckBefore 11365 EXPORT_PC 11366 REFRESH_IBASE 11367 dla ra, artMterpAsmInstructionStart 11368 dla t9, MterpCheckBefore 11369 move a0, rSELF 11370 daddu a1, rFP, OFF_FP_SHADOWFRAME 11371 daddu ra, ra, (209 * 128) # Addr of primary handler. 11372 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11373 11374/* ------------------------------ */ 11375 .balign 128 11376.L_ALT_op_mul_int_lit16: /* 0xd2 */ 11377/* File: mips64/alt_stub.S */ 11378/* 11379 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11380 * any interesting requests and then jump to the real instruction 11381 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11382 */ 11383 .extern MterpCheckBefore 11384 EXPORT_PC 11385 REFRESH_IBASE 11386 dla ra, artMterpAsmInstructionStart 11387 dla t9, MterpCheckBefore 11388 move a0, rSELF 11389 daddu a1, rFP, OFF_FP_SHADOWFRAME 11390 daddu ra, ra, (210 * 128) # Addr of primary handler. 11391 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11392 11393/* ------------------------------ */ 11394 .balign 128 11395.L_ALT_op_div_int_lit16: /* 0xd3 */ 11396/* File: mips64/alt_stub.S */ 11397/* 11398 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11399 * any interesting requests and then jump to the real instruction 11400 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11401 */ 11402 .extern MterpCheckBefore 11403 EXPORT_PC 11404 REFRESH_IBASE 11405 dla ra, artMterpAsmInstructionStart 11406 dla t9, MterpCheckBefore 11407 move a0, rSELF 11408 daddu a1, rFP, OFF_FP_SHADOWFRAME 11409 daddu ra, ra, (211 * 128) # Addr of primary handler. 11410 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11411 11412/* ------------------------------ */ 11413 .balign 128 11414.L_ALT_op_rem_int_lit16: /* 0xd4 */ 11415/* File: mips64/alt_stub.S */ 11416/* 11417 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11418 * any interesting requests and then jump to the real instruction 11419 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11420 */ 11421 .extern MterpCheckBefore 11422 EXPORT_PC 11423 REFRESH_IBASE 11424 dla ra, artMterpAsmInstructionStart 11425 dla t9, MterpCheckBefore 11426 move a0, rSELF 11427 daddu a1, rFP, OFF_FP_SHADOWFRAME 11428 daddu ra, ra, (212 * 128) # Addr of primary handler. 11429 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11430 11431/* ------------------------------ */ 11432 .balign 128 11433.L_ALT_op_and_int_lit16: /* 0xd5 */ 11434/* File: mips64/alt_stub.S */ 11435/* 11436 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11437 * any interesting requests and then jump to the real instruction 11438 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11439 */ 11440 .extern MterpCheckBefore 11441 EXPORT_PC 11442 REFRESH_IBASE 11443 dla ra, artMterpAsmInstructionStart 11444 dla t9, MterpCheckBefore 11445 move a0, rSELF 11446 daddu a1, rFP, OFF_FP_SHADOWFRAME 11447 daddu ra, ra, (213 * 128) # Addr of primary handler. 11448 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11449 11450/* ------------------------------ */ 11451 .balign 128 11452.L_ALT_op_or_int_lit16: /* 0xd6 */ 11453/* File: mips64/alt_stub.S */ 11454/* 11455 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11456 * any interesting requests and then jump to the real instruction 11457 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11458 */ 11459 .extern MterpCheckBefore 11460 EXPORT_PC 11461 REFRESH_IBASE 11462 dla ra, artMterpAsmInstructionStart 11463 dla t9, MterpCheckBefore 11464 move a0, rSELF 11465 daddu a1, rFP, OFF_FP_SHADOWFRAME 11466 daddu ra, ra, (214 * 128) # Addr of primary handler. 11467 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11468 11469/* ------------------------------ */ 11470 .balign 128 11471.L_ALT_op_xor_int_lit16: /* 0xd7 */ 11472/* File: mips64/alt_stub.S */ 11473/* 11474 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11475 * any interesting requests and then jump to the real instruction 11476 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11477 */ 11478 .extern MterpCheckBefore 11479 EXPORT_PC 11480 REFRESH_IBASE 11481 dla ra, artMterpAsmInstructionStart 11482 dla t9, MterpCheckBefore 11483 move a0, rSELF 11484 daddu a1, rFP, OFF_FP_SHADOWFRAME 11485 daddu ra, ra, (215 * 128) # Addr of primary handler. 11486 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11487 11488/* ------------------------------ */ 11489 .balign 128 11490.L_ALT_op_add_int_lit8: /* 0xd8 */ 11491/* File: mips64/alt_stub.S */ 11492/* 11493 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11494 * any interesting requests and then jump to the real instruction 11495 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11496 */ 11497 .extern MterpCheckBefore 11498 EXPORT_PC 11499 REFRESH_IBASE 11500 dla ra, artMterpAsmInstructionStart 11501 dla t9, MterpCheckBefore 11502 move a0, rSELF 11503 daddu a1, rFP, OFF_FP_SHADOWFRAME 11504 daddu ra, ra, (216 * 128) # Addr of primary handler. 11505 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11506 11507/* ------------------------------ */ 11508 .balign 128 11509.L_ALT_op_rsub_int_lit8: /* 0xd9 */ 11510/* File: mips64/alt_stub.S */ 11511/* 11512 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11513 * any interesting requests and then jump to the real instruction 11514 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11515 */ 11516 .extern MterpCheckBefore 11517 EXPORT_PC 11518 REFRESH_IBASE 11519 dla ra, artMterpAsmInstructionStart 11520 dla t9, MterpCheckBefore 11521 move a0, rSELF 11522 daddu a1, rFP, OFF_FP_SHADOWFRAME 11523 daddu ra, ra, (217 * 128) # Addr of primary handler. 11524 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11525 11526/* ------------------------------ */ 11527 .balign 128 11528.L_ALT_op_mul_int_lit8: /* 0xda */ 11529/* File: mips64/alt_stub.S */ 11530/* 11531 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11532 * any interesting requests and then jump to the real instruction 11533 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11534 */ 11535 .extern MterpCheckBefore 11536 EXPORT_PC 11537 REFRESH_IBASE 11538 dla ra, artMterpAsmInstructionStart 11539 dla t9, MterpCheckBefore 11540 move a0, rSELF 11541 daddu a1, rFP, OFF_FP_SHADOWFRAME 11542 daddu ra, ra, (218 * 128) # Addr of primary handler. 11543 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11544 11545/* ------------------------------ */ 11546 .balign 128 11547.L_ALT_op_div_int_lit8: /* 0xdb */ 11548/* File: mips64/alt_stub.S */ 11549/* 11550 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11551 * any interesting requests and then jump to the real instruction 11552 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11553 */ 11554 .extern MterpCheckBefore 11555 EXPORT_PC 11556 REFRESH_IBASE 11557 dla ra, artMterpAsmInstructionStart 11558 dla t9, MterpCheckBefore 11559 move a0, rSELF 11560 daddu a1, rFP, OFF_FP_SHADOWFRAME 11561 daddu ra, ra, (219 * 128) # Addr of primary handler. 11562 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11563 11564/* ------------------------------ */ 11565 .balign 128 11566.L_ALT_op_rem_int_lit8: /* 0xdc */ 11567/* File: mips64/alt_stub.S */ 11568/* 11569 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11570 * any interesting requests and then jump to the real instruction 11571 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11572 */ 11573 .extern MterpCheckBefore 11574 EXPORT_PC 11575 REFRESH_IBASE 11576 dla ra, artMterpAsmInstructionStart 11577 dla t9, MterpCheckBefore 11578 move a0, rSELF 11579 daddu a1, rFP, OFF_FP_SHADOWFRAME 11580 daddu ra, ra, (220 * 128) # Addr of primary handler. 11581 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11582 11583/* ------------------------------ */ 11584 .balign 128 11585.L_ALT_op_and_int_lit8: /* 0xdd */ 11586/* File: mips64/alt_stub.S */ 11587/* 11588 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11589 * any interesting requests and then jump to the real instruction 11590 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11591 */ 11592 .extern MterpCheckBefore 11593 EXPORT_PC 11594 REFRESH_IBASE 11595 dla ra, artMterpAsmInstructionStart 11596 dla t9, MterpCheckBefore 11597 move a0, rSELF 11598 daddu a1, rFP, OFF_FP_SHADOWFRAME 11599 daddu ra, ra, (221 * 128) # Addr of primary handler. 11600 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11601 11602/* ------------------------------ */ 11603 .balign 128 11604.L_ALT_op_or_int_lit8: /* 0xde */ 11605/* File: mips64/alt_stub.S */ 11606/* 11607 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11608 * any interesting requests and then jump to the real instruction 11609 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11610 */ 11611 .extern MterpCheckBefore 11612 EXPORT_PC 11613 REFRESH_IBASE 11614 dla ra, artMterpAsmInstructionStart 11615 dla t9, MterpCheckBefore 11616 move a0, rSELF 11617 daddu a1, rFP, OFF_FP_SHADOWFRAME 11618 daddu ra, ra, (222 * 128) # Addr of primary handler. 11619 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11620 11621/* ------------------------------ */ 11622 .balign 128 11623.L_ALT_op_xor_int_lit8: /* 0xdf */ 11624/* File: mips64/alt_stub.S */ 11625/* 11626 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11627 * any interesting requests and then jump to the real instruction 11628 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11629 */ 11630 .extern MterpCheckBefore 11631 EXPORT_PC 11632 REFRESH_IBASE 11633 dla ra, artMterpAsmInstructionStart 11634 dla t9, MterpCheckBefore 11635 move a0, rSELF 11636 daddu a1, rFP, OFF_FP_SHADOWFRAME 11637 daddu ra, ra, (223 * 128) # Addr of primary handler. 11638 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11639 11640/* ------------------------------ */ 11641 .balign 128 11642.L_ALT_op_shl_int_lit8: /* 0xe0 */ 11643/* File: mips64/alt_stub.S */ 11644/* 11645 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11646 * any interesting requests and then jump to the real instruction 11647 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11648 */ 11649 .extern MterpCheckBefore 11650 EXPORT_PC 11651 REFRESH_IBASE 11652 dla ra, artMterpAsmInstructionStart 11653 dla t9, MterpCheckBefore 11654 move a0, rSELF 11655 daddu a1, rFP, OFF_FP_SHADOWFRAME 11656 daddu ra, ra, (224 * 128) # Addr of primary handler. 11657 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11658 11659/* ------------------------------ */ 11660 .balign 128 11661.L_ALT_op_shr_int_lit8: /* 0xe1 */ 11662/* File: mips64/alt_stub.S */ 11663/* 11664 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11665 * any interesting requests and then jump to the real instruction 11666 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11667 */ 11668 .extern MterpCheckBefore 11669 EXPORT_PC 11670 REFRESH_IBASE 11671 dla ra, artMterpAsmInstructionStart 11672 dla t9, MterpCheckBefore 11673 move a0, rSELF 11674 daddu a1, rFP, OFF_FP_SHADOWFRAME 11675 daddu ra, ra, (225 * 128) # Addr of primary handler. 11676 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11677 11678/* ------------------------------ */ 11679 .balign 128 11680.L_ALT_op_ushr_int_lit8: /* 0xe2 */ 11681/* File: mips64/alt_stub.S */ 11682/* 11683 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11684 * any interesting requests and then jump to the real instruction 11685 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11686 */ 11687 .extern MterpCheckBefore 11688 EXPORT_PC 11689 REFRESH_IBASE 11690 dla ra, artMterpAsmInstructionStart 11691 dla t9, MterpCheckBefore 11692 move a0, rSELF 11693 daddu a1, rFP, OFF_FP_SHADOWFRAME 11694 daddu ra, ra, (226 * 128) # Addr of primary handler. 11695 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11696 11697/* ------------------------------ */ 11698 .balign 128 11699.L_ALT_op_iget_quick: /* 0xe3 */ 11700/* File: mips64/alt_stub.S */ 11701/* 11702 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11703 * any interesting requests and then jump to the real instruction 11704 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11705 */ 11706 .extern MterpCheckBefore 11707 EXPORT_PC 11708 REFRESH_IBASE 11709 dla ra, artMterpAsmInstructionStart 11710 dla t9, MterpCheckBefore 11711 move a0, rSELF 11712 daddu a1, rFP, OFF_FP_SHADOWFRAME 11713 daddu ra, ra, (227 * 128) # Addr of primary handler. 11714 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11715 11716/* ------------------------------ */ 11717 .balign 128 11718.L_ALT_op_iget_wide_quick: /* 0xe4 */ 11719/* File: mips64/alt_stub.S */ 11720/* 11721 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11722 * any interesting requests and then jump to the real instruction 11723 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11724 */ 11725 .extern MterpCheckBefore 11726 EXPORT_PC 11727 REFRESH_IBASE 11728 dla ra, artMterpAsmInstructionStart 11729 dla t9, MterpCheckBefore 11730 move a0, rSELF 11731 daddu a1, rFP, OFF_FP_SHADOWFRAME 11732 daddu ra, ra, (228 * 128) # Addr of primary handler. 11733 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11734 11735/* ------------------------------ */ 11736 .balign 128 11737.L_ALT_op_iget_object_quick: /* 0xe5 */ 11738/* File: mips64/alt_stub.S */ 11739/* 11740 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11741 * any interesting requests and then jump to the real instruction 11742 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11743 */ 11744 .extern MterpCheckBefore 11745 EXPORT_PC 11746 REFRESH_IBASE 11747 dla ra, artMterpAsmInstructionStart 11748 dla t9, MterpCheckBefore 11749 move a0, rSELF 11750 daddu a1, rFP, OFF_FP_SHADOWFRAME 11751 daddu ra, ra, (229 * 128) # Addr of primary handler. 11752 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11753 11754/* ------------------------------ */ 11755 .balign 128 11756.L_ALT_op_iput_quick: /* 0xe6 */ 11757/* File: mips64/alt_stub.S */ 11758/* 11759 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11760 * any interesting requests and then jump to the real instruction 11761 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11762 */ 11763 .extern MterpCheckBefore 11764 EXPORT_PC 11765 REFRESH_IBASE 11766 dla ra, artMterpAsmInstructionStart 11767 dla t9, MterpCheckBefore 11768 move a0, rSELF 11769 daddu a1, rFP, OFF_FP_SHADOWFRAME 11770 daddu ra, ra, (230 * 128) # Addr of primary handler. 11771 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11772 11773/* ------------------------------ */ 11774 .balign 128 11775.L_ALT_op_iput_wide_quick: /* 0xe7 */ 11776/* File: mips64/alt_stub.S */ 11777/* 11778 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11779 * any interesting requests and then jump to the real instruction 11780 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11781 */ 11782 .extern MterpCheckBefore 11783 EXPORT_PC 11784 REFRESH_IBASE 11785 dla ra, artMterpAsmInstructionStart 11786 dla t9, MterpCheckBefore 11787 move a0, rSELF 11788 daddu a1, rFP, OFF_FP_SHADOWFRAME 11789 daddu ra, ra, (231 * 128) # Addr of primary handler. 11790 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11791 11792/* ------------------------------ */ 11793 .balign 128 11794.L_ALT_op_iput_object_quick: /* 0xe8 */ 11795/* File: mips64/alt_stub.S */ 11796/* 11797 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11798 * any interesting requests and then jump to the real instruction 11799 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11800 */ 11801 .extern MterpCheckBefore 11802 EXPORT_PC 11803 REFRESH_IBASE 11804 dla ra, artMterpAsmInstructionStart 11805 dla t9, MterpCheckBefore 11806 move a0, rSELF 11807 daddu a1, rFP, OFF_FP_SHADOWFRAME 11808 daddu ra, ra, (232 * 128) # Addr of primary handler. 11809 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11810 11811/* ------------------------------ */ 11812 .balign 128 11813.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ 11814/* File: mips64/alt_stub.S */ 11815/* 11816 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11817 * any interesting requests and then jump to the real instruction 11818 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11819 */ 11820 .extern MterpCheckBefore 11821 EXPORT_PC 11822 REFRESH_IBASE 11823 dla ra, artMterpAsmInstructionStart 11824 dla t9, MterpCheckBefore 11825 move a0, rSELF 11826 daddu a1, rFP, OFF_FP_SHADOWFRAME 11827 daddu ra, ra, (233 * 128) # Addr of primary handler. 11828 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11829 11830/* ------------------------------ */ 11831 .balign 128 11832.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ 11833/* File: mips64/alt_stub.S */ 11834/* 11835 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11836 * any interesting requests and then jump to the real instruction 11837 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11838 */ 11839 .extern MterpCheckBefore 11840 EXPORT_PC 11841 REFRESH_IBASE 11842 dla ra, artMterpAsmInstructionStart 11843 dla t9, MterpCheckBefore 11844 move a0, rSELF 11845 daddu a1, rFP, OFF_FP_SHADOWFRAME 11846 daddu ra, ra, (234 * 128) # Addr of primary handler. 11847 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11848 11849/* ------------------------------ */ 11850 .balign 128 11851.L_ALT_op_iput_boolean_quick: /* 0xeb */ 11852/* File: mips64/alt_stub.S */ 11853/* 11854 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11855 * any interesting requests and then jump to the real instruction 11856 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11857 */ 11858 .extern MterpCheckBefore 11859 EXPORT_PC 11860 REFRESH_IBASE 11861 dla ra, artMterpAsmInstructionStart 11862 dla t9, MterpCheckBefore 11863 move a0, rSELF 11864 daddu a1, rFP, OFF_FP_SHADOWFRAME 11865 daddu ra, ra, (235 * 128) # Addr of primary handler. 11866 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11867 11868/* ------------------------------ */ 11869 .balign 128 11870.L_ALT_op_iput_byte_quick: /* 0xec */ 11871/* File: mips64/alt_stub.S */ 11872/* 11873 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11874 * any interesting requests and then jump to the real instruction 11875 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11876 */ 11877 .extern MterpCheckBefore 11878 EXPORT_PC 11879 REFRESH_IBASE 11880 dla ra, artMterpAsmInstructionStart 11881 dla t9, MterpCheckBefore 11882 move a0, rSELF 11883 daddu a1, rFP, OFF_FP_SHADOWFRAME 11884 daddu ra, ra, (236 * 128) # Addr of primary handler. 11885 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11886 11887/* ------------------------------ */ 11888 .balign 128 11889.L_ALT_op_iput_char_quick: /* 0xed */ 11890/* File: mips64/alt_stub.S */ 11891/* 11892 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11893 * any interesting requests and then jump to the real instruction 11894 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11895 */ 11896 .extern MterpCheckBefore 11897 EXPORT_PC 11898 REFRESH_IBASE 11899 dla ra, artMterpAsmInstructionStart 11900 dla t9, MterpCheckBefore 11901 move a0, rSELF 11902 daddu a1, rFP, OFF_FP_SHADOWFRAME 11903 daddu ra, ra, (237 * 128) # Addr of primary handler. 11904 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11905 11906/* ------------------------------ */ 11907 .balign 128 11908.L_ALT_op_iput_short_quick: /* 0xee */ 11909/* File: mips64/alt_stub.S */ 11910/* 11911 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11912 * any interesting requests and then jump to the real instruction 11913 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11914 */ 11915 .extern MterpCheckBefore 11916 EXPORT_PC 11917 REFRESH_IBASE 11918 dla ra, artMterpAsmInstructionStart 11919 dla t9, MterpCheckBefore 11920 move a0, rSELF 11921 daddu a1, rFP, OFF_FP_SHADOWFRAME 11922 daddu ra, ra, (238 * 128) # Addr of primary handler. 11923 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11924 11925/* ------------------------------ */ 11926 .balign 128 11927.L_ALT_op_iget_boolean_quick: /* 0xef */ 11928/* File: mips64/alt_stub.S */ 11929/* 11930 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11931 * any interesting requests and then jump to the real instruction 11932 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11933 */ 11934 .extern MterpCheckBefore 11935 EXPORT_PC 11936 REFRESH_IBASE 11937 dla ra, artMterpAsmInstructionStart 11938 dla t9, MterpCheckBefore 11939 move a0, rSELF 11940 daddu a1, rFP, OFF_FP_SHADOWFRAME 11941 daddu ra, ra, (239 * 128) # Addr of primary handler. 11942 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11943 11944/* ------------------------------ */ 11945 .balign 128 11946.L_ALT_op_iget_byte_quick: /* 0xf0 */ 11947/* File: mips64/alt_stub.S */ 11948/* 11949 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11950 * any interesting requests and then jump to the real instruction 11951 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11952 */ 11953 .extern MterpCheckBefore 11954 EXPORT_PC 11955 REFRESH_IBASE 11956 dla ra, artMterpAsmInstructionStart 11957 dla t9, MterpCheckBefore 11958 move a0, rSELF 11959 daddu a1, rFP, OFF_FP_SHADOWFRAME 11960 daddu ra, ra, (240 * 128) # Addr of primary handler. 11961 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11962 11963/* ------------------------------ */ 11964 .balign 128 11965.L_ALT_op_iget_char_quick: /* 0xf1 */ 11966/* File: mips64/alt_stub.S */ 11967/* 11968 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11969 * any interesting requests and then jump to the real instruction 11970 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11971 */ 11972 .extern MterpCheckBefore 11973 EXPORT_PC 11974 REFRESH_IBASE 11975 dla ra, artMterpAsmInstructionStart 11976 dla t9, MterpCheckBefore 11977 move a0, rSELF 11978 daddu a1, rFP, OFF_FP_SHADOWFRAME 11979 daddu ra, ra, (241 * 128) # Addr of primary handler. 11980 jalr zero, t9 # (self, shadow_frame) Note: tail call. 11981 11982/* ------------------------------ */ 11983 .balign 128 11984.L_ALT_op_iget_short_quick: /* 0xf2 */ 11985/* File: mips64/alt_stub.S */ 11986/* 11987 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11988 * any interesting requests and then jump to the real instruction 11989 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11990 */ 11991 .extern MterpCheckBefore 11992 EXPORT_PC 11993 REFRESH_IBASE 11994 dla ra, artMterpAsmInstructionStart 11995 dla t9, MterpCheckBefore 11996 move a0, rSELF 11997 daddu a1, rFP, OFF_FP_SHADOWFRAME 11998 daddu ra, ra, (242 * 128) # Addr of primary handler. 11999 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12000 12001/* ------------------------------ */ 12002 .balign 128 12003.L_ALT_op_invoke_lambda: /* 0xf3 */ 12004/* File: mips64/alt_stub.S */ 12005/* 12006 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12007 * any interesting requests and then jump to the real instruction 12008 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12009 */ 12010 .extern MterpCheckBefore 12011 EXPORT_PC 12012 REFRESH_IBASE 12013 dla ra, artMterpAsmInstructionStart 12014 dla t9, MterpCheckBefore 12015 move a0, rSELF 12016 daddu a1, rFP, OFF_FP_SHADOWFRAME 12017 daddu ra, ra, (243 * 128) # Addr of primary handler. 12018 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12019 12020/* ------------------------------ */ 12021 .balign 128 12022.L_ALT_op_unused_f4: /* 0xf4 */ 12023/* File: mips64/alt_stub.S */ 12024/* 12025 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12026 * any interesting requests and then jump to the real instruction 12027 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12028 */ 12029 .extern MterpCheckBefore 12030 EXPORT_PC 12031 REFRESH_IBASE 12032 dla ra, artMterpAsmInstructionStart 12033 dla t9, MterpCheckBefore 12034 move a0, rSELF 12035 daddu a1, rFP, OFF_FP_SHADOWFRAME 12036 daddu ra, ra, (244 * 128) # Addr of primary handler. 12037 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12038 12039/* ------------------------------ */ 12040 .balign 128 12041.L_ALT_op_capture_variable: /* 0xf5 */ 12042/* File: mips64/alt_stub.S */ 12043/* 12044 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12045 * any interesting requests and then jump to the real instruction 12046 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12047 */ 12048 .extern MterpCheckBefore 12049 EXPORT_PC 12050 REFRESH_IBASE 12051 dla ra, artMterpAsmInstructionStart 12052 dla t9, MterpCheckBefore 12053 move a0, rSELF 12054 daddu a1, rFP, OFF_FP_SHADOWFRAME 12055 daddu ra, ra, (245 * 128) # Addr of primary handler. 12056 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12057 12058/* ------------------------------ */ 12059 .balign 128 12060.L_ALT_op_create_lambda: /* 0xf6 */ 12061/* File: mips64/alt_stub.S */ 12062/* 12063 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12064 * any interesting requests and then jump to the real instruction 12065 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12066 */ 12067 .extern MterpCheckBefore 12068 EXPORT_PC 12069 REFRESH_IBASE 12070 dla ra, artMterpAsmInstructionStart 12071 dla t9, MterpCheckBefore 12072 move a0, rSELF 12073 daddu a1, rFP, OFF_FP_SHADOWFRAME 12074 daddu ra, ra, (246 * 128) # Addr of primary handler. 12075 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12076 12077/* ------------------------------ */ 12078 .balign 128 12079.L_ALT_op_liberate_variable: /* 0xf7 */ 12080/* File: mips64/alt_stub.S */ 12081/* 12082 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12083 * any interesting requests and then jump to the real instruction 12084 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12085 */ 12086 .extern MterpCheckBefore 12087 EXPORT_PC 12088 REFRESH_IBASE 12089 dla ra, artMterpAsmInstructionStart 12090 dla t9, MterpCheckBefore 12091 move a0, rSELF 12092 daddu a1, rFP, OFF_FP_SHADOWFRAME 12093 daddu ra, ra, (247 * 128) # Addr of primary handler. 12094 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12095 12096/* ------------------------------ */ 12097 .balign 128 12098.L_ALT_op_box_lambda: /* 0xf8 */ 12099/* File: mips64/alt_stub.S */ 12100/* 12101 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12102 * any interesting requests and then jump to the real instruction 12103 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12104 */ 12105 .extern MterpCheckBefore 12106 EXPORT_PC 12107 REFRESH_IBASE 12108 dla ra, artMterpAsmInstructionStart 12109 dla t9, MterpCheckBefore 12110 move a0, rSELF 12111 daddu a1, rFP, OFF_FP_SHADOWFRAME 12112 daddu ra, ra, (248 * 128) # Addr of primary handler. 12113 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12114 12115/* ------------------------------ */ 12116 .balign 128 12117.L_ALT_op_unbox_lambda: /* 0xf9 */ 12118/* File: mips64/alt_stub.S */ 12119/* 12120 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12121 * any interesting requests and then jump to the real instruction 12122 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12123 */ 12124 .extern MterpCheckBefore 12125 EXPORT_PC 12126 REFRESH_IBASE 12127 dla ra, artMterpAsmInstructionStart 12128 dla t9, MterpCheckBefore 12129 move a0, rSELF 12130 daddu a1, rFP, OFF_FP_SHADOWFRAME 12131 daddu ra, ra, (249 * 128) # Addr of primary handler. 12132 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12133 12134/* ------------------------------ */ 12135 .balign 128 12136.L_ALT_op_unused_fa: /* 0xfa */ 12137/* File: mips64/alt_stub.S */ 12138/* 12139 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12140 * any interesting requests and then jump to the real instruction 12141 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12142 */ 12143 .extern MterpCheckBefore 12144 EXPORT_PC 12145 REFRESH_IBASE 12146 dla ra, artMterpAsmInstructionStart 12147 dla t9, MterpCheckBefore 12148 move a0, rSELF 12149 daddu a1, rFP, OFF_FP_SHADOWFRAME 12150 daddu ra, ra, (250 * 128) # Addr of primary handler. 12151 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12152 12153/* ------------------------------ */ 12154 .balign 128 12155.L_ALT_op_unused_fb: /* 0xfb */ 12156/* File: mips64/alt_stub.S */ 12157/* 12158 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12159 * any interesting requests and then jump to the real instruction 12160 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12161 */ 12162 .extern MterpCheckBefore 12163 EXPORT_PC 12164 REFRESH_IBASE 12165 dla ra, artMterpAsmInstructionStart 12166 dla t9, MterpCheckBefore 12167 move a0, rSELF 12168 daddu a1, rFP, OFF_FP_SHADOWFRAME 12169 daddu ra, ra, (251 * 128) # Addr of primary handler. 12170 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12171 12172/* ------------------------------ */ 12173 .balign 128 12174.L_ALT_op_unused_fc: /* 0xfc */ 12175/* File: mips64/alt_stub.S */ 12176/* 12177 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12178 * any interesting requests and then jump to the real instruction 12179 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12180 */ 12181 .extern MterpCheckBefore 12182 EXPORT_PC 12183 REFRESH_IBASE 12184 dla ra, artMterpAsmInstructionStart 12185 dla t9, MterpCheckBefore 12186 move a0, rSELF 12187 daddu a1, rFP, OFF_FP_SHADOWFRAME 12188 daddu ra, ra, (252 * 128) # Addr of primary handler. 12189 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12190 12191/* ------------------------------ */ 12192 .balign 128 12193.L_ALT_op_unused_fd: /* 0xfd */ 12194/* File: mips64/alt_stub.S */ 12195/* 12196 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12197 * any interesting requests and then jump to the real instruction 12198 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12199 */ 12200 .extern MterpCheckBefore 12201 EXPORT_PC 12202 REFRESH_IBASE 12203 dla ra, artMterpAsmInstructionStart 12204 dla t9, MterpCheckBefore 12205 move a0, rSELF 12206 daddu a1, rFP, OFF_FP_SHADOWFRAME 12207 daddu ra, ra, (253 * 128) # Addr of primary handler. 12208 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12209 12210/* ------------------------------ */ 12211 .balign 128 12212.L_ALT_op_unused_fe: /* 0xfe */ 12213/* File: mips64/alt_stub.S */ 12214/* 12215 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12216 * any interesting requests and then jump to the real instruction 12217 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12218 */ 12219 .extern MterpCheckBefore 12220 EXPORT_PC 12221 REFRESH_IBASE 12222 dla ra, artMterpAsmInstructionStart 12223 dla t9, MterpCheckBefore 12224 move a0, rSELF 12225 daddu a1, rFP, OFF_FP_SHADOWFRAME 12226 daddu ra, ra, (254 * 128) # Addr of primary handler. 12227 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12228 12229/* ------------------------------ */ 12230 .balign 128 12231.L_ALT_op_unused_ff: /* 0xff */ 12232/* File: mips64/alt_stub.S */ 12233/* 12234 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12235 * any interesting requests and then jump to the real instruction 12236 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12237 */ 12238 .extern MterpCheckBefore 12239 EXPORT_PC 12240 REFRESH_IBASE 12241 dla ra, artMterpAsmInstructionStart 12242 dla t9, MterpCheckBefore 12243 move a0, rSELF 12244 daddu a1, rFP, OFF_FP_SHADOWFRAME 12245 daddu ra, ra, (255 * 128) # Addr of primary handler. 12246 jalr zero, t9 # (self, shadow_frame) Note: tail call. 12247 12248 .balign 128 12249 .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart 12250 .global artMterpAsmAltInstructionEnd 12251artMterpAsmAltInstructionEnd: 12252/* File: mips64/footer.S */ 12253/* 12254 * We've detected a condition that will result in an exception, but the exception 12255 * has not yet been thrown. Just bail out to the reference interpreter to deal with it. 12256 * TUNING: for consistency, we may want to just go ahead and handle these here. 12257 */ 12258 12259 .extern MterpLogDivideByZeroException 12260common_errDivideByZero: 12261 EXPORT_PC 12262#if MTERP_LOGGING 12263 move a0, rSELF 12264 daddu a1, rFP, OFF_FP_SHADOWFRAME 12265 jal MterpLogDivideByZeroException 12266#endif 12267 b MterpCommonFallback 12268 12269 .extern MterpLogArrayIndexException 12270common_errArrayIndex: 12271 EXPORT_PC 12272#if MTERP_LOGGING 12273 move a0, rSELF 12274 daddu a1, rFP, OFF_FP_SHADOWFRAME 12275 jal MterpLogArrayIndexException 12276#endif 12277 b MterpCommonFallback 12278 12279 .extern MterpLogNullObjectException 12280common_errNullObject: 12281 EXPORT_PC 12282#if MTERP_LOGGING 12283 move a0, rSELF 12284 daddu a1, rFP, OFF_FP_SHADOWFRAME 12285 jal MterpLogNullObjectException 12286#endif 12287 b MterpCommonFallback 12288 12289/* 12290 * If we're here, something is out of the ordinary. If there is a pending 12291 * exception, handle it. Otherwise, roll back and retry with the reference 12292 * interpreter. 12293 */ 12294MterpPossibleException: 12295 ld a0, THREAD_EXCEPTION_OFFSET(rSELF) 12296 beqzc a0, MterpFallback # If not, fall back to reference interpreter. 12297 /* intentional fallthrough - handle pending exception. */ 12298/* 12299 * On return from a runtime helper routine, we've found a pending exception. 12300 * Can we handle it here - or need to bail out to caller? 12301 * 12302 */ 12303 .extern MterpHandleException 12304 .extern MterpShouldSwitchInterpreters 12305MterpException: 12306 move a0, rSELF 12307 daddu a1, rFP, OFF_FP_SHADOWFRAME 12308 jal MterpHandleException # (self, shadow_frame) 12309 beqzc v0, MterpExceptionReturn # no local catch, back to caller. 12310 ld a0, OFF_FP_CODE_ITEM(rFP) 12311 lwu a1, OFF_FP_DEX_PC(rFP) 12312 REFRESH_IBASE 12313 daddu rPC, a0, CODEITEM_INSNS_OFFSET 12314 dlsa rPC, a1, rPC, 1 # generate new dex_pc_ptr 12315 /* Do we need to switch interpreters? */ 12316 jal MterpShouldSwitchInterpreters 12317 bnezc v0, MterpFallback 12318 /* resume execution at catch block */ 12319 EXPORT_PC 12320 FETCH_INST 12321 GET_INST_OPCODE v0 12322 GOTO_OPCODE v0 12323 /* NOTE: no fallthrough */ 12324 12325/* 12326 * Check for suspend check request. Assumes rINST already loaded, rPC advanced and 12327 * still needs to get the opcode and branch to it, and flags are in ra. 12328 */ 12329 .extern MterpSuspendCheck 12330MterpCheckSuspendAndContinue: 12331 REFRESH_IBASE 12332 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 12333 bnez ra, check1 12334 GET_INST_OPCODE v0 # extract opcode from rINST 12335 GOTO_OPCODE v0 # jump to next instruction 12336check1: 12337 EXPORT_PC 12338 move a0, rSELF 12339 jal MterpSuspendCheck # (self) 12340 bnezc v0, MterpFallback # Something in the environment changed, switch interpreters 12341 GET_INST_OPCODE v0 # extract opcode from rINST 12342 GOTO_OPCODE v0 # jump to next instruction 12343 12344/* 12345 * On-stack replacement has happened, and now we've returned from the compiled method. 12346 */ 12347MterpOnStackReplacement: 12348#if MTERP_LOGGING 12349 move a0, rSELF 12350 daddu a1, rFP, OFF_FP_SHADOWFRAME 12351 move a2, rINST # rINST contains offset 12352 jal MterpLogOSR 12353#endif 12354 li v0, 1 # Signal normal return 12355 b MterpDone 12356 12357/* 12358 * Bail out to reference interpreter. 12359 */ 12360 .extern MterpLogFallback 12361MterpFallback: 12362 EXPORT_PC 12363#if MTERP_LOGGING 12364 move a0, rSELF 12365 daddu a1, rFP, OFF_FP_SHADOWFRAME 12366 jal MterpLogFallback 12367#endif 12368MterpCommonFallback: 12369 li v0, 0 # signal retry with reference interpreter. 12370 b MterpDone 12371 12372/* 12373 * We pushed some registers on the stack in ExecuteMterpImpl, then saved 12374 * SP and RA. Here we restore SP, restore the registers, and then restore 12375 * RA to PC. 12376 * 12377 * On entry: 12378 * uint32_t* rFP (should still be live, pointer to base of vregs) 12379 */ 12380MterpExceptionReturn: 12381 li v0, 1 # signal return to caller. 12382 b MterpDone 12383/* 12384 * Returned value is expected in a0 and if it's not 64-bit, the 32 most 12385 * significant bits of a0 must be 0. 12386 */ 12387MterpReturn: 12388 ld a2, OFF_FP_RESULT_REGISTER(rFP) 12389 lw ra, THREAD_FLAGS_OFFSET(rSELF) 12390 sd a0, 0(a2) 12391 move a0, rSELF 12392 and ra, ra, (THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST) 12393 beqzc ra, check2 12394 jal MterpSuspendCheck # (self) 12395check2: 12396 li v0, 1 # signal return to caller. 12397MterpDone: 12398 ld s5, STACK_OFFSET_S5(sp) 12399 .cfi_restore 21 12400 ld s4, STACK_OFFSET_S4(sp) 12401 .cfi_restore 20 12402 ld s3, STACK_OFFSET_S3(sp) 12403 .cfi_restore 19 12404 ld s2, STACK_OFFSET_S2(sp) 12405 .cfi_restore 18 12406 ld s1, STACK_OFFSET_S1(sp) 12407 .cfi_restore 17 12408 ld s0, STACK_OFFSET_S0(sp) 12409 .cfi_restore 16 12410 12411 ld ra, STACK_OFFSET_RA(sp) 12412 .cfi_restore 31 12413 12414 ld t8, STACK_OFFSET_GP(sp) 12415 .cpreturn 12416 .cfi_restore 28 12417 12418 .set noreorder 12419 jr ra 12420 daddu sp, sp, STACK_SIZE 12421 .cfi_adjust_cfa_offset -STACK_SIZE 12422 12423 .cfi_endproc 12424 .size ExecuteMterpImpl, .-ExecuteMterpImpl 12425 12426