1/* 2 * Copyright (c) 1997 Mark Brinicombe 3 * Copyright (c) 2010 Android Open Source Project. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Mark Brinicombe 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34#include <private/bionic_asm.h> 35 36// According to the ARM AAPCS document, we only need to save 37// the following registers: 38// 39// Core r4-r11, sp, lr 40// AAPCS 5.1.1: 41// A subroutine must preserve the contents of the registers r4-r8, r10, r11 42// and SP (and r9 in PCS variants that designate r9 as v6). 43// 44// VFP d8-d15 45// AAPCS 5.1.2.1: 46// Registers s16-s31 (d8-d15, q4-q7) must be preserved across subroutine 47// calls; registers s0-s15 (d0-d7, q0-q3) do not need to be preserved 48// (and can be used for passing arguments or returning results in standard 49// procedure-call variants). Registers d16-d31 (q8-q15), if present, do 50// not need to be preserved. 51// 52// FPSCR saved because glibc does. 53 54// The internal structure of a jmp_buf is totally private. 55// Current layout (changes from release to release): 56// 57// word name description 58// 0 sigflag/cookie setjmp cookie in top 31 bits, signal mask flag in low bit 59// 1 sigmask signal mask (not used with _setjmp / _longjmp) 60// 2 float_base base of float registers (d8 to d15) 61// 18 float_state floating-point status and control register 62// 19 core_base base of core registers (r4-r11, r13-r14) 63// 29 checksum checksum of all of the core registers, to give better error messages. 64// 30 reserved reserved entries (room to grow) 65// 64 66// 67// NOTE: float_base must be at an even word index, since the 68// FP registers will be loaded/stored with instructions 69// that expect 8-byte alignment. 70 71#define _JB_SIGFLAG 0 72#define _JB_SIGMASK (_JB_SIGFLAG+1) 73#define _JB_FLOAT_BASE (_JB_SIGMASK+1) 74#define _JB_FLOAT_STATE (_JB_FLOAT_BASE + (15-8+1)*2) 75#define _JB_CORE_BASE (_JB_FLOAT_STATE+1) 76#define _JB_CHECKSUM (_JB_CORE_BASE+10) 77 78ENTRY(setjmp) 79 mov r1, #1 80 b sigsetjmp 81END(setjmp) 82 83ENTRY(_setjmp) 84 mov r1, #0 85 b sigsetjmp 86END(_setjmp) 87 88#define MANGLE_REGISTERS 1 89#define USE_CHECKSUM 1 90 91.macro m_mangle_registers reg 92#if MANGLE_REGISTERS 93 eor r4, r4, \reg 94 eor r5, r5, \reg 95 eor r6, r6, \reg 96 eor r7, r7, \reg 97 eor r8, r8, \reg 98 eor r9, r9, \reg 99 eor r10, r10, \reg 100 eor r11, r11, \reg 101 eor r13, r13, \reg 102 eor r14, r14, \reg 103#endif 104.endm 105 106.macro m_unmangle_registers reg 107 m_mangle_registers \reg 108.endm 109 110.macro m_calculate_checksum dst, src, scratch 111 mov \dst, #0 112 .irp i,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28 113 ldr \scratch, [\src, #(\i * 4)] 114 eor \dst, \dst, \scratch 115 .endr 116.endm 117 118// int sigsetjmp(sigjmp_buf env, int save_signal_mask); 119ENTRY(sigsetjmp) 120 stmfd sp!, {r0, lr} 121 .cfi_def_cfa_offset 8 122 .cfi_rel_offset r0, 0 123 .cfi_rel_offset lr, 4 124 125 mov r0, r1 126 bl __bionic_setjmp_cookie_get 127 mov r1, r0 128 129 ldmfd sp, {r0} 130 131 // Save the setjmp cookie for later. 132 bic r2, r1, #1 133 stmfd sp!, {r2} 134 .cfi_adjust_cfa_offset 4 135 136 // Record the setjmp cookie and whether or not we're saving the signal mask. 137 str r1, [r0, #(_JB_SIGFLAG * 4)] 138 139 // Do we need to save the signal mask? 140 tst r1, #1 141 beq 1f 142 143 // Align the stack. 144 sub sp, #4 145 .cfi_adjust_cfa_offset 4 146 147 // Save the current signal mask. 148 add r2, r0, #(_JB_SIGMASK * 4) 149 mov r0, #2 // SIG_SETMASK 150 mov r1, #0 151 bl sigprocmask 152 153 // Unalign the stack. 154 add sp, #4 155 .cfi_adjust_cfa_offset -4 156 1571: 158 ldmfd sp!, {r2} 159 .cfi_adjust_cfa_offset -4 160 ldmfd sp!, {r0, lr} 161 .cfi_adjust_cfa_offset -8 162 .cfi_restore r0 163 .cfi_restore lr 164 165 // Save core registers. 166 add r1, r0, #(_JB_CORE_BASE * 4) 167 m_mangle_registers r2 168 169 // ARM deprecates using sp in the register list for stmia. 170 stmia r1, {r4-r11, lr} 171 str sp, [r1, #(9 * 4)] 172 m_unmangle_registers r2 173 174 // Save floating-point registers. 175 add r1, r0, #(_JB_FLOAT_BASE * 4) 176 vstmia r1, {d8-d15} 177 178 // Save floating-point state. 179 fmrx r1, fpscr 180 str r1, [r0, #(_JB_FLOAT_STATE * 4)] 181 182#if USE_CHECKSUM 183 // Calculate the checksum. 184 m_calculate_checksum r12, r0, r2 185 str r12, [r0, #(_JB_CHECKSUM * 4)] 186#endif 187 188 mov r0, #0 189 bx lr 190END(sigsetjmp) 191 192// void siglongjmp(sigjmp_buf env, int value); 193ENTRY(siglongjmp) 194 stmfd sp!, {r0, r1, lr} 195 .cfi_def_cfa_offset 12 196 .cfi_rel_offset r0, 0 197 .cfi_rel_offset r1, 4 198 .cfi_rel_offset lr, 8 199 200#if USE_CHECKSUM 201 // Check the checksum before doing anything. 202 m_calculate_checksum r12, r0, r3 203 ldr r2, [r0, #(_JB_CHECKSUM * 4)] 204 205 teq r2, r12 206 bne __bionic_setjmp_checksum_mismatch 207#endif 208 209 // Fetch the signal flag. 210 ldr r1, [r0, #(_JB_SIGFLAG * 4)] 211 212 // Do we need to restore the signal mask? 213 ands r1, r1, #1 214 beq 1f 215 216 // Restore the signal mask. 217 ldr r0, [r0, #(_JB_SIGMASK * 4)] 218 bl sigsetmask 219 2201: 221 ldmfd sp!, {r0, r1, lr} 222 .cfi_adjust_cfa_offset -12 223 .cfi_restore r0 224 .cfi_restore r1 225 .cfi_restore lr 226 227 // Restore floating-point registers. 228 add r2, r0, #(_JB_FLOAT_BASE * 4) 229 vldmia r2, {d8-d15} 230 231 // Restore floating-point state. 232 ldr r2, [r0, #(_JB_FLOAT_STATE * 4)] 233 fmxr fpscr, r2 234 235 // Load the cookie. 236 ldr r3, [r0, #(_JB_SIGFLAG * 4)] 237 bic r3, r3, #1 238 239 // Restore core registers. 240 add r2, r0, #(_JB_CORE_BASE * 4) 241 242 // ARM deprecates using sp in the register list for ldmia. 243 ldmia r2, {r4-r11, lr} 244 ldr sp, [r2, #(9 * 4)] 245 m_unmangle_registers r3 246 247 // Save the return value/address and check the setjmp cookie. 248 stmfd sp!, {r1, lr} 249 .cfi_adjust_cfa_offset 8 250 .cfi_rel_offset lr, 4 251 mov r0, r3 252 bl __bionic_setjmp_cookie_check 253 254 // Restore return value/address. 255 ldmfd sp!, {r0, lr} 256 .cfi_adjust_cfa_offset -8 257 .cfi_restore lr 258 259 teq r0, #0 260 moveq r0, #1 261 bx lr 262END(siglongjmp) 263 264ALIAS_SYMBOL(longjmp, siglongjmp) 265ALIAS_SYMBOL(_longjmp, siglongjmp) 266