1 /*
2 * Copyright (c) 2014-2015, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU Lesser General Public License,
6 * version 2.1, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT ANY
9 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
10 * FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for
11 * more details.
12 */
13 #ifndef __NDCTL_H__
14 #define __NDCTL_H__
15
16 #include <linux/types.h>
17
18 struct nd_cmd_smart {
19 __u32 status;
20 __u8 data[128];
21 } __packed;
22
23 struct nd_cmd_smart_threshold {
24 __u32 status;
25 __u8 data[8];
26 } __packed;
27
28 struct nd_cmd_dimm_flags {
29 __u32 status;
30 __u32 flags;
31 } __packed;
32
33 struct nd_cmd_get_config_size {
34 __u32 status;
35 __u32 config_size;
36 __u32 max_xfer;
37 } __packed;
38
39 struct nd_cmd_get_config_data_hdr {
40 __u32 in_offset;
41 __u32 in_length;
42 __u32 status;
43 __u8 out_buf[0];
44 } __packed;
45
46 struct nd_cmd_set_config_hdr {
47 __u32 in_offset;
48 __u32 in_length;
49 __u8 in_buf[0];
50 } __packed;
51
52 struct nd_cmd_vendor_hdr {
53 __u32 opcode;
54 __u32 in_length;
55 __u8 in_buf[0];
56 } __packed;
57
58 struct nd_cmd_vendor_tail {
59 __u32 status;
60 __u32 out_length;
61 __u8 out_buf[0];
62 } __packed;
63
64 struct nd_cmd_ars_cap {
65 __u64 address;
66 __u64 length;
67 __u32 status;
68 __u32 max_ars_out;
69 } __packed;
70
71 struct nd_cmd_ars_start {
72 __u64 address;
73 __u64 length;
74 __u16 type;
75 __u8 reserved[6];
76 __u32 status;
77 } __packed;
78
79 struct nd_cmd_ars_status {
80 __u32 status;
81 __u32 out_length;
82 __u64 address;
83 __u64 length;
84 __u16 type;
85 __u32 num_records;
86 struct nd_ars_record {
87 __u32 handle;
88 __u32 flags;
89 __u64 err_address;
90 __u64 length;
91 } __packed records[0];
92 } __packed;
93
94 enum {
95 ND_CMD_IMPLEMENTED = 0,
96
97 /* bus commands */
98 ND_CMD_ARS_CAP = 1,
99 ND_CMD_ARS_START = 2,
100 ND_CMD_ARS_STATUS = 3,
101
102 /* per-dimm commands */
103 ND_CMD_SMART = 1,
104 ND_CMD_SMART_THRESHOLD = 2,
105 ND_CMD_DIMM_FLAGS = 3,
106 ND_CMD_GET_CONFIG_SIZE = 4,
107 ND_CMD_GET_CONFIG_DATA = 5,
108 ND_CMD_SET_CONFIG_DATA = 6,
109 ND_CMD_VENDOR_EFFECT_LOG_SIZE = 7,
110 ND_CMD_VENDOR_EFFECT_LOG = 8,
111 ND_CMD_VENDOR = 9,
112 };
113
114 enum {
115 ND_ARS_VOLATILE = 1,
116 ND_ARS_PERSISTENT = 2,
117 };
118
nvdimm_bus_cmd_name(unsigned cmd)119 static inline const char *nvdimm_bus_cmd_name(unsigned cmd)
120 {
121 static const char * const names[] = {
122 [ND_CMD_ARS_CAP] = "ars_cap",
123 [ND_CMD_ARS_START] = "ars_start",
124 [ND_CMD_ARS_STATUS] = "ars_status",
125 };
126
127 if (cmd < ARRAY_SIZE(names) && names[cmd])
128 return names[cmd];
129 return "unknown";
130 }
131
nvdimm_cmd_name(unsigned cmd)132 static inline const char *nvdimm_cmd_name(unsigned cmd)
133 {
134 static const char * const names[] = {
135 [ND_CMD_SMART] = "smart",
136 [ND_CMD_SMART_THRESHOLD] = "smart_thresh",
137 [ND_CMD_DIMM_FLAGS] = "flags",
138 [ND_CMD_GET_CONFIG_SIZE] = "get_size",
139 [ND_CMD_GET_CONFIG_DATA] = "get_data",
140 [ND_CMD_SET_CONFIG_DATA] = "set_data",
141 [ND_CMD_VENDOR_EFFECT_LOG_SIZE] = "effect_size",
142 [ND_CMD_VENDOR_EFFECT_LOG] = "effect_log",
143 [ND_CMD_VENDOR] = "vendor",
144 };
145
146 if (cmd < ARRAY_SIZE(names) && names[cmd])
147 return names[cmd];
148 return "unknown";
149 }
150
151 #define ND_IOCTL 'N'
152
153 #define ND_IOCTL_SMART _IOWR(ND_IOCTL, ND_CMD_SMART,\
154 struct nd_cmd_smart)
155
156 #define ND_IOCTL_SMART_THRESHOLD _IOWR(ND_IOCTL, ND_CMD_SMART_THRESHOLD,\
157 struct nd_cmd_smart_threshold)
158
159 #define ND_IOCTL_DIMM_FLAGS _IOWR(ND_IOCTL, ND_CMD_DIMM_FLAGS,\
160 struct nd_cmd_dimm_flags)
161
162 #define ND_IOCTL_GET_CONFIG_SIZE _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_SIZE,\
163 struct nd_cmd_get_config_size)
164
165 #define ND_IOCTL_GET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_DATA,\
166 struct nd_cmd_get_config_data_hdr)
167
168 #define ND_IOCTL_SET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_SET_CONFIG_DATA,\
169 struct nd_cmd_set_config_hdr)
170
171 #define ND_IOCTL_VENDOR _IOWR(ND_IOCTL, ND_CMD_VENDOR,\
172 struct nd_cmd_vendor_hdr)
173
174 #define ND_IOCTL_ARS_CAP _IOWR(ND_IOCTL, ND_CMD_ARS_CAP,\
175 struct nd_cmd_ars_cap)
176
177 #define ND_IOCTL_ARS_START _IOWR(ND_IOCTL, ND_CMD_ARS_START,\
178 struct nd_cmd_ars_start)
179
180 #define ND_IOCTL_ARS_STATUS _IOWR(ND_IOCTL, ND_CMD_ARS_STATUS,\
181 struct nd_cmd_ars_status)
182
183 #define ND_DEVICE_DIMM 1 /* nd_dimm: container for "config data" */
184 #define ND_DEVICE_REGION_PMEM 2 /* nd_region: (parent of PMEM namespaces) */
185 #define ND_DEVICE_REGION_BLK 3 /* nd_region: (parent of BLK namespaces) */
186 #define ND_DEVICE_NAMESPACE_IO 4 /* legacy persistent memory */
187 #define ND_DEVICE_NAMESPACE_PMEM 5 /* PMEM namespace (may alias with BLK) */
188 #define ND_DEVICE_NAMESPACE_BLK 6 /* BLK namespace (may alias with PMEM) */
189
190 enum nd_driver_flags {
191 ND_DRIVER_DIMM = 1 << ND_DEVICE_DIMM,
192 ND_DRIVER_REGION_PMEM = 1 << ND_DEVICE_REGION_PMEM,
193 ND_DRIVER_REGION_BLK = 1 << ND_DEVICE_REGION_BLK,
194 ND_DRIVER_NAMESPACE_IO = 1 << ND_DEVICE_NAMESPACE_IO,
195 ND_DRIVER_NAMESPACE_PMEM = 1 << ND_DEVICE_NAMESPACE_PMEM,
196 ND_DRIVER_NAMESPACE_BLK = 1 << ND_DEVICE_NAMESPACE_BLK,
197 };
198
199 enum {
200 ND_MIN_NAMESPACE_SIZE = 0x00400000,
201 };
202
203 enum ars_masks {
204 ARS_STATUS_MASK = 0x0000FFFF,
205 ARS_EXT_STATUS_SHIFT = 16,
206 };
207 #endif /* __NDCTL_H__ */
208