1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 // When allowed by the instruction, replace a dead definition of a GPR with
10 // the zero register. This makes the code a bit friendlier towards the
11 // hardware's register renamer.
12 //===----------------------------------------------------------------------===//
13
14 #include "AArch64.h"
15 #include "AArch64RegisterInfo.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
23 using namespace llvm;
24
25 #define DEBUG_TYPE "aarch64-dead-defs"
26
27 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
28
29 namespace llvm {
30 void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &);
31 }
32
33 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
34
35 namespace {
36 class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
37 private:
38 const TargetRegisterInfo *TRI;
39 bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
40 bool processMachineBasicBlock(MachineBasicBlock &MBB);
41 bool usesFrameIndex(const MachineInstr &MI);
42 public:
43 static char ID; // Pass identification, replacement for typeid.
AArch64DeadRegisterDefinitions()44 explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
45 initializeAArch64DeadRegisterDefinitionsPass(
46 *PassRegistry::getPassRegistry());
47 }
48
49 bool runOnMachineFunction(MachineFunction &F) override;
50
getPassName() const51 const char *getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
52
getAnalysisUsage(AnalysisUsage & AU) const53 void getAnalysisUsage(AnalysisUsage &AU) const override {
54 AU.setPreservesCFG();
55 MachineFunctionPass::getAnalysisUsage(AU);
56 }
57 };
58 char AArch64DeadRegisterDefinitions::ID = 0;
59 } // end anonymous namespace
60
61 INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
62 AARCH64_DEAD_REG_DEF_NAME, false, false)
63
implicitlyDefinesOverlappingReg(unsigned Reg,const MachineInstr & MI)64 bool AArch64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg(
65 unsigned Reg, const MachineInstr &MI) {
66 for (const MachineOperand &MO : MI.implicit_operands())
67 if (MO.isReg() && MO.isDef())
68 if (TRI->regsOverlap(Reg, MO.getReg()))
69 return true;
70 return false;
71 }
72
usesFrameIndex(const MachineInstr & MI)73 bool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) {
74 for (const MachineOperand &Op : MI.uses())
75 if (Op.isFI())
76 return true;
77 return false;
78 }
79
processMachineBasicBlock(MachineBasicBlock & MBB)80 bool AArch64DeadRegisterDefinitions::processMachineBasicBlock(
81 MachineBasicBlock &MBB) {
82 bool Changed = false;
83 for (MachineInstr &MI : MBB) {
84 if (usesFrameIndex(MI)) {
85 // We need to skip this instruction because while it appears to have a
86 // dead def it uses a frame index which might expand into a multi
87 // instruction sequence during EPI.
88 DEBUG(dbgs() << " Ignoring, operand is frame index\n");
89 continue;
90 }
91 for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
92 MachineOperand &MO = MI.getOperand(i);
93 if (MO.isReg() && MO.isDead() && MO.isDef()) {
94 assert(!MO.isImplicit() && "Unexpected implicit def!");
95 DEBUG(dbgs() << " Dead def operand #" << i << " in:\n ";
96 MI.print(dbgs()));
97 // Be careful not to change the register if it's a tied operand.
98 if (MI.isRegTiedToUseOperand(i)) {
99 DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
100 continue;
101 }
102 // Don't change the register if there's an implicit def of a subreg or
103 // supperreg.
104 if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
105 DEBUG(dbgs() << " Ignoring, implicitly defines overlap reg.\n");
106 continue;
107 }
108 // Make sure the instruction take a register class that contains
109 // the zero register and replace it if so.
110 unsigned NewReg;
111 switch (MI.getDesc().OpInfo[i].RegClass) {
112 default:
113 DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
114 continue;
115 case AArch64::GPR32RegClassID:
116 NewReg = AArch64::WZR;
117 break;
118 case AArch64::GPR64RegClassID:
119 NewReg = AArch64::XZR;
120 break;
121 }
122 DEBUG(dbgs() << " Replacing with zero register. New:\n ");
123 MO.setReg(NewReg);
124 DEBUG(MI.print(dbgs()));
125 ++NumDeadDefsReplaced;
126 }
127 }
128 }
129 return Changed;
130 }
131
132 // Scan the function for instructions that have a dead definition of a
133 // register. Replace that register with the zero register when possible.
runOnMachineFunction(MachineFunction & MF)134 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
135 TRI = MF.getSubtarget().getRegisterInfo();
136 bool Changed = false;
137 DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
138
139 for (auto &MBB : MF)
140 if (processMachineBasicBlock(MBB))
141 Changed = true;
142 return Changed;
143 }
144
createAArch64DeadRegisterDefinitions()145 FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
146 return new AArch64DeadRegisterDefinitions();
147 }
148