1//===-- VIInstrFormats.td - VI Instruction Encodings ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// VI Instruction format definitions. 11// 12//===----------------------------------------------------------------------===// 13 14class DSe_vi <bits<8> op> : Enc64 { 15 bits<8> vdst; 16 bits<1> gds; 17 bits<8> addr; 18 bits<8> data0; 19 bits<8> data1; 20 bits<8> offset0; 21 bits<8> offset1; 22 23 let Inst{7-0} = offset0; 24 let Inst{15-8} = offset1; 25 let Inst{16} = gds; 26 let Inst{24-17} = op; 27 let Inst{31-26} = 0x36; //encoding 28 let Inst{39-32} = addr; 29 let Inst{47-40} = data0; 30 let Inst{55-48} = data1; 31 let Inst{63-56} = vdst; 32} 33 34class MUBUFe_vi <bits<7> op> : Enc64 { 35 bits<12> offset; 36 bits<1> offen; 37 bits<1> idxen; 38 bits<1> glc; 39 bits<1> lds; 40 bits<8> vaddr; 41 bits<8> vdata; 42 bits<7> srsrc; 43 bits<1> slc; 44 bits<1> tfe; 45 bits<8> soffset; 46 47 let Inst{11-0} = offset; 48 let Inst{12} = offen; 49 let Inst{13} = idxen; 50 let Inst{14} = glc; 51 let Inst{16} = lds; 52 let Inst{17} = slc; 53 let Inst{24-18} = op; 54 let Inst{31-26} = 0x38; //encoding 55 let Inst{39-32} = vaddr; 56 let Inst{47-40} = vdata; 57 let Inst{52-48} = srsrc{6-2}; 58 let Inst{55} = tfe; 59 let Inst{63-56} = soffset; 60} 61 62class MTBUFe_vi <bits<4> op> : Enc64 { 63 bits<12> offset; 64 bits<1> offen; 65 bits<1> idxen; 66 bits<1> glc; 67 bits<4> dfmt; 68 bits<3> nfmt; 69 bits<8> vaddr; 70 bits<8> vdata; 71 bits<7> srsrc; 72 bits<1> slc; 73 bits<1> tfe; 74 bits<8> soffset; 75 76 let Inst{11-0} = offset; 77 let Inst{12} = offen; 78 let Inst{13} = idxen; 79 let Inst{14} = glc; 80 let Inst{18-15} = op; 81 let Inst{22-19} = dfmt; 82 let Inst{25-23} = nfmt; 83 let Inst{31-26} = 0x3a; //encoding 84 let Inst{39-32} = vaddr; 85 let Inst{47-40} = vdata; 86 let Inst{52-48} = srsrc{6-2}; 87 let Inst{54} = slc; 88 let Inst{55} = tfe; 89 let Inst{63-56} = soffset; 90} 91 92class SMEMe_vi <bits<8> op, bit imm> : Enc64 { 93 bits<7> sbase; 94 bits<7> sdata; 95 bits<1> glc; 96 bits<20> offset; 97 98 let Inst{5-0} = sbase{6-1}; 99 let Inst{12-6} = sdata; 100 let Inst{16} = glc; 101 let Inst{17} = imm; 102 let Inst{25-18} = op; 103 let Inst{31-26} = 0x30; //encoding 104 let Inst{51-32} = offset; 105} 106 107class VOP3e_vi <bits<10> op> : Enc64 { 108 bits<8> vdst; 109 bits<2> src0_modifiers; 110 bits<9> src0; 111 bits<2> src1_modifiers; 112 bits<9> src1; 113 bits<2> src2_modifiers; 114 bits<9> src2; 115 bits<1> clamp; 116 bits<2> omod; 117 118 let Inst{7-0} = vdst; 119 let Inst{8} = src0_modifiers{1}; 120 let Inst{9} = src1_modifiers{1}; 121 let Inst{10} = src2_modifiers{1}; 122 let Inst{15} = clamp; 123 let Inst{25-16} = op; 124 let Inst{31-26} = 0x34; //encoding 125 let Inst{40-32} = src0; 126 let Inst{49-41} = src1; 127 let Inst{58-50} = src2; 128 let Inst{60-59} = omod; 129 let Inst{61} = src0_modifiers{0}; 130 let Inst{62} = src1_modifiers{0}; 131 let Inst{63} = src2_modifiers{0}; 132} 133 134class VOP3be_vi <bits<10> op> : Enc64 { 135 bits<8> vdst; 136 bits<2> src0_modifiers; 137 bits<9> src0; 138 bits<2> src1_modifiers; 139 bits<9> src1; 140 bits<2> src2_modifiers; 141 bits<9> src2; 142 bits<7> sdst; 143 bits<2> omod; 144 bits<1> clamp; 145 146 let Inst{7-0} = vdst; 147 let Inst{14-8} = sdst; 148 let Inst{15} = clamp; 149 let Inst{25-16} = op; 150 let Inst{31-26} = 0x34; //encoding 151 let Inst{40-32} = src0; 152 let Inst{49-41} = src1; 153 let Inst{58-50} = src2; 154 let Inst{60-59} = omod; 155 let Inst{61} = src0_modifiers{0}; 156 let Inst{62} = src1_modifiers{0}; 157 let Inst{63} = src2_modifiers{0}; 158} 159 160class EXPe_vi : EXPe { 161 let Inst{31-26} = 0x31; //encoding 162} 163 164class VINTRPe_vi <bits<2> op> : VINTRPe <op> { 165 let Inst{31-26} = 0x35; // encoding 166} 167