1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// ARM Helper classes. 21// 22 23class ProcNoItin<string Name, list<SubtargetFeature> Features> 24 : Processor<Name, NoItineraries, Features>; 25 26class Architecture<string fname, string aname, list<SubtargetFeature> features > 27 : SubtargetFeature<fname, "ARMArch", aname, 28 !strconcat(aname, " architecture"), features>; 29 30//===----------------------------------------------------------------------===// 31// ARM Subtarget state. 32// 33 34def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 35 "Thumb mode">; 36 37def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 38 "Use software floating point features.">; 39 40//===----------------------------------------------------------------------===// 41// ARM Subtarget features. 42// 43 44def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 45 "Enable VFP2 instructions">; 46def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 47 "Enable VFP3 instructions", 48 [FeatureVFP2]>; 49def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 50 "Enable NEON instructions", 51 [FeatureVFP3]>; 52def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 53 "Enable Thumb2 instructions">; 54def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 55 "Does not support ARM mode execution", 56 [ModeThumb]>; 57def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 58 "Enable half-precision floating point">; 59def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 60 "Enable VFP4 instructions", 61 [FeatureVFP3, FeatureFP16]>; 62def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", 63 "true", "Enable ARMv8 FP", 64 [FeatureVFP4]>; 65def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 66 "Enable full half-precision floating point", 67 [FeatureFPARMv8]>; 68def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 69 "Restrict FP to 16 double registers">; 70def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 71 "Enable divide instructions">; 72def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 73 "HasHardwareDivideInARM", "true", 74 "Enable divide instructions in ARM mode">; 75def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 76 "Enable Thumb2 extract and pack instructions">; 77def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 78 "Has data barrier (dmb / dsb) instructions">; 79def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 80 "FP compare + branch is slow">; 81def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 82 "Floating point unit supports single precision only">; 83def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 84 "Enable support for Performance Monitor extensions">; 85def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 86 "Enable support for TrustZone security extensions">; 87def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 88 "Enable support for Cryptography extensions", 89 [FeatureNEON]>; 90def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 91 "Enable support for CRC instructions">; 92 93// Cyclone has preferred instructions for zeroing VFP registers, which can 94// execute in 0 cycles. 95def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 96 "Has zero-cycle zeroing instructions">; 97 98// Some processors have FP multiply-accumulate instructions that don't 99// play nicely with other VFP / NEON instructions, and it's generally better 100// to just not use them. 101def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 102 "Disable VFP / NEON MAC instructions">; 103 104// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 105def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 106 "HasVMLxForwarding", "true", 107 "Has multiplier accumulator forwarding">; 108 109// Some processors benefit from using NEON instructions for scalar 110// single-precision FP operations. 111def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 112 "true", 113 "Use NEON for single precision FP">; 114 115// Disable 32-bit to 16-bit narrowing for experimentation. 116def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 117 "Prefer 32-bit Thumb instrs">; 118 119/// Some instructions update CPSR partially, which can add false dependency for 120/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 121/// mapped to a separate physical register. Avoid partial CPSR update for these 122/// processors. 123def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 124 "AvoidCPSRPartialUpdate", "true", 125 "Avoid CPSR partial update for OOO execution">; 126 127def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 128 "AvoidMOVsShifterOperand", "true", 129 "Avoid movs instructions with shifter operand">; 130 131// Some processors perform return stack prediction. CodeGen should avoid issue 132// "normal" call instructions to callees which do not return. 133def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true", 134 "Has return address stack">; 135 136/// DSP extension. 137def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", 138 "Supports DSP instructions in ARM and/or Thumb2">; 139 140// Multiprocessing extension. 141def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 142 "Supports Multiprocessing extension">; 143 144// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 145def FeatureVirtualization : SubtargetFeature<"virtualization", 146 "HasVirtualization", "true", 147 "Supports Virtualization extension", 148 [FeatureHWDiv, FeatureHWDivARM]>; 149 150// M-series ISA 151def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 152 "Is microcontroller profile ('M' series)">; 153 154// R-series ISA 155def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 156 "Is realtime profile ('R' series)">; 157 158// A-series ISA 159def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 160 "Is application profile ('A' series)">; 161 162// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 163// See ARMInstrInfo.td for details. 164def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 165 "NaCl trap">; 166 167// RenderScript-specific support for 64-bit long types on all targets 168def FeatureLong64 : SubtargetFeature<"long64", "UseLong64", 169 "true", 170 "long type is forced to be 64-bit">; 171 172def FeatureStrictAlign : SubtargetFeature<"strict-align", 173 "StrictAlign", "true", 174 "Disallow all unaligned memory " 175 "access">; 176 177def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", 178 "Generate calls via indirect call " 179 "instructions">; 180 181def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", 182 "Reserve R9, making it unavailable as " 183 "GPR">; 184 185def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", 186 "Don't use movt/movw pairs for 32-bit " 187 "imms">; 188 189 190//===----------------------------------------------------------------------===// 191// ARM ISAa. 192// 193 194def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 195 "Support ARM v4T instructions">; 196def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 197 "Support ARM v5T instructions", 198 [HasV4TOps]>; 199def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 200 "Support ARM v5TE, v5TEj, and v5TExp instructions", 201 [HasV5TOps]>; 202def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 203 "Support ARM v6 instructions", 204 [HasV5TEOps]>; 205def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 206 "Support ARM v6M instructions", 207 [HasV6Ops]>; 208def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", 209 "Support ARM v6k instructions", 210 [HasV6Ops]>; 211def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 212 "Support ARM v6t2 instructions", 213 [HasV6MOps, HasV6KOps, FeatureThumb2]>; 214def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 215 "Support ARM v7 instructions", 216 [HasV6T2Ops, FeaturePerfMon]>; 217def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 218 "Support ARM v8 instructions", 219 [HasV7Ops]>; 220def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 221 "Support ARM v8.1a instructions", 222 [HasV8Ops]>; 223def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 224 "Support ARM v8.2a instructions", 225 [HasV8_1aOps]>; 226 227 228//===----------------------------------------------------------------------===// 229// ARM Processor subtarget features. 230// 231 232def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 233 "Cortex-A5 ARM processors", []>; 234def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", 235 "Cortex-A7 ARM processors", []>; 236def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 237 "Cortex-A8 ARM processors", []>; 238def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 239 "Cortex-A9 ARM processors", []>; 240def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", 241 "Cortex-A12 ARM processors", []>; 242def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 243 "Cortex-A15 ARM processors", []>; 244def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", 245 "Cortex-A17 ARM processors", []>; 246def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 247 "Cortex-A35 ARM processors", []>; 248def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 249 "Cortex-A53 ARM processors", []>; 250def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 251 "Cortex-A57 ARM processors", []>; 252def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 253 "Cortex-A72 ARM processors", []>; 254 255def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", 256 "Qualcomm ARM processors", []>; 257def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 258 "Swift ARM processors", []>; 259 260 261def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", 262 "Cortex-R4 ARM processors", []>; 263def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 264 "Cortex-R5 ARM processors", []>; 265def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", 266 "Cortex-R7 ARM processors", []>; 267 268 269//===----------------------------------------------------------------------===// 270// ARM schedules. 271// 272 273include "ARMSchedule.td" 274 275 276//===----------------------------------------------------------------------===// 277// ARM architectures 278// 279 280def ARMv2 : Architecture<"armv2", "ARMv2", []>; 281 282def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; 283 284def ARMv3 : Architecture<"armv3", "ARMv3", []>; 285 286def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; 287 288def ARMv4 : Architecture<"armv4", "ARMv4", []>; 289 290def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; 291 292def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; 293 294def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; 295 296def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; 297 298def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>; 299 300def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, 301 FeatureDSP]>; 302 303def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; 304 305def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, 306 FeatureTrustZone]>; 307 308def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, 309 FeatureNoARM, 310 FeatureDB, 311 FeatureMClass]>; 312 313def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, 314 FeatureNoARM, 315 FeatureDB, 316 FeatureMClass]>; 317 318def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, 319 FeatureNEON, 320 FeatureDB, 321 FeatureDSP, 322 FeatureAClass]>; 323 324def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, 325 FeatureDB, 326 FeatureDSP, 327 FeatureHWDiv, 328 FeatureRClass]>; 329 330def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, 331 FeatureThumb2, 332 FeatureNoARM, 333 FeatureDB, 334 FeatureHWDiv, 335 FeatureMClass]>; 336 337def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, 338 FeatureThumb2, 339 FeatureNoARM, 340 FeatureDB, 341 FeatureHWDiv, 342 FeatureMClass, 343 FeatureDSP, 344 FeatureT2XtPk]>; 345 346def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, 347 FeatureAClass, 348 FeatureDB, 349 FeatureFPARMv8, 350 FeatureNEON, 351 FeatureDSP, 352 FeatureTrustZone, 353 FeatureMP, 354 FeatureVirtualization, 355 FeatureCrypto, 356 FeatureCRC]>; 357 358def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, 359 FeatureAClass, 360 FeatureDB, 361 FeatureFPARMv8, 362 FeatureNEON, 363 FeatureDSP, 364 FeatureTrustZone, 365 FeatureMP, 366 FeatureVirtualization, 367 FeatureCrypto, 368 FeatureCRC]>; 369 370def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, 371 FeatureAClass, 372 FeatureDB, 373 FeatureFPARMv8, 374 FeatureNEON, 375 FeatureDSP, 376 FeatureTrustZone, 377 FeatureMP, 378 FeatureVirtualization, 379 FeatureCrypto, 380 FeatureCRC]>; 381 382// Aliases 383def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; 384def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; 385def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; 386def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; 387def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; 388def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; 389 390 391//===----------------------------------------------------------------------===// 392// ARM processors 393// 394 395// Dummy CPU, used to target architectures 396def : ProcNoItin<"generic", []>; 397 398def : ProcNoItin<"arm8", [ARMv4]>; 399def : ProcNoItin<"arm810", [ARMv4]>; 400def : ProcNoItin<"strongarm", [ARMv4]>; 401def : ProcNoItin<"strongarm110", [ARMv4]>; 402def : ProcNoItin<"strongarm1100", [ARMv4]>; 403def : ProcNoItin<"strongarm1110", [ARMv4]>; 404 405def : ProcNoItin<"arm7tdmi", [ARMv4t]>; 406def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; 407def : ProcNoItin<"arm710t", [ARMv4t]>; 408def : ProcNoItin<"arm720t", [ARMv4t]>; 409def : ProcNoItin<"arm9", [ARMv4t]>; 410def : ProcNoItin<"arm9tdmi", [ARMv4t]>; 411def : ProcNoItin<"arm920", [ARMv4t]>; 412def : ProcNoItin<"arm920t", [ARMv4t]>; 413def : ProcNoItin<"arm922t", [ARMv4t]>; 414def : ProcNoItin<"arm940t", [ARMv4t]>; 415def : ProcNoItin<"ep9312", [ARMv4t]>; 416 417def : ProcNoItin<"arm10tdmi", [ARMv5t]>; 418def : ProcNoItin<"arm1020t", [ARMv5t]>; 419 420def : ProcNoItin<"arm9e", [ARMv5te]>; 421def : ProcNoItin<"arm926ej-s", [ARMv5te]>; 422def : ProcNoItin<"arm946e-s", [ARMv5te]>; 423def : ProcNoItin<"arm966e-s", [ARMv5te]>; 424def : ProcNoItin<"arm968e-s", [ARMv5te]>; 425def : ProcNoItin<"arm10e", [ARMv5te]>; 426def : ProcNoItin<"arm1020e", [ARMv5te]>; 427def : ProcNoItin<"arm1022e", [ARMv5te]>; 428def : ProcNoItin<"xscale", [ARMv5te]>; 429def : ProcNoItin<"iwmmxt", [ARMv5te]>; 430 431def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; 432def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, 433 FeatureVFP2, 434 FeatureHasSlowFPVMLx]>; 435 436def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; 437def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; 438def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; 439def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; 440 441def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; 442def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, 443 FeatureVFP2, 444 FeatureHasSlowFPVMLx]>; 445 446def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; 447def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, 448 FeatureVFP2, 449 FeatureHasSlowFPVMLx]>; 450 451def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; 452def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, 453 FeatureVFP2, 454 FeatureHasSlowFPVMLx]>; 455 456// FIXME: A5 has currently the same Schedule model as A8 457def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, 458 FeatureHasRAS, 459 FeatureTrustZone, 460 FeatureSlowFPBrcc, 461 FeatureHasSlowFPVMLx, 462 FeatureVMLxForwarding, 463 FeatureT2XtPk, 464 FeatureMP, 465 FeatureVFP4]>; 466 467def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, 468 FeatureHasRAS, 469 FeatureTrustZone, 470 FeatureSlowFPBrcc, 471 FeatureHasSlowFPVMLx, 472 FeatureVMLxForwarding, 473 FeatureT2XtPk, 474 FeatureMP, 475 FeatureVFP4, 476 FeatureHWDiv, 477 FeatureHWDivARM, 478 FeatureVirtualization]>; 479 480def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, 481 FeatureHasRAS, 482 FeatureTrustZone, 483 FeatureSlowFPBrcc, 484 FeatureHasSlowFPVMLx, 485 FeatureVMLxForwarding, 486 FeatureT2XtPk]>; 487 488def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, 489 FeatureHasRAS, 490 FeatureTrustZone, 491 FeatureVMLxForwarding, 492 FeatureT2XtPk, 493 FeatureFP16, 494 FeatureAvoidPartialCPSR, 495 FeatureMP]>; 496 497// FIXME: A12 has currently the same Schedule model as A9 498def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, 499 FeatureHasRAS, 500 FeatureTrustZone, 501 FeatureVMLxForwarding, 502 FeatureT2XtPk, 503 FeatureVFP4, 504 FeatureHWDiv, 505 FeatureHWDivARM, 506 FeatureAvoidPartialCPSR, 507 FeatureVirtualization, 508 FeatureMP]>; 509 510// FIXME: A15 has currently the same Schedule model as A9. 511def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, 512 FeatureHasRAS, 513 FeatureTrustZone, 514 FeatureT2XtPk, 515 FeatureVFP4, 516 FeatureMP, 517 FeatureHWDiv, 518 FeatureHWDivARM, 519 FeatureAvoidPartialCPSR, 520 FeatureVirtualization]>; 521 522// FIXME: A17 has currently the same Schedule model as A9 523def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, 524 FeatureHasRAS, 525 FeatureTrustZone, 526 FeatureMP, 527 FeatureVMLxForwarding, 528 FeatureT2XtPk, 529 FeatureVFP4, 530 FeatureHWDiv, 531 FeatureHWDivARM, 532 FeatureAvoidPartialCPSR, 533 FeatureVirtualization]>; 534 535// FIXME: krait has currently the same Schedule model as A9 536// FIXME: krait has currently the same features as A9 plus VFP4 and hardware 537// division features. 538def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, 539 FeatureHasRAS, 540 FeatureVMLxForwarding, 541 FeatureT2XtPk, 542 FeatureFP16, 543 FeatureAvoidPartialCPSR, 544 FeatureVFP4, 545 FeatureHWDiv, 546 FeatureHWDivARM]>; 547 548def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, 549 FeatureHasRAS, 550 FeatureNEONForFP, 551 FeatureT2XtPk, 552 FeatureVFP4, 553 FeatureMP, 554 FeatureHWDiv, 555 FeatureHWDivARM, 556 FeatureAvoidPartialCPSR, 557 FeatureAvoidMOVsShOp, 558 FeatureHasSlowFPVMLx]>; 559 560// FIXME: R4 has currently the same ProcessorModel as A8. 561def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, 562 FeatureHasRAS, 563 FeatureAvoidPartialCPSR, 564 FeatureT2XtPk]>; 565 566// FIXME: R4F has currently the same ProcessorModel as A8. 567def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, 568 FeatureHasRAS, 569 FeatureSlowFPBrcc, 570 FeatureHasSlowFPVMLx, 571 FeatureVFP3, 572 FeatureD16, 573 FeatureAvoidPartialCPSR, 574 FeatureT2XtPk]>; 575 576// FIXME: R5 has currently the same ProcessorModel as A8. 577def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, 578 FeatureHasRAS, 579 FeatureVFP3, 580 FeatureD16, 581 FeatureSlowFPBrcc, 582 FeatureHWDivARM, 583 FeatureHasSlowFPVMLx, 584 FeatureAvoidPartialCPSR, 585 FeatureT2XtPk]>; 586 587// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5. 588def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, 589 FeatureHasRAS, 590 FeatureVFP3, 591 FeatureVFPOnlySP, 592 FeatureD16, 593 FeatureFP16, 594 FeatureMP, 595 FeatureSlowFPBrcc, 596 FeatureHWDivARM, 597 FeatureHasSlowFPVMLx, 598 FeatureAvoidPartialCPSR, 599 FeatureT2XtPk]>; 600 601def : ProcNoItin<"cortex-m3", [ARMv7m]>; 602def : ProcNoItin<"sc300", [ARMv7m]>; 603 604def : ProcNoItin<"cortex-m4", [ARMv7em, 605 FeatureVFP4, 606 FeatureVFPOnlySP, 607 FeatureD16]>; 608 609def : ProcNoItin<"cortex-m7", [ARMv7em, 610 FeatureFPARMv8, 611 FeatureD16]>; 612 613 614def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, 615 FeatureHWDiv, 616 FeatureHWDivARM, 617 FeatureT2XtPk, 618 FeatureCrypto, 619 FeatureCRC]>; 620 621def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, 622 FeatureHWDiv, 623 FeatureHWDivARM, 624 FeatureT2XtPk, 625 FeatureCrypto, 626 FeatureCRC]>; 627 628def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57, 629 FeatureHWDiv, 630 FeatureHWDivARM, 631 FeatureT2XtPk, 632 FeatureCrypto, 633 FeatureCRC]>; 634 635def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72, 636 FeatureHWDiv, 637 FeatureHWDivARM, 638 FeatureT2XtPk, 639 FeatureCrypto, 640 FeatureCRC]>; 641 642// Cyclone is very similar to swift 643def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, 644 FeatureHasRAS, 645 FeatureNEONForFP, 646 FeatureT2XtPk, 647 FeatureVFP4, 648 FeatureMP, 649 FeatureHWDiv, 650 FeatureHWDivARM, 651 FeatureAvoidPartialCPSR, 652 FeatureAvoidMOVsShOp, 653 FeatureHasSlowFPVMLx, 654 FeatureCrypto, 655 FeatureZCZeroing]>; 656 657 658//===----------------------------------------------------------------------===// 659// Register File Description 660//===----------------------------------------------------------------------===// 661 662include "ARMRegisterInfo.td" 663 664include "ARMCallingConv.td" 665 666//===----------------------------------------------------------------------===// 667// Instruction Descriptions 668//===----------------------------------------------------------------------===// 669 670include "ARMInstrInfo.td" 671 672def ARMInstrInfo : InstrInfo; 673 674//===----------------------------------------------------------------------===// 675// Declare the target which we are implementing 676//===----------------------------------------------------------------------===// 677 678def ARMAsmWriter : AsmWriter { 679 string AsmWriterClassName = "InstPrinter"; 680 int PassSubtarget = 1; 681 int Variant = 0; 682 bit isMCAsmWriter = 1; 683} 684 685def ARMAsmParserVariant : AsmParserVariant { 686 int Variant = 0; 687 string Name = "ARM"; 688 string BreakCharacters = "."; 689} 690 691def ARM : Target { 692 // Pull in Instruction Info: 693 let InstructionSet = ARMInstrInfo; 694 let AssemblyWriters = [ARMAsmWriter]; 695 let AssemblyParserVariants = [ARMAsmParserVariant]; 696} 697