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1//===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class MMDSPInst<string opstr = "">
11    : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
12  let InsnPredicates = [HasDSP];
13  let AdditionalPredicates = [InMicroMips];
14  string BaseOpcode = opstr;
15  string Arch = "mmdsp";
16  let DecoderNamespace = "MicroMips";
17}
18
19class MMDSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
20    : InstAlias<Asm, Result, Emit>, PredicateControl {
21  let InsnPredicates = [HasDSP];
22  let AdditionalPredicates = [InMicroMips];
23}
24
25class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
26  bits<5> rd;
27  bits<5> rs;
28  bits<5> rt;
29
30  let Inst{31-26} = 0b000000;
31  let Inst{25-21} = rt;
32  let Inst{20-16} = rs;
33  let Inst{15-11} = rd;
34  let Inst{10-0}  = op;
35}
36
37class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
38  bits<5> rt;
39  bits<5> rs;
40
41  let Inst{31-26} = 0b000000;
42  let Inst{25-21} = rt;
43  let Inst{20-16} = rs;
44  let Inst{15-6}  = op;
45  let Inst{5-0}   = 0b111100;
46}
47
48class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
49  bits<5> rt;
50  bits<5> rs;
51  bits<2> ac;
52
53  let Inst{31-26} = 0b000000;
54  let Inst{25-21} = rt;
55  let Inst{20-16} = rs;
56  let Inst{15-14} = ac;
57  let Inst{13-6}  = op;
58  let Inst{5-0}   = 0b111100;
59}
60
61class POOL32A_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
62  bits<5> rd;
63  bits<5> rs;
64  bits<5> rt;
65
66  let Inst{31-26} = 0b000000;
67  let Inst{25-21} = rt;
68  let Inst{20-16} = rs;
69  let Inst{15-11} = rd;
70  let Inst{10}    = 0b0;
71  let Inst{9-0}   = op;
72}
73
74class POOL32A_2RSA4_FMT<string opstr, bits<12> op> : MMDSPInst<opstr> {
75  bits<5> rt;
76  bits<5> rs;
77  bits<4> sa;
78
79  let Inst{31-26} = 0b000000;
80  let Inst{25-21} = rt;
81  let Inst{20-16} = rs;
82  let Inst{15-12} = sa;
83  let Inst{11-0}  = op;
84}
85
86class POOL32A_2RSA3_FMT<string opstr, bits<7> op> : MMDSPInst<opstr> {
87  bits<5> rt;
88  bits<5> rs;
89  bits<3> sa;
90
91  let Inst{31-26} = 0b000000;
92  let Inst{25-21} = rt;
93  let Inst{20-16} = rs;
94  let Inst{15-13} = sa;
95  let Inst{12-6}  = op;
96  let Inst{5-0}   = 0b111100;
97}
98
99class POOL32A_2RSA5B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
100  bits<5> rt;
101  bits<5> rs;
102  bits<5> sa;
103
104  let Inst{31-26} = 0b000000;
105  let Inst{25-21} = rt;
106  let Inst{20-16} = rs;
107  let Inst{15-11} = sa;
108  let Inst{10}    = 0b0;
109  let Inst{9-0}   = op;
110}
111
112class POOL32A_2RSA4B0_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
113  bits<5> rt;
114  bits<5> rs;
115  bits<4> sa;
116
117  let Inst{31-26} = 0b000000;
118  let Inst{25-21} = rt;
119  let Inst{20-16} = rs;
120  let Inst{15-12} = sa;
121  let Inst{11}    = 0b0;
122  let Inst{10-0}  = op;
123}
124
125class POOL32A_2RSA4OP6_FMT<string opstr, bits<6> op> : MMDSPInst<opstr> {
126  bits<5> rt;
127  bits<5> rs;
128  bits<4> sa;
129
130  let Inst{31-26} = 0b000000;
131  let Inst{25-21} = rt;
132  let Inst{20-16} = rs;
133  let Inst{15-12} = sa;
134  let Inst{11-6}  = op;
135  let Inst{5-0}   = 0b111100;
136}
137
138class POOL32A_1RIMM5AC_FMT<string opstr, bits<8> funct> : MMDSPInst<opstr> {
139  bits<5> rt;
140  bits<5> imm;
141  bits<2> ac;
142
143  let Inst{31-26} = 0b000000;
144  let Inst{25-21} = rt;
145  let Inst{20-16} = imm;
146  let Inst{15-14} = ac;
147  let Inst{13-6}  = funct;
148  let Inst{5-0}   = 0b111100;
149}
150
151class POOL32A_2RSA5_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
152  bits<5> rt;
153  bits<5> rs;
154  bits<5> sa;
155
156  let Inst{31-26} = 0b000000;
157  let Inst{25-21} = rt;
158  let Inst{20-16} = rs;
159  let Inst{15-11} = sa;
160  let Inst{10-0}  = op;
161}
162
163class POOL32A_1RMEMB0_FMT<string opstr, bits<10> funct> : MMDSPInst<opstr> {
164  bits<5> index;
165  bits<5> base;
166  bits<5> rd;
167
168  let Inst{31-26} = 0;
169  let Inst{25-21} = index;
170  let Inst{20-16} = base;
171  let Inst{15-11} = rd;
172  let Inst{10}    = 0b0;
173  let Inst{9-0}   = funct;
174}
175
176class POOL32A_1RAC_FMT<string instr_asm, bits<8> funct> : MMDSPInst<instr_asm> {
177  bits<5> rs;
178  bits<2> ac;
179
180  let Inst{31-26} = 0;
181  let Inst{25-21} = 0;
182  let Inst{20-16} = rs;
183  let Inst{15-14} = ac;
184  let Inst{13-6}  = funct;
185  let Inst{5-0}   = 0b111100;
186}
187
188class POOL32A_1RMASK7_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
189  bits<5> rt;
190  bits<7> mask;
191
192  let Inst{31-26} = 0b000000;
193  let Inst{25-21} = rt;
194  let Inst{20-14} = mask;
195  let Inst{13-6}  = op;
196  let Inst{5-0}   = 0b111100;
197}
198
199class POOL32A_1RIMM10_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
200  bits<5> rd;
201  bits<10> imm;
202
203  let Inst{31-26} = 0;
204  let Inst{25-16} = imm;
205  let Inst{15-11} = rd;
206  let Inst{10}    = 0;
207  let Inst{9-0}   = op;
208}
209
210class POOL32A_1RIMM8_FMT<string opstr, bits<6> op> : MMDSPInst<opstr> {
211  bits<5> rt;
212  bits<8> imm;
213
214  let Inst{31-26} = 0;
215  let Inst{25-21} = rt;
216  let Inst{20-13} = imm;
217  let Inst{12}    = 0;
218  let Inst{11-6}  = op;
219  let Inst{5-0}   = 0b111100;
220}
221
222class POOL32A_4B0SHIFT6AC4B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
223  bits<6> shift;
224  bits<2> ac;
225
226  let Inst{31-26} = 0b000000;
227  let Inst{25-22} = 0b0000;
228  let Inst{21-16} = shift;
229  let Inst{15-14} = ac;
230  let Inst{13-10} = 0b0000;
231  let Inst{9-0}   = op;
232}
233
234class POOL32A_5B01RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
235  bits<5> rs;
236  bits<2> ac;
237
238  let Inst{31-26} = 0b000000;
239  let Inst{25-21} = 0b00000;
240  let Inst{20-16} = rs;
241  let Inst{15-14} = ac;
242  let Inst{13-6}  = op;
243  let Inst{5-0}   = 0b111100;
244}
245