1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __MSMB_ISP__ 20 #define __MSMB_ISP__ 21 #include <linux/videodev2.h> 22 #define MAX_PLANES_PER_STREAM 3 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define MAX_NUM_STREAM 7 25 #define ISP_VERSION_47 47 26 #define ISP_VERSION_46 46 27 #define ISP_VERSION_44 44 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define ISP_VERSION_40 40 30 #define ISP_VERSION_32 32 31 #define ISP_NATIVE_BUF_BIT (0x10000 << 0) 32 #define ISP0_BIT (0x10000 << 1) 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define ISP1_BIT (0x10000 << 2) 35 #define ISP_META_CHANNEL_BIT (0x10000 << 3) 36 #define ISP_SCRATCH_BUF_BIT (0x10000 << 4) 37 #define ISP_OFFLINE_STATS_BIT (0x10000 << 5) 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define ISP_STATS_STREAM_BIT 0x80000000 40 struct msm_vfe_cfg_cmd_list; 41 enum ISP_START_PIXEL_PATTERN { 42 ISP_BAYER_RGRGRG, 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 ISP_BAYER_GRGRGR, 45 ISP_BAYER_BGBGBG, 46 ISP_BAYER_GBGBGB, 47 ISP_YUV_YCbYCr, 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 ISP_YUV_YCrYCb, 50 ISP_YUV_CbYCrY, 51 ISP_YUV_CrYCbY, 52 ISP_PIX_PATTERN_MAX 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 }; 55 enum msm_vfe_plane_fmt { 56 Y_PLANE, 57 CB_PLANE, 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 CR_PLANE, 60 CRCB_PLANE, 61 CBCR_PLANE, 62 VFE_PLANE_FMT_MAX 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 }; 65 enum msm_vfe_input_src { 66 VFE_PIX_0, 67 VFE_RAW_0, 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 VFE_RAW_1, 70 VFE_RAW_2, 71 VFE_SRC_MAX, 72 }; 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 enum msm_vfe_axi_stream_src { 75 PIX_ENCODER, 76 PIX_VIEWFINDER, 77 PIX_VIDEO, 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 CAMIF_RAW, 80 IDEAL_RAW, 81 RDI_INTF_0, 82 RDI_INTF_1, 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 RDI_INTF_2, 85 VFE_AXI_SRC_MAX 86 }; 87 enum msm_vfe_frame_skip_pattern { 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 NO_SKIP, 90 EVERY_2FRAME, 91 EVERY_3FRAME, 92 EVERY_4FRAME, 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 EVERY_5FRAME, 95 EVERY_6FRAME, 96 EVERY_7FRAME, 97 EVERY_8FRAME, 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 EVERY_16FRAME, 100 EVERY_32FRAME, 101 SKIP_ALL, 102 SKIP_RANGE, 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 MAX_SKIP, 105 }; 106 #define MSM_VFE_STREAM_STOP_PERIOD 15 107 enum msm_isp_stats_type { 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 MSM_ISP_STATS_AEC, 110 MSM_ISP_STATS_AF, 111 MSM_ISP_STATS_AWB, 112 MSM_ISP_STATS_RS, 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 MSM_ISP_STATS_CS, 115 MSM_ISP_STATS_IHIST, 116 MSM_ISP_STATS_SKIN, 117 MSM_ISP_STATS_BG, 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 MSM_ISP_STATS_BF, 120 MSM_ISP_STATS_BE, 121 MSM_ISP_STATS_BHIST, 122 MSM_ISP_STATS_BF_SCALE, 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 MSM_ISP_STATS_HDR_BE, 125 MSM_ISP_STATS_HDR_BHIST, 126 MSM_ISP_STATS_AEC_BG, 127 MSM_ISP_STATS_MAX 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 }; 130 struct msm_isp_sw_framskip { 131 uint32_t stats_type_mask; 132 uint32_t stream_src_mask; 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 enum msm_vfe_frame_skip_pattern skip_mode; 135 uint32_t min_frame_id; 136 uint32_t max_frame_id; 137 }; 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 enum msm_vfe_testgen_color_pattern { 140 COLOR_BAR_8_COLOR, 141 UNICOLOR_WHITE, 142 UNICOLOR_YELLOW, 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 UNICOLOR_CYAN, 145 UNICOLOR_GREEN, 146 UNICOLOR_MAGENTA, 147 UNICOLOR_RED, 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 UNICOLOR_BLUE, 150 UNICOLOR_BLACK, 151 MAX_COLOR, 152 }; 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 enum msm_vfe_camif_input { 155 CAMIF_DISABLED, 156 CAMIF_PAD_REG_INPUT, 157 CAMIF_MIDDI_INPUT, 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 CAMIF_MIPI_INPUT, 160 }; 161 struct msm_vfe_fetch_engine_cfg { 162 uint32_t input_format; 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 uint32_t buf_width; 165 uint32_t buf_height; 166 uint32_t fetch_width; 167 uint32_t fetch_height; 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 uint32_t x_offset; 170 uint32_t y_offset; 171 uint32_t buf_stride; 172 }; 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 enum msm_vfe_camif_output_format { 175 CAMIF_QCOM_RAW, 176 CAMIF_MIPI_RAW, 177 CAMIF_PLAIN_8, 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 CAMIF_PLAIN_16, 180 CAMIF_MAX_FORMAT, 181 }; 182 struct msm_vfe_camif_subsample_cfg { 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 uint32_t irq_subsample_period; 185 uint32_t irq_subsample_pattern; 186 uint32_t sof_counter_step; 187 uint32_t pixel_skip; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 uint32_t line_skip; 190 uint32_t first_line; 191 uint32_t last_line; 192 uint32_t first_pixel; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 uint32_t last_pixel; 195 enum msm_vfe_camif_output_format output_format; 196 }; 197 struct msm_vfe_camif_cfg { 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 uint32_t lines_per_frame; 200 uint32_t pixels_per_line; 201 uint32_t first_pixel; 202 uint32_t last_pixel; 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 uint32_t first_line; 205 uint32_t last_line; 206 uint32_t epoch_line0; 207 uint32_t epoch_line1; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 uint32_t is_split; 210 enum msm_vfe_camif_input camif_input; 211 struct msm_vfe_camif_subsample_cfg subsample_cfg; 212 }; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 struct msm_vfe_testgen_cfg { 215 uint32_t lines_per_frame; 216 uint32_t pixels_per_line; 217 uint32_t v_blank; 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 uint32_t h_blank; 220 enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; 221 uint32_t rotate_period; 222 enum msm_vfe_testgen_color_pattern color_bar_pattern; 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 uint32_t burst_num_frame; 225 }; 226 enum msm_vfe_inputmux { 227 CAMIF, 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 TESTGEN, 230 EXTERNAL_READ, 231 }; 232 enum msm_vfe_stats_composite_group { 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 STATS_COMPOSITE_GRP_NONE, 235 STATS_COMPOSITE_GRP_1, 236 STATS_COMPOSITE_GRP_2, 237 STATS_COMPOSITE_GRP_MAX, 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 }; 240 enum msm_vfe_hvx_streaming_cmd { 241 HVX_DISABLE, 242 HVX_ONE_WAY, 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 HVX_ROUND_TRIP 245 }; 246 struct msm_vfe_pix_cfg { 247 struct msm_vfe_camif_cfg camif_cfg; 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 struct msm_vfe_testgen_cfg testgen_cfg; 250 struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; 251 enum msm_vfe_inputmux input_mux; 252 enum ISP_START_PIXEL_PATTERN pixel_pattern; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 uint32_t input_format; 255 enum msm_vfe_hvx_streaming_cmd hvx_cmd; 256 uint32_t is_split; 257 }; 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 struct msm_vfe_rdi_cfg { 260 uint8_t cid; 261 uint8_t frame_based; 262 }; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 struct msm_vfe_input_cfg { 265 union { 266 struct msm_vfe_pix_cfg pix_cfg; 267 struct msm_vfe_rdi_cfg rdi_cfg; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 } d; 270 enum msm_vfe_input_src input_src; 271 uint32_t input_pix_clk; 272 }; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 struct msm_vfe_fetch_eng_start { 275 uint32_t session_id; 276 uint32_t stream_id; 277 uint32_t buf_idx; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 uint8_t offline_mode; 280 uint32_t fd; 281 uint32_t buf_addr; 282 uint32_t frame_id; 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 }; 285 struct msm_vfe_axi_plane_cfg { 286 uint32_t output_width; 287 uint32_t output_height; 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 uint32_t output_stride; 290 uint32_t output_scan_lines; 291 uint32_t output_plane_format; 292 uint32_t plane_addr_offset; 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 uint8_t csid_src; 295 uint8_t rdi_cid; 296 }; 297 enum msm_stream_memory_input_t { 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 MEMORY_INPUT_DISABLED, 300 MEMORY_INPUT_ENABLED 301 }; 302 struct msm_vfe_axi_stream_request_cmd { 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 uint32_t session_id; 305 uint32_t stream_id; 306 uint32_t vt_enable; 307 uint32_t output_format; 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 enum msm_vfe_axi_stream_src stream_src; 310 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 311 uint32_t burst_count; 312 uint32_t hfr_mode; 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 uint8_t frame_base; 315 uint32_t init_frame_drop; 316 enum msm_vfe_frame_skip_pattern frame_skip_pattern; 317 uint8_t buf_divert; 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 uint32_t axi_stream_handle; 320 uint32_t controllable_output; 321 uint32_t burst_len; 322 enum msm_stream_memory_input_t memory_input; 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 }; 325 struct msm_vfe_axi_stream_release_cmd { 326 uint32_t stream_handle; 327 }; 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 enum msm_vfe_axi_stream_cmd { 330 STOP_STREAM, 331 START_STREAM, 332 STOP_IMMEDIATELY, 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 }; 335 struct msm_vfe_axi_stream_cfg_cmd { 336 uint8_t num_streams; 337 uint32_t stream_handle[VFE_AXI_SRC_MAX]; 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 enum msm_vfe_axi_stream_cmd cmd; 340 uint8_t sync_frame_id_src; 341 }; 342 enum msm_vfe_axi_stream_update_type { 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 ENABLE_STREAM_BUF_DIVERT, 345 DISABLE_STREAM_BUF_DIVERT, 346 UPDATE_STREAM_FRAMEDROP_PATTERN, 347 UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 UPDATE_STREAM_AXI_CONFIG, 350 UPDATE_STREAM_REQUEST_FRAMES, 351 UPDATE_STREAM_ADD_BUFQ, 352 UPDATE_STREAM_REMOVE_BUFQ, 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 UPDATE_STREAM_SW_FRAME_DROP, 355 }; 356 enum msm_vfe_iommu_type { 357 IOMMU_ATTACH, 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 IOMMU_DETACH, 360 }; 361 enum msm_vfe_buff_queue_id { 362 VFE_BUF_QUEUE_DEFAULT, 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 VFE_BUF_QUEUE_SHARED, 365 VFE_BUF_QUEUE_MAX, 366 }; 367 struct msm_vfe_axi_stream_cfg_update_info { 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 uint32_t stream_handle; 370 uint32_t output_format; 371 uint32_t user_stream_id; 372 uint32_t frame_id; 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 enum msm_vfe_frame_skip_pattern skip_pattern; 375 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; 376 struct msm_isp_sw_framskip sw_skip_info; 377 }; 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 struct msm_vfe_axi_halt_cmd { 380 uint32_t stop_camif; 381 uint32_t overflow_detected; 382 uint32_t blocking_halt; 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 }; 385 struct msm_vfe_axi_reset_cmd { 386 uint32_t blocking; 387 uint32_t frame_id; 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 }; 390 struct msm_vfe_axi_restart_cmd { 391 uint32_t enable_camif; 392 }; 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 struct msm_vfe_axi_stream_update_cmd { 395 uint32_t num_streams; 396 enum msm_vfe_axi_stream_update_type update_type; 397 struct msm_vfe_axi_stream_cfg_update_info update_info[MSM_ISP_STATS_MAX]; 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 }; 400 struct msm_vfe_smmu_attach_cmd { 401 uint32_t security_mode; 402 uint32_t iommu_attach_mode; 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 }; 405 struct msm_vfe_stats_stream_request_cmd { 406 uint32_t session_id; 407 uint32_t stream_id; 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 enum msm_isp_stats_type stats_type; 410 uint32_t composite_flag; 411 uint32_t framedrop_pattern; 412 uint32_t init_frame_drop; 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 uint32_t irq_subsample_pattern; 415 uint32_t buffer_offset; 416 uint32_t stream_handle; 417 }; 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 struct msm_vfe_stats_stream_release_cmd { 420 uint32_t stream_handle; 421 }; 422 struct msm_vfe_stats_stream_cfg_cmd { 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 uint8_t num_streams; 425 uint32_t stream_handle[MSM_ISP_STATS_MAX]; 426 uint8_t enable; 427 uint32_t stats_burst_len; 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 }; 430 enum msm_vfe_reg_cfg_type { 431 VFE_WRITE, 432 VFE_WRITE_MB, 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 VFE_READ, 435 VFE_CFG_MASK, 436 VFE_WRITE_DMI_16BIT, 437 VFE_WRITE_DMI_32BIT, 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 VFE_WRITE_DMI_64BIT, 440 VFE_READ_DMI_16BIT, 441 VFE_READ_DMI_32BIT, 442 VFE_READ_DMI_64BIT, 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 GET_MAX_CLK_RATE, 445 GET_CLK_RATES, 446 GET_ISP_ID, 447 VFE_HW_UPDATE_LOCK, 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 VFE_HW_UPDATE_UNLOCK, 450 SET_WM_UB_SIZE, 451 SET_UB_POLICY, 452 }; 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 struct msm_vfe_cfg_cmd2 { 455 uint16_t num_cfg; 456 uint16_t cmd_len; 457 void __user * cfg_data; 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 void __user * cfg_cmd; 460 }; 461 struct msm_vfe_cfg_cmd_list { 462 struct msm_vfe_cfg_cmd2 cfg_cmd; 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 struct msm_vfe_cfg_cmd_list * next; 465 uint32_t next_size; 466 }; 467 struct msm_vfe_reg_rw_info { 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 uint32_t reg_offset; 470 uint32_t cmd_data_offset; 471 uint32_t len; 472 }; 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 struct msm_vfe_reg_mask_info { 475 uint32_t reg_offset; 476 uint32_t mask; 477 uint32_t val; 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 }; 480 struct msm_vfe_reg_dmi_info { 481 uint32_t hi_tbl_offset; 482 uint32_t lo_tbl_offset; 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 uint32_t len; 485 }; 486 struct msm_vfe_reg_cfg_cmd { 487 union { 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 struct msm_vfe_reg_rw_info rw_info; 490 struct msm_vfe_reg_mask_info mask_info; 491 struct msm_vfe_reg_dmi_info dmi_info; 492 } u; 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 enum msm_vfe_reg_cfg_type cmd_type; 495 }; 496 enum vfe_sd_type { 497 VFE_SD_0 = 0, 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 VFE_SD_1, 500 VFE_SD_COMMON, 501 VFE_SD_MAX, 502 }; 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 #define MS_NUM_SLAVE_MAX 1 505 enum msm_vfe_dual_hw_type { 506 DUAL_NONE = 0, 507 DUAL_HW_VFE_SPLIT = 1, 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 DUAL_HW_MASTER_SLAVE = 2, 510 }; 511 enum msm_vfe_dual_hw_ms_type { 512 MS_TYPE_NONE, 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 MS_TYPE_MASTER, 515 MS_TYPE_SLAVE, 516 }; 517 struct msm_isp_set_dual_hw_ms_cmd { 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 uint8_t num_src; 520 enum msm_vfe_dual_hw_ms_type dual_hw_ms_type; 521 enum msm_vfe_input_src primary_intf; 522 enum msm_vfe_input_src input_src[VFE_SRC_MAX]; 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 uint32_t sof_delta_threshold; 525 }; 526 enum msm_isp_buf_type { 527 ISP_PRIVATE_BUF, 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 ISP_SHARE_BUF, 530 MAX_ISP_BUF_TYPE, 531 }; 532 struct msm_isp_unmap_buf_req { 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 uint32_t fd; 535 }; 536 struct msm_isp_buf_request { 537 uint32_t session_id; 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 uint32_t stream_id; 540 uint8_t num_buf; 541 uint32_t handle; 542 enum msm_isp_buf_type buf_type; 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 }; 545 struct msm_isp_qbuf_plane { 546 uint32_t addr; 547 uint32_t offset; 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 uint32_t length; 550 }; 551 struct msm_isp_qbuf_buffer { 552 struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 uint32_t num_planes; 555 }; 556 struct msm_isp_qbuf_info { 557 uint32_t handle; 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 int32_t buf_idx; 560 struct msm_isp_qbuf_buffer buffer; 561 uint32_t dirty_buf; 562 }; 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 struct msm_isp_clk_rates { 565 uint32_t svs_rate; 566 uint32_t nominal_rate; 567 uint32_t high_rate; 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 }; 570 struct msm_vfe_axi_src_state { 571 enum msm_vfe_input_src input_src; 572 uint32_t src_active; 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 uint32_t src_frame_id; 575 }; 576 enum msm_isp_event_mask_index { 577 ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0, 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 ISP_EVENT_MASK_INDEX_ERROR = 1, 580 ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2, 581 ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3, 582 ISP_EVENT_MASK_INDEX_REG_UPDATE = 4, 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 ISP_EVENT_MASK_INDEX_SOF = 5, 585 ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, 586 ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, 587 ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8, 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 ISP_EVENT_MASK_INDEX_BUF_DONE = 9, 590 ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10, 591 ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11, 592 ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12, 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 }; 595 #define ISP_EVENT_SUBS_MASK_NONE 0 596 #define ISP_EVENT_SUBS_MASK_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY) 597 #define ISP_EVENT_SUBS_MASK_ERROR (1 << ISP_EVENT_MASK_INDEX_ERROR) 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 #define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT) 600 #define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE) 601 #define ISP_EVENT_SUBS_MASK_REG_UPDATE (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE) 602 #define ISP_EVENT_SUBS_MASK_SOF (1 << ISP_EVENT_MASK_INDEX_SOF) 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 #define ISP_EVENT_SUBS_MASK_BUF_DIVERT (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT) 605 #define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY) 606 #define ISP_EVENT_SUBS_MASK_FE_READ_DONE (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) 607 #define ISP_EVENT_SUBS_MASK_BUF_DONE (1 << ISP_EVENT_MASK_INDEX_BUF_DONE) 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 #define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING) 610 #define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH) 611 #define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR) 612 enum msm_isp_event_idx { 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 ISP_REG_UPDATE = 0, 615 ISP_EPOCH_0 = 1, 616 ISP_EPOCH_1 = 2, 617 ISP_START_ACK = 3, 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 ISP_STOP_ACK = 4, 620 ISP_IRQ_VIOLATION = 5, 621 ISP_STATS_OVERFLOW = 6, 622 ISP_BUF_DONE = 7, 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 ISP_FE_RD_DONE = 8, 625 ISP_IOMMU_P_FAULT = 9, 626 ISP_ERROR = 10, 627 ISP_HW_FATAL_ERROR = 11, 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 ISP_PING_PONG_MISMATCH = 12, 630 ISP_REG_UPDATE_MISSING = 13, 631 ISP_BUF_FATAL_ERROR = 14, 632 ISP_EVENT_MAX = 15 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 }; 635 #define ISP_EVENT_OFFSET 8 636 #define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) 637 #define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 #define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) 640 #define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) 641 #define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) 642 #define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 #define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) 645 #define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) 646 #define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) 647 #define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 #define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) 650 #define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) 651 #define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR) 652 #define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 #define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) 655 #define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) 656 #define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) 657 #define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 #define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) 660 #define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) 661 #define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT) 662 #define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR) 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 #define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH) 665 #define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING) 666 #define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR) 667 #define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 struct msm_isp_buf_event { 670 uint32_t session_id; 671 uint32_t stream_id; 672 uint32_t handle; 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 uint32_t output_format; 675 int8_t buf_idx; 676 }; 677 struct msm_isp_fetch_eng_event { 678 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 uint32_t session_id; 680 uint32_t stream_id; 681 uint32_t handle; 682 uint32_t fd; 683 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 int8_t buf_idx; 685 int8_t offline_mode; 686 }; 687 struct msm_isp_stats_event { 688 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 uint32_t stats_mask; 690 uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; 691 }; 692 struct msm_isp_stream_ack { 693 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 uint32_t session_id; 695 uint32_t stream_id; 696 uint32_t handle; 697 }; 698 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 enum msm_vfe_error_type { 700 ISP_ERROR_NONE, 701 ISP_ERROR_CAMIF, 702 ISP_ERROR_BUS_OVERFLOW, 703 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 ISP_ERROR_RETURN_EMPTY_BUFFER, 705 ISP_ERROR_FRAME_ID_MISMATCH, 706 ISP_ERROR_MAX, 707 }; 708 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 struct msm_isp_error_info { 710 enum msm_vfe_error_type err_type; 711 uint32_t session_id; 712 uint32_t stream_id; 713 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 uint32_t stream_id_mask; 715 }; 716 struct msm_isp_ms_delta_info { 717 uint8_t num_delta_info; 718 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 uint32_t delta[MS_NUM_SLAVE_MAX]; 720 }; 721 struct msm_isp_output_info { 722 uint8_t regs_not_updated; 723 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724 uint16_t output_err_mask; 725 uint8_t stream_framedrop_mask; 726 uint16_t stats_framedrop_mask; 727 }; 728 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 struct msm_isp_sof_info { 730 uint8_t regs_not_updated; 731 uint16_t reg_update_fail_mask; 732 uint32_t stream_get_buf_fail_mask; 733 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734 uint16_t stats_get_buf_fail_mask; 735 struct msm_isp_ms_delta_info ms_delta_info; 736 }; 737 struct msm_isp_event_data { 738 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739 struct timeval timestamp; 740 struct timeval mono_timestamp; 741 uint32_t frame_id; 742 union { 743 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 struct msm_isp_stats_event stats; 745 struct msm_isp_buf_event buf_done; 746 struct msm_isp_fetch_eng_event fetch_done; 747 struct msm_isp_error_info error_info; 748 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749 struct msm_isp_output_info output_info; 750 struct msm_isp_sof_info sof_info; 751 } u; 752 }; 753 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754 #define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') 755 #define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') 756 #define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') 757 #define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') 758 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759 #define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') 760 #define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') 761 #define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') 762 #define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') 763 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764 #define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') 765 #define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') 766 #define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') 767 #define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') 768 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769 #define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') 770 #define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') 771 #define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') 772 #define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') 773 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774 #define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') 775 #define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') 776 #define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') 777 #define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') 778 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 #define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') 780 #define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') 781 #define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') 782 #define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') 783 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784 #define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') 785 #define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') 786 #define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') 787 #define VIDIOC_MSM_VFE_REG_CFG _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2) 788 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789 #define VIDIOC_MSM_ISP_REQUEST_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_isp_buf_request) 790 #define VIDIOC_MSM_ISP_ENQUEUE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_isp_qbuf_info) 791 #define VIDIOC_MSM_ISP_RELEASE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_isp_buf_request) 792 #define VIDIOC_MSM_ISP_REQUEST_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_vfe_axi_stream_request_cmd) 793 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794 #define VIDIOC_MSM_ISP_CFG_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_vfe_axi_stream_cfg_cmd) 795 #define VIDIOC_MSM_ISP_RELEASE_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_vfe_axi_stream_release_cmd) 796 #define VIDIOC_MSM_ISP_INPUT_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vfe_input_cfg) 797 #define VIDIOC_MSM_ISP_SET_SRC_STATE _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_vfe_axi_src_state) 798 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799 #define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_vfe_stats_stream_request_cmd) 800 #define VIDIOC_MSM_ISP_CFG_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_vfe_stats_stream_cfg_cmd) 801 #define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_vfe_stats_stream_release_cmd) 802 #define VIDIOC_MSM_ISP_REG_UPDATE_CMD _IOWR('V', BASE_VIDIOC_PRIVATE + 12, enum msm_vfe_input_src) 803 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804 #define VIDIOC_MSM_ISP_UPDATE_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_vfe_axi_stream_update_cmd) 805 #define VIDIOC_MSM_VFE_REG_LIST_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_vfe_cfg_cmd_list) 806 #define VIDIOC_MSM_ISP_SMMU_ATTACH _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_vfe_smmu_attach_cmd) 807 #define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_vfe_axi_stream_update_cmd) 808 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809 #define VIDIOC_MSM_ISP_AXI_HALT _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_vfe_axi_halt_cmd) 810 #define VIDIOC_MSM_ISP_AXI_RESET _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_vfe_axi_reset_cmd) 811 #define VIDIOC_MSM_ISP_AXI_RESTART _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_vfe_axi_restart_cmd) 812 #define VIDIOC_MSM_ISP_FETCH_ENG_START _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_vfe_fetch_eng_start) 813 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814 #define VIDIOC_MSM_ISP_DEQUEUE_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 21, struct msm_isp_qbuf_info) 815 #define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE _IOWR('V', BASE_VIDIOC_PRIVATE + 22, struct msm_isp_set_dual_hw_ms_cmd) 816 #define VIDIOC_MSM_ISP_MAP_BUF_START_FE _IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct msm_vfe_fetch_eng_start) 817 #define VIDIOC_MSM_ISP_UNMAP_BUF _IOWR('V', BASE_VIDIOC_PRIVATE + 24, struct msm_isp_unmap_buf_req) 818 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819 #endif 820 821