| /external/libopus/celt/arm/ |
| D | celt_pitch_xcorr_arm.s | 121 ADDS r12, r12, #2
140 ADDS r12, r12, #1
306 ADDS r2, r2, #4
388 ADDS r12, r12, #4
435 ADDS r1, r1, #2
461 ADDS r12, r12, #2
474 ADDS r12, r12, #1
500 ADDS r1, r1, #1
522 ADDS r12, r12, #2
529 ADDS r12, r12, #1
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| /external/valgrind/none/tests/mips32/ |
| D | FPUarithmetic.c | 6 ADDS, ADDD, enumerator
145 case ADDS: in arithmeticOperations()
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| /external/tremolo/Tremolo/ |
| D | bitwiseARM.s | 68 ADDS r10,r2,r1 @ r10= bitsLeftInSegment + bits (i.e.
151 ADDS r14,r14,r10 @ r14= length in bits-bits to skip
196 ADDS r10,r10,r2 @ r10= bits left in word after skip
200 ADDS r2,r2,r12,LSL #3 @ r2 = length in bits after advance
260 ADDS r10,r2,r1 @ r10= bitsLeftInSegment + bits (i.e.
391 ADDS r14,r14,r10 @ r14= length in bits-bits to skip
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| D | dpen.s | 102 ADDS r1, r1, #1 @ r1 = i-read++ (i-read<0 => i<read)
127 ADDS r1, r1, #1 @ r1 = i++
159 ADDS r1, r1, #1 @ r1 = i-read++ (i-read<0 => i<read)
185 ADDS r1, r1, #1 @ r1 = i++
217 ADDS r1, r1, #1 @ r1 = i-read++ (i-read<0 => i<read)
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| D | mdctLARM.s | 92 ADDS r1, r1, #16
160 ADDS r1, r1, #16
282 ADDS r0, r0, #8
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| D | mdctARM.s | 94 ADDS r1, r1, #16
162 ADDS r1, r1, #16
281 ADDS r0, r0, #8
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| /external/valgrind/VEX/priv/ |
| D | guest_mips_defs.h | 92 CVTLD, CVTSL, ADDS, ADDD, enumerator
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| D | guest_mips_helpers.c | 1303 case ADDS: in mips_dirtyhelper_calculate_FCSR_fp32()
1422 case ADDS: in mips_dirtyhelper_calculate_FCSR_fp64()
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 431 ADDS = ADD | AddSubSetFlagsBit, enumerator
438 V(ADDS), \
483 ADCS_w = AddSubWithCarryFixed | ADDS,
484 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
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| D | simulator-arm64.cc | 1395 case ADDS: { in AddSubHelper()
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| /external/valgrind/none/tests/mips64/ |
| D | fpu_arithmetic.c | 27 case ADDS: in arithmeticOperations()
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| D | macro_fpu.h | 4 ABSS=0, ABSD, ADDS, ADDD, enumerator
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 15 ADDS r0, r0, #5 // T1
17 ADDS r1, r1, #8 // T2
19 ADDS.W r1, r1, #8 // .w => T3
21 ADDS r8, r8, #8 // T3
43 ADDS r0, r2, r1 // ADDS has T1 narrow 3 operand
45 ADDS r2, r2, r1 // ADDS has T1 narrow 3 operand
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 458 ADDS = ADD | AddSubSetFlagsBit, enumerator
465 V(ADDS), \
510 ADCS_w = AddSubWithCarryFixed | ADDS,
511 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
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| D | simulator-a64.cc | 896 case ADDS: { in AddSubHelper()
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| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 882 X86_INTRINSIC_DATA(avx512_mask_padds_b_128, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
883 X86_INTRINSIC_DATA(avx512_mask_padds_b_256, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
884 X86_INTRINSIC_DATA(avx512_mask_padds_b_512, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
885 X86_INTRINSIC_DATA(avx512_mask_padds_w_128, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
886 X86_INTRINSIC_DATA(avx512_mask_padds_w_256, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
887 X86_INTRINSIC_DATA(avx512_mask_padds_w_512, INTR_TYPE_2OP_MASK, X86ISD::ADDS, 0),
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| D | X86ISelLowering.h | 227 ADDS, enumerator
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| D | X86InstrFragmentsSIMD.td | 256 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 56 ADDS, enumerator
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| D | AArch64ISelLowering.cpp | 852 case AArch64ISD::ADDS: return "AArch64ISD::ADDS"; in getTargetNodeName()
1201 Opcode = AArch64ISD::ADDS; in emitComparison()
1557 Opc = AArch64ISD::ADDS; in getAArch64XALUOOp()
1561 Opc = AArch64ISD::ADDS; in getAArch64XALUOOp()
1739 Opc = AArch64ISD::ADDS; in LowerADDC_ADDE_SUBC_SUBE()
9458 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS) in performBRCONDCombine()
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| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_T2_32.c | 91 #define ADDS 0x1800 macro
731 return push_inst16(compiler, ADDS | RD3(dst) | RN3(arg1) | RM3(arg2)); in emit_op_imm()
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| /external/llvm/test/MC/AArch64/ |
| D | arm64-aliases.s | 58 ; ADDS to WZR/XZR is a CMN
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3450 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3455 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3458 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 178 # ADDS
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| /external/vixl/doc/ |
| D | supported-instructions.md | 39 ### ADDS ### subsection
|