1VIXL Supported Instruction List 2=============================== 3 4This is a list of the AArch64 instructions supported by the VIXL assembler, 5disassembler and simulator. The simulator may not support all floating point 6operations to the precision required by AArch64 - please check the simulator 7source code for details. 8 9AArch64 integer instructions 10---------------------------- 11 12### ADC ### 13 14Add with carry bit. 15 16 void adc(const Register& rd, 17 const Register& rn, 18 const Operand& operand) 19 20 21### ADCS ### 22 23Add with carry bit and update status flags. 24 25 void adcs(const Register& rd, 26 const Register& rn, 27 const Operand& operand) 28 29 30### ADD ### 31 32Add. 33 34 void add(const Register& rd, 35 const Register& rn, 36 const Operand& operand) 37 38 39### ADDS ### 40 41Add and update status flags. 42 43 void adds(const Register& rd, 44 const Register& rn, 45 const Operand& operand) 46 47 48### ADR ### 49 50Calculate the address of a PC offset. 51 52 void adr(const Register& rd, int imm21) 53 54 55### ADR ### 56 57Calculate the address of a label. 58 59 void adr(const Register& rd, Label* label) 60 61 62### ADRP ### 63 64Calculate the page address of a PC offset. 65 66 void adrp(const Register& rd, int imm21) 67 68 69### ADRP ### 70 71Calculate the page address of a label. 72 73 void adrp(const Register& rd, Label* label) 74 75 76### AND ### 77 78Bitwise and (A & B). 79 80 void and_(const Register& rd, 81 const Register& rn, 82 const Operand& operand) 83 84 85### ANDS ### 86 87Bitwise and (A & B) and update status flags. 88 89 void ands(const Register& rd, 90 const Register& rn, 91 const Operand& operand) 92 93 94### ASR ### 95 96Arithmetic shift right. 97 98 void asr(const Register& rd, const Register& rn, unsigned shift) 99 100 101### ASRV ### 102 103Arithmetic shift right by variable. 104 105 void asrv(const Register& rd, const Register& rn, const Register& rm) 106 107 108### B ### 109 110Conditional branch to PC offset. 111 112 void b(int imm19, Condition cond) 113 114 115### B ### 116 117Conditional branch to label. 118 119 void b(Label* label, Condition cond) 120 121 122### B ### 123 124Unconditional branch to PC offset. 125 126 void b(int imm26) 127 128 129### B ### 130 131Unconditional branch to label. 132 133 void b(Label* label) 134 135 136### BFI ### 137 138Bitfield insert. 139 140 void bfi(const Register& rd, 141 const Register& rn, 142 unsigned lsb, 143 unsigned width) 144 145 146### BFM ### 147 148Bitfield move. 149 150 void bfm(const Register& rd, 151 const Register& rn, 152 unsigned immr, 153 unsigned imms) 154 155 156### BFXIL ### 157 158Bitfield extract and insert low. 159 160 void bfxil(const Register& rd, 161 const Register& rn, 162 unsigned lsb, 163 unsigned width) 164 165 166### BIC ### 167 168Bit clear (A & ~B). 169 170 void bic(const Register& rd, 171 const Register& rn, 172 const Operand& operand) 173 174 175### BICS ### 176 177Bit clear (A & ~B) and update status flags. 178 179 void bics(const Register& rd, 180 const Register& rn, 181 const Operand& operand) 182 183 184### BL ### 185 186Branch with link to PC offset. 187 188 void bl(int imm26) 189 190 191### BL ### 192 193Branch with link to label. 194 195 void bl(Label* label) 196 197 198### BLR ### 199 200Branch with link to register. 201 202 void blr(const Register& xn) 203 204 205### BR ### 206 207Branch to register. 208 209 void br(const Register& xn) 210 211 212### BRK ### 213 214Monitor debug-mode breakpoint. 215 216 void brk(int code) 217 218 219### CBNZ ### 220 221Compare and branch to PC offset if not zero. 222 223 void cbnz(const Register& rt, int imm19) 224 225 226### CBNZ ### 227 228Compare and branch to label if not zero. 229 230 void cbnz(const Register& rt, Label* label) 231 232 233### CBZ ### 234 235Compare and branch to PC offset if zero. 236 237 void cbz(const Register& rt, int imm19) 238 239 240### CBZ ### 241 242Compare and branch to label if zero. 243 244 void cbz(const Register& rt, Label* label) 245 246 247### CCMN ### 248 249Conditional compare negative. 250 251 void ccmn(const Register& rn, 252 const Operand& operand, 253 StatusFlags nzcv, 254 Condition cond) 255 256 257### CCMP ### 258 259Conditional compare. 260 261 void ccmp(const Register& rn, 262 const Operand& operand, 263 StatusFlags nzcv, 264 Condition cond) 265 266 267### CINC ### 268 269Conditional increment: rd = cond ? rn + 1 : rn. 270 271 void cinc(const Register& rd, const Register& rn, Condition cond) 272 273 274### CINV ### 275 276Conditional invert: rd = cond ? ~rn : rn. 277 278 void cinv(const Register& rd, const Register& rn, Condition cond) 279 280 281### CLREX ### 282 283Clear exclusive monitor. 284 285 void clrex(int imm4 = 0xf) 286 287 288### CLS ### 289 290Count leading sign bits. 291 292 void cls(const Register& rd, const Register& rn) 293 294 295### CLZ ### 296 297Count leading zeroes. 298 299 void clz(const Register& rd, const Register& rn) 300 301 302### CMN ### 303 304Compare negative. 305 306 void cmn(const Register& rn, const Operand& operand) 307 308 309### CMP ### 310 311Compare. 312 313 void cmp(const Register& rn, const Operand& operand) 314 315 316### CNEG ### 317 318Conditional negate: rd = cond ? -rn : rn. 319 320 void cneg(const Register& rd, const Register& rn, Condition cond) 321 322 323### CRC32B ### 324 325CRC-32 checksum from byte. 326 327 void crc32b(const Register& rd, 328 const Register& rn, 329 const Register& rm) 330 331 332### CRC32CB ### 333 334CRC-32 C checksum from byte. 335 336 void crc32cb(const Register& rd, 337 const Register& rn, 338 const Register& rm) 339 340 341### CRC32CH ### 342 343CRC-32 C checksum from half-word. 344 345 void crc32ch(const Register& rd, 346 const Register& rn, 347 const Register& rm) 348 349 350### CRC32CW ### 351 352CRC-32 C checksum from word. 353 354 void crc32cw(const Register& rd, 355 const Register& rn, 356 const Register& rm) 357 358 359### CRC32CX ### 360 361CRC-32C checksum from double word. 362 363 void crc32cx(const Register& rd, 364 const Register& rn, 365 const Register& rm) 366 367 368### CRC32H ### 369 370CRC-32 checksum from half-word. 371 372 void crc32h(const Register& rd, 373 const Register& rn, 374 const Register& rm) 375 376 377### CRC32W ### 378 379CRC-32 checksum from word. 380 381 void crc32w(const Register& rd, 382 const Register& rn, 383 const Register& rm) 384 385 386### CRC32X ### 387 388CRC-32 checksum from double word. 389 390 void crc32x(const Register& rd, 391 const Register& rn, 392 const Register& rm) 393 394 395### CSEL ### 396 397Conditional select: rd = cond ? rn : rm. 398 399 void csel(const Register& rd, 400 const Register& rn, 401 const Register& rm, 402 Condition cond) 403 404 405### CSET ### 406 407Conditional set: rd = cond ? 1 : 0. 408 409 void cset(const Register& rd, Condition cond) 410 411 412### CSETM ### 413 414Conditional set mask: rd = cond ? -1 : 0. 415 416 void csetm(const Register& rd, Condition cond) 417 418 419### CSINC ### 420 421Conditional select increment: rd = cond ? rn : rm + 1. 422 423 void csinc(const Register& rd, 424 const Register& rn, 425 const Register& rm, 426 Condition cond) 427 428 429### CSINV ### 430 431Conditional select inversion: rd = cond ? rn : ~rm. 432 433 void csinv(const Register& rd, 434 const Register& rn, 435 const Register& rm, 436 Condition cond) 437 438 439### CSNEG ### 440 441Conditional select negation: rd = cond ? rn : -rm. 442 443 void csneg(const Register& rd, 444 const Register& rn, 445 const Register& rm, 446 Condition cond) 447 448 449### DC ### 450 451System data cache operation. 452 453 void dc(DataCacheOp op, const Register& rt) 454 455 456### DMB ### 457 458Data memory barrier. 459 460 void dmb(BarrierDomain domain, BarrierType type) 461 462 463### DSB ### 464 465Data synchronization barrier. 466 467 void dsb(BarrierDomain domain, BarrierType type) 468 469 470### EON ### 471 472Bitwise enor/xnor (A ^ ~B). 473 474 void eon(const Register& rd, const Register& rn, const Operand& operand) 475 476 477### EOR ### 478 479Bitwise eor/xor (A ^ B). 480 481 void eor(const Register& rd, const Register& rn, const Operand& operand) 482 483 484### EXTR ### 485 486Extract. 487 488 void extr(const Register& rd, 489 const Register& rn, 490 const Register& rm, 491 unsigned lsb) 492 493 494### HINT ### 495 496System hint. 497 498 void hint(SystemHint code) 499 500 501### HLT ### 502 503Halting debug-mode breakpoint. 504 505 void hlt(int code) 506 507 508### IC ### 509 510System instruction cache operation. 511 512 void ic(InstructionCacheOp op, const Register& rt) 513 514 515### ISB ### 516 517Instruction synchronization barrier. 518 519 void isb() 520 521 522### LDAR ### 523 524Load-acquire register. 525 526 void ldar(const Register& rt, const MemOperand& src) 527 528 529### LDARB ### 530 531Load-acquire byte. 532 533 void ldarb(const Register& rt, const MemOperand& src) 534 535 536### LDARH ### 537 538Load-acquire half-word. 539 540 void ldarh(const Register& rt, const MemOperand& src) 541 542 543### LDAXP ### 544 545Load-acquire exclusive register pair. 546 547 void ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) 548 549 550### LDAXR ### 551 552Load-acquire exclusive register. 553 554 void ldaxr(const Register& rt, const MemOperand& src) 555 556 557### LDAXRB ### 558 559Load-acquire exclusive byte. 560 561 void ldaxrb(const Register& rt, const MemOperand& src) 562 563 564### LDAXRH ### 565 566Load-acquire exclusive half-word. 567 568 void ldaxrh(const Register& rt, const MemOperand& src) 569 570 571### LDNP ### 572 573Load integer or FP register pair, non-temporal. 574 575 void ldnp(const CPURegister& rt, const CPURegister& rt2, 576 const MemOperand& src) 577 578 579### LDP ### 580 581Load integer or FP register pair. 582 583 void ldp(const CPURegister& rt, const CPURegister& rt2, 584 const MemOperand& src) 585 586 587### LDPSW ### 588 589Load word pair with sign extension. 590 591 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src) 592 593 594### LDR ### 595 596Load integer or FP register from literal pool. 597 598 void ldr(const CPURegister& rt, RawLiteral* literal) 599 600 601### LDR ### 602 603Load integer or FP register from pc + imm19 << 2. 604 605 void ldr(const CPURegister& rt, int imm19) 606 607 608### LDR ### 609 610Load integer or FP register. 611 612 void ldr(const CPURegister& rt, const MemOperand& src, 613 LoadStoreScalingOption option = PreferScaledOffset) 614 615 616### LDRB ### 617 618Load byte. 619 620 void ldrb(const Register& rt, const MemOperand& src, 621 LoadStoreScalingOption option = PreferScaledOffset) 622 623 624### LDRH ### 625 626Load half-word. 627 628 void ldrh(const Register& rt, const MemOperand& src, 629 LoadStoreScalingOption option = PreferScaledOffset) 630 631 632### LDRSB ### 633 634Load byte with sign extension. 635 636 void ldrsb(const Register& rt, const MemOperand& src, 637 LoadStoreScalingOption option = PreferScaledOffset) 638 639 640### LDRSH ### 641 642Load half-word with sign extension. 643 644 void ldrsh(const Register& rt, const MemOperand& src, 645 LoadStoreScalingOption option = PreferScaledOffset) 646 647 648### LDRSW ### 649 650Load word with sign extension from literal pool. 651 652 void ldrsw(const Register& rt, RawLiteral* literal) 653 654 655### LDRSW ### 656 657Load word with sign extension from pc + imm19 << 2. 658 659 void ldrsw(const Register& rt, int imm19) 660 661 662### LDRSW ### 663 664Load word with sign extension. 665 666 void ldrsw(const Register& rt, const MemOperand& src, 667 LoadStoreScalingOption option = PreferScaledOffset) 668 669 670### LDUR ### 671 672Load integer or FP register (with unscaled offset). 673 674 void ldur(const CPURegister& rt, const MemOperand& src, 675 LoadStoreScalingOption option = PreferUnscaledOffset) 676 677 678### LDURB ### 679 680Load byte (with unscaled offset). 681 682 void ldurb(const Register& rt, const MemOperand& src, 683 LoadStoreScalingOption option = PreferUnscaledOffset) 684 685 686### LDURH ### 687 688Load half-word (with unscaled offset). 689 690 void ldurh(const Register& rt, const MemOperand& src, 691 LoadStoreScalingOption option = PreferUnscaledOffset) 692 693 694### LDURSB ### 695 696Load byte with sign extension (and unscaled offset). 697 698 void ldursb(const Register& rt, const MemOperand& src, 699 LoadStoreScalingOption option = PreferUnscaledOffset) 700 701 702### LDURSH ### 703 704Load half-word with sign extension (and unscaled offset). 705 706 void ldursh(const Register& rt, const MemOperand& src, 707 LoadStoreScalingOption option = PreferUnscaledOffset) 708 709 710### LDURSW ### 711 712Load word with sign extension. 713 714 void ldursw(const Register& rt, const MemOperand& src, 715 LoadStoreScalingOption option = PreferUnscaledOffset) 716 717 718### LDXP ### 719 720Load exclusive register pair. 721 722 void ldxp(const Register& rt, const Register& rt2, const MemOperand& src) 723 724 725### LDXR ### 726 727Load exclusive register. 728 729 void ldxr(const Register& rt, const MemOperand& src) 730 731 732### LDXRB ### 733 734Load exclusive byte. 735 736 void ldxrb(const Register& rt, const MemOperand& src) 737 738 739### LDXRH ### 740 741Load exclusive half-word. 742 743 void ldxrh(const Register& rt, const MemOperand& src) 744 745 746### LSL ### 747 748Logical shift left. 749 750 void lsl(const Register& rd, const Register& rn, unsigned shift) 751 752 753### LSLV ### 754 755Logical shift left by variable. 756 757 void lslv(const Register& rd, const Register& rn, const Register& rm) 758 759 760### LSR ### 761 762Logical shift right. 763 764 void lsr(const Register& rd, const Register& rn, unsigned shift) 765 766 767### LSRV ### 768 769Logical shift right by variable. 770 771 void lsrv(const Register& rd, const Register& rn, const Register& rm) 772 773 774### MADD ### 775 776Multiply and accumulate. 777 778 void madd(const Register& rd, 779 const Register& rn, 780 const Register& rm, 781 const Register& ra) 782 783 784### MNEG ### 785 786Negated multiply. 787 788 void mneg(const Register& rd, const Register& rn, const Register& rm) 789 790 791### MOV ### 792 793Move register to register. 794 795 void mov(const Register& rd, const Register& rn) 796 797 798### MOVK ### 799 800Move immediate and keep. 801 802 void movk(const Register& rd, uint64_t imm, int shift = -1) 803 804 805### MOVN ### 806 807Move inverted immediate. 808 809 void movn(const Register& rd, uint64_t imm, int shift = -1) 810 811 812### MOVZ ### 813 814Move immediate. 815 816 void movz(const Register& rd, uint64_t imm, int shift = -1) 817 818 819### MRS ### 820 821Move to register from system register. 822 823 void mrs(const Register& rt, SystemRegister sysreg) 824 825 826### MSR ### 827 828Move from register to system register. 829 830 void msr(SystemRegister sysreg, const Register& rt) 831 832 833### MSUB ### 834 835Multiply and subtract. 836 837 void msub(const Register& rd, 838 const Register& rn, 839 const Register& rm, 840 const Register& ra) 841 842 843### MUL ### 844 845Multiply. 846 847 void mul(const Register& rd, const Register& rn, const Register& rm) 848 849 850### MVN ### 851 852Move inverted operand to register. 853 854 void mvn(const Register& rd, const Operand& operand) 855 856 857### NEG ### 858 859Negate. 860 861 void neg(const Register& rd, 862 const Operand& operand) 863 864 865### NEGS ### 866 867Negate and update status flags. 868 869 void negs(const Register& rd, 870 const Operand& operand) 871 872 873### NGC ### 874 875Negate with carry bit. 876 877 void ngc(const Register& rd, 878 const Operand& operand) 879 880 881### NGCS ### 882 883Negate with carry bit and update status flags. 884 885 void ngcs(const Register& rd, 886 const Operand& operand) 887 888 889### NOP ### 890 891No-op. 892 893 void nop() 894 895 896### ORN ### 897 898Bitwise nor (A | ~B). 899 900 void orn(const Register& rd, const Register& rn, const Operand& operand) 901 902 903### ORR ### 904 905Bitwise or (A | B). 906 907 void orr(const Register& rd, const Register& rn, const Operand& operand) 908 909 910### PRFM ### 911 912Prefetch from pc + imm19 << 2. 913 914 void prfm(PrefetchOperation op, int imm19) 915 916 917### PRFM ### 918 919Prefetch memory in the literal pool. 920 921 void prfm(PrefetchOperation op, RawLiteral* literal) 922 923 924### PRFM ### 925 926Prefetch memory. 927 928 void prfm(PrefetchOperation op, const MemOperand& addr, 929 LoadStoreScalingOption option = PreferScaledOffset) 930 931 932### PRFUM ### 933 934Prefetch memory (with unscaled offset). 935 936 void prfum(PrefetchOperation op, const MemOperand& addr, 937 LoadStoreScalingOption option = PreferUnscaledOffset) 938 939 940### RBIT ### 941 942Bit reverse. 943 944 void rbit(const Register& rd, const Register& rn) 945 946 947### RET ### 948 949Branch to register with return hint. 950 951 void ret(const Register& xn = lr) 952 953 954### REV ### 955 956Reverse bytes. 957 958 void rev(const Register& rd, const Register& rn) 959 960 961### REV16 ### 962 963Reverse bytes in 16-bit half words. 964 965 void rev16(const Register& rd, const Register& rn) 966 967 968### REV32 ### 969 970Reverse bytes in 32-bit words. 971 972 void rev32(const Register& rd, const Register& rn) 973 974 975### ROR ### 976 977Rotate right. 978 979 void ror(const Register& rd, const Register& rs, unsigned shift) 980 981 982### RORV ### 983 984Rotate right by variable. 985 986 void rorv(const Register& rd, const Register& rn, const Register& rm) 987 988 989### SBC ### 990 991Subtract with carry bit. 992 993 void sbc(const Register& rd, 994 const Register& rn, 995 const Operand& operand) 996 997 998### SBCS ### 999 1000Subtract with carry bit and update status flags. 1001 1002 void sbcs(const Register& rd, 1003 const Register& rn, 1004 const Operand& operand) 1005 1006 1007### SBFIZ ### 1008 1009Signed bitfield insert with zero at right. 1010 1011 void sbfiz(const Register& rd, 1012 const Register& rn, 1013 unsigned lsb, 1014 unsigned width) 1015 1016 1017### SBFM ### 1018 1019Signed bitfield move. 1020 1021 void sbfm(const Register& rd, 1022 const Register& rn, 1023 unsigned immr, 1024 unsigned imms) 1025 1026 1027### SBFX ### 1028 1029Signed bitfield extract. 1030 1031 void sbfx(const Register& rd, 1032 const Register& rn, 1033 unsigned lsb, 1034 unsigned width) 1035 1036 1037### SDIV ### 1038 1039Signed integer divide. 1040 1041 void sdiv(const Register& rd, const Register& rn, const Register& rm) 1042 1043 1044### SMADDL ### 1045 1046Signed long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 1047 1048 void smaddl(const Register& rd, 1049 const Register& rn, 1050 const Register& rm, 1051 const Register& ra) 1052 1053 1054### SMSUBL ### 1055 1056Signed long multiply and subtract: 64 - (32 x 32) -> 64-bit. 1057 1058 void smsubl(const Register& rd, 1059 const Register& rn, 1060 const Register& rm, 1061 const Register& ra) 1062 1063 1064### SMULH ### 1065 1066Signed multiply high: 64 x 64 -> 64-bit <127:64>. 1067 1068 void smulh(const Register& xd, const Register& xn, const Register& xm) 1069 1070 1071### SMULL ### 1072 1073Signed long multiply: 32 x 32 -> 64-bit. 1074 1075 void smull(const Register& rd, const Register& rn, const Register& rm) 1076 1077 1078### STLR ### 1079 1080Store-release register. 1081 1082 void stlr(const Register& rt, const MemOperand& dst) 1083 1084 1085### STLRB ### 1086 1087Store-release byte. 1088 1089 void stlrb(const Register& rt, const MemOperand& dst) 1090 1091 1092### STLRH ### 1093 1094Store-release half-word. 1095 1096 void stlrh(const Register& rt, const MemOperand& dst) 1097 1098 1099### STLXP ### 1100 1101Store-release exclusive register pair. 1102 1103 void stlxp(const Register& rs, 1104 const Register& rt, 1105 const Register& rt2, 1106 const MemOperand& dst) 1107 1108 1109### STLXR ### 1110 1111Store-release exclusive register. 1112 1113 void stlxr(const Register& rs, const Register& rt, const MemOperand& dst) 1114 1115 1116### STLXRB ### 1117 1118Store-release exclusive byte. 1119 1120 void stlxrb(const Register& rs, const Register& rt, const MemOperand& dst) 1121 1122 1123### STLXRH ### 1124 1125Store-release exclusive half-word. 1126 1127 void stlxrh(const Register& rs, const Register& rt, const MemOperand& dst) 1128 1129 1130### STNP ### 1131 1132Store integer or FP register pair, non-temporal. 1133 1134 void stnp(const CPURegister& rt, const CPURegister& rt2, 1135 const MemOperand& dst) 1136 1137 1138### STP ### 1139 1140Store integer or FP register pair. 1141 1142 void stp(const CPURegister& rt, const CPURegister& rt2, 1143 const MemOperand& dst) 1144 1145 1146### STR ### 1147 1148Store integer or FP register. 1149 1150 void str(const CPURegister& rt, const MemOperand& dst, 1151 LoadStoreScalingOption option = PreferScaledOffset) 1152 1153 1154### STRB ### 1155 1156Store byte. 1157 1158 void strb(const Register& rt, const MemOperand& dst, 1159 LoadStoreScalingOption option = PreferScaledOffset) 1160 1161 1162### STRH ### 1163 1164Store half-word. 1165 1166 void strh(const Register& rt, const MemOperand& dst, 1167 LoadStoreScalingOption option = PreferScaledOffset) 1168 1169 1170### STUR ### 1171 1172Store integer or FP register (with unscaled offset). 1173 1174 void stur(const CPURegister& rt, const MemOperand& src, 1175 LoadStoreScalingOption option = PreferUnscaledOffset) 1176 1177 1178### STURB ### 1179 1180Store byte (with unscaled offset). 1181 1182 void sturb(const Register& rt, const MemOperand& dst, 1183 LoadStoreScalingOption option = PreferUnscaledOffset) 1184 1185 1186### STURH ### 1187 1188Store half-word (with unscaled offset). 1189 1190 void sturh(const Register& rt, const MemOperand& dst, 1191 LoadStoreScalingOption option = PreferUnscaledOffset) 1192 1193 1194### STXP ### 1195 1196Store exclusive register pair. 1197 1198 void stxp(const Register& rs, 1199 const Register& rt, 1200 const Register& rt2, 1201 const MemOperand& dst) 1202 1203 1204### STXR ### 1205 1206Store exclusive register. 1207 1208 void stxr(const Register& rs, const Register& rt, const MemOperand& dst) 1209 1210 1211### STXRB ### 1212 1213Store exclusive byte. 1214 1215 void stxrb(const Register& rs, const Register& rt, const MemOperand& dst) 1216 1217 1218### STXRH ### 1219 1220Store exclusive half-word. 1221 1222 void stxrh(const Register& rs, const Register& rt, const MemOperand& dst) 1223 1224 1225### SUB ### 1226 1227Subtract. 1228 1229 void sub(const Register& rd, 1230 const Register& rn, 1231 const Operand& operand) 1232 1233 1234### SUBS ### 1235 1236Subtract and update status flags. 1237 1238 void subs(const Register& rd, 1239 const Register& rn, 1240 const Operand& operand) 1241 1242 1243### SVC ### 1244 1245Generate exception targeting EL1. 1246 1247 void svc(int code) 1248 1249 1250### SXTB ### 1251 1252Signed extend byte. 1253 1254 void sxtb(const Register& rd, const Register& rn) 1255 1256 1257### SXTH ### 1258 1259Signed extend halfword. 1260 1261 void sxth(const Register& rd, const Register& rn) 1262 1263 1264### SXTW ### 1265 1266Signed extend word. 1267 1268 void sxtw(const Register& rd, const Register& rn) 1269 1270 1271### SYS ### 1272 1273System instruction with pre-encoded op (op1:crn:crm:op2). 1274 1275 void sys(int op, const Register& rt = xzr) 1276 1277 1278### SYS ### 1279 1280System instruction. 1281 1282 void sys(int op1, int crn, int crm, int op2, const Register& rt = xzr) 1283 1284 1285### TBNZ ### 1286 1287Test bit and branch to PC offset if not zero. 1288 1289 void tbnz(const Register& rt, unsigned bit_pos, int imm14) 1290 1291 1292### TBNZ ### 1293 1294Test bit and branch to label if not zero. 1295 1296 void tbnz(const Register& rt, unsigned bit_pos, Label* label) 1297 1298 1299### TBZ ### 1300 1301Test bit and branch to PC offset if zero. 1302 1303 void tbz(const Register& rt, unsigned bit_pos, int imm14) 1304 1305 1306### TBZ ### 1307 1308Test bit and branch to label if zero. 1309 1310 void tbz(const Register& rt, unsigned bit_pos, Label* label) 1311 1312 1313### TST ### 1314 1315Bit test and set flags. 1316 1317 void tst(const Register& rn, const Operand& operand) 1318 1319 1320### UBFIZ ### 1321 1322Unsigned bitfield insert with zero at right. 1323 1324 void ubfiz(const Register& rd, 1325 const Register& rn, 1326 unsigned lsb, 1327 unsigned width) 1328 1329 1330### UBFM ### 1331 1332Unsigned bitfield move. 1333 1334 void ubfm(const Register& rd, 1335 const Register& rn, 1336 unsigned immr, 1337 unsigned imms) 1338 1339 1340### UBFX ### 1341 1342Unsigned bitfield extract. 1343 1344 void ubfx(const Register& rd, 1345 const Register& rn, 1346 unsigned lsb, 1347 unsigned width) 1348 1349 1350### UDIV ### 1351 1352Unsigned integer divide. 1353 1354 void udiv(const Register& rd, const Register& rn, const Register& rm) 1355 1356 1357### UMADDL ### 1358 1359Unsigned long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 1360 1361 void umaddl(const Register& rd, 1362 const Register& rn, 1363 const Register& rm, 1364 const Register& ra) 1365 1366 1367### UMSUBL ### 1368 1369Unsigned long multiply and subtract: 64 - (32 x 32) -> 64-bit. 1370 1371 void umsubl(const Register& rd, 1372 const Register& rn, 1373 const Register& rm, 1374 const Register& ra) 1375 1376 1377### UMULH ### 1378 1379Unsigned multiply high: 64 x 64 -> 64-bit <127:64>. 1380 1381 void umulh(const Register& xd, 1382 const Register& xn, 1383 const Register& xm) 1384 1385 1386### UMULL ### 1387 1388Unsigned long multiply: 32 x 32 -> 64-bit. 1389 1390 void umull(const Register& rd, 1391 const Register& rn, 1392 const Register& rm) 1393 1394 1395### UXTB ### 1396 1397Unsigned extend byte. 1398 1399 void uxtb(const Register& rd, const Register& rn) 1400 1401 1402### UXTH ### 1403 1404Unsigned extend halfword. 1405 1406 void uxth(const Register& rd, const Register& rn) 1407 1408 1409### UXTW ### 1410 1411Unsigned extend word. 1412 1413 void uxtw(const Register& rd, const Register& rn) 1414 1415 1416 1417AArch64 floating point and NEON instructions 1418-------------------------------------------- 1419 1420### ABS ### 1421 1422Absolute value. 1423 1424 void abs(const VRegister& vd, 1425 const VRegister& vn) 1426 1427 1428### ADD ### 1429 1430Add. 1431 1432 void add(const VRegister& vd, 1433 const VRegister& vn, 1434 const VRegister& vm) 1435 1436 1437### ADDHN ### 1438 1439Add narrow returning high half. 1440 1441 void addhn(const VRegister& vd, 1442 const VRegister& vn, 1443 const VRegister& vm) 1444 1445 1446### ADDHN2 ### 1447 1448Add narrow returning high half (second part). 1449 1450 void addhn2(const VRegister& vd, 1451 const VRegister& vn, 1452 const VRegister& vm) 1453 1454 1455### ADDP ### 1456 1457Add pair of elements scalar. 1458 1459 void addp(const VRegister& vd, 1460 const VRegister& vn) 1461 1462 1463### ADDP ### 1464 1465Add pairwise. 1466 1467 void addp(const VRegister& vd, 1468 const VRegister& vn, 1469 const VRegister& vm) 1470 1471 1472### ADDV ### 1473 1474Add across vector. 1475 1476 void addv(const VRegister& vd, 1477 const VRegister& vn) 1478 1479 1480### AND ### 1481 1482Bitwise and. 1483 1484 void and_(const VRegister& vd, 1485 const VRegister& vn, 1486 const VRegister& vm) 1487 1488 1489### BIC ### 1490 1491Bit clear immediate. 1492 1493 void bic(const VRegister& vd, 1494 const int imm8, 1495 const int left_shift = 0) 1496 1497 1498### BIC ### 1499 1500Bit clear. 1501 1502 void bic(const VRegister& vd, 1503 const VRegister& vn, 1504 const VRegister& vm) 1505 1506 1507### BIF ### 1508 1509Bitwise insert if false. 1510 1511 void bif(const VRegister& vd, 1512 const VRegister& vn, 1513 const VRegister& vm) 1514 1515 1516### BIT ### 1517 1518Bitwise insert if true. 1519 1520 void bit(const VRegister& vd, 1521 const VRegister& vn, 1522 const VRegister& vm) 1523 1524 1525### BSL ### 1526 1527Bitwise select. 1528 1529 void bsl(const VRegister& vd, 1530 const VRegister& vn, 1531 const VRegister& vm) 1532 1533 1534### CLS ### 1535 1536Count leading sign bits. 1537 1538 void cls(const VRegister& vd, 1539 const VRegister& vn) 1540 1541 1542### CLZ ### 1543 1544Count leading zero bits (vector). 1545 1546 void clz(const VRegister& vd, 1547 const VRegister& vn) 1548 1549 1550### CMEQ ### 1551 1552Compare bitwise to zero. 1553 1554 void cmeq(const VRegister& vd, 1555 const VRegister& vn, 1556 int value) 1557 1558 1559### CMEQ ### 1560 1561Compare equal. 1562 1563 void cmeq(const VRegister& vd, 1564 const VRegister& vn, 1565 const VRegister& vm) 1566 1567 1568### CMGE ### 1569 1570Compare signed greater than or equal to zero. 1571 1572 void cmge(const VRegister& vd, 1573 const VRegister& vn, 1574 int value) 1575 1576 1577### CMGE ### 1578 1579Compare signed greater than or equal. 1580 1581 void cmge(const VRegister& vd, 1582 const VRegister& vn, 1583 const VRegister& vm) 1584 1585 1586### CMGT ### 1587 1588Compare signed greater than zero. 1589 1590 void cmgt(const VRegister& vd, 1591 const VRegister& vn, 1592 int value) 1593 1594 1595### CMGT ### 1596 1597Compare signed greater than. 1598 1599 void cmgt(const VRegister& vd, 1600 const VRegister& vn, 1601 const VRegister& vm) 1602 1603 1604### CMHI ### 1605 1606Compare unsigned higher. 1607 1608 void cmhi(const VRegister& vd, 1609 const VRegister& vn, 1610 const VRegister& vm) 1611 1612 1613### CMHS ### 1614 1615Compare unsigned higher or same. 1616 1617 void cmhs(const VRegister& vd, 1618 const VRegister& vn, 1619 const VRegister& vm) 1620 1621 1622### CMLE ### 1623 1624Compare signed less than or equal to zero. 1625 1626 void cmle(const VRegister& vd, 1627 const VRegister& vn, 1628 int value) 1629 1630 1631### CMLT ### 1632 1633Compare signed less than zero. 1634 1635 void cmlt(const VRegister& vd, 1636 const VRegister& vn, 1637 int value) 1638 1639 1640### CMTST ### 1641 1642Compare bitwise test bits nonzero. 1643 1644 void cmtst(const VRegister& vd, 1645 const VRegister& vn, 1646 const VRegister& vm) 1647 1648 1649### CNT ### 1650 1651Population count per byte. 1652 1653 void cnt(const VRegister& vd, 1654 const VRegister& vn) 1655 1656 1657### DUP ### 1658 1659Duplicate general-purpose register to vector. 1660 1661 void dup(const VRegister& vd, 1662 const Register& rn) 1663 1664 1665### DUP ### 1666 1667Duplicate vector element to vector or scalar. 1668 1669 void dup(const VRegister& vd, 1670 const VRegister& vn, 1671 int vn_index) 1672 1673 1674### EOR ### 1675 1676Bitwise eor. 1677 1678 void eor(const VRegister& vd, 1679 const VRegister& vn, 1680 const VRegister& vm) 1681 1682 1683### EXT ### 1684 1685Extract vector from pair of vectors. 1686 1687 void ext(const VRegister& vd, 1688 const VRegister& vn, 1689 const VRegister& vm, 1690 int index) 1691 1692 1693### FABD ### 1694 1695FP absolute difference. 1696 1697 void fabd(const VRegister& vd, 1698 const VRegister& vn, 1699 const VRegister& vm) 1700 1701 1702### FABS ### 1703 1704FP absolute. 1705 1706 void fabs(const VRegister& vd, const VRegister& vn) 1707 1708 1709### FACGE ### 1710 1711FP absolute greater than or equal. 1712 1713 void facge(const VRegister& vd, 1714 const VRegister& vn, 1715 const VRegister& vm) 1716 1717 1718### FACGT ### 1719 1720FP absolute greater than. 1721 1722 void facgt(const VRegister& vd, 1723 const VRegister& vn, 1724 const VRegister& vm) 1725 1726 1727### FADD ### 1728 1729FP add. 1730 1731 void fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1732 1733 1734### FADDP ### 1735 1736FP pairwise add scalar. 1737 1738 void faddp(const VRegister& vd, 1739 const VRegister& vn) 1740 1741 1742### FADDP ### 1743 1744FP pairwise add vector. 1745 1746 void faddp(const VRegister& vd, 1747 const VRegister& vn, 1748 const VRegister& vm) 1749 1750 1751### FCCMP ### 1752 1753FP conditional compare. 1754 1755 void fccmp(const VRegister& vn, 1756 const VRegister& vm, 1757 StatusFlags nzcv, 1758 Condition cond) 1759 1760 1761### FCCMPE ### 1762 1763FP conditional signaling compare. 1764 1765 void fccmpe(const VRegister& vn, 1766 const VRegister& vm, 1767 StatusFlags nzcv, 1768 Condition cond) 1769 1770 1771### FCMEQ ### 1772 1773FP compare equal to zero. 1774 1775 void fcmeq(const VRegister& vd, 1776 const VRegister& vn, 1777 double imm) 1778 1779 1780### FCMEQ ### 1781 1782FP compare equal. 1783 1784 void fcmeq(const VRegister& vd, 1785 const VRegister& vn, 1786 const VRegister& vm) 1787 1788 1789### FCMGE ### 1790 1791FP greater than or equal to zero. 1792 1793 void fcmge(const VRegister& vd, 1794 const VRegister& vn, 1795 double imm) 1796 1797 1798### FCMGE ### 1799 1800FP greater than or equal. 1801 1802 void fcmge(const VRegister& vd, 1803 const VRegister& vn, 1804 const VRegister& vm) 1805 1806 1807### FCMGT ### 1808 1809FP greater than zero. 1810 1811 void fcmgt(const VRegister& vd, 1812 const VRegister& vn, 1813 double imm) 1814 1815 1816### FCMGT ### 1817 1818FP greater than. 1819 1820 void fcmgt(const VRegister& vd, 1821 const VRegister& vn, 1822 const VRegister& vm) 1823 1824 1825### FCMLE ### 1826 1827FP less than or equal to zero. 1828 1829 void fcmle(const VRegister& vd, 1830 const VRegister& vn, 1831 double imm) 1832 1833 1834### FCMLT ### 1835 1836FP less than to zero. 1837 1838 void fcmlt(const VRegister& vd, 1839 const VRegister& vn, 1840 double imm) 1841 1842 1843### FCMP ### 1844 1845FP compare immediate. 1846 1847 void fcmp(const VRegister& vn, double value) 1848 1849 1850### FCMP ### 1851 1852FP compare registers. 1853 1854 void fcmp(const VRegister& vn, const VRegister& vm) 1855 1856 1857### FCMPE ### 1858 1859FP signaling compare immediate. 1860 1861 void fcmpe(const VRegister& vn, double value) 1862 1863 1864### FCMPE ### 1865 1866FP signaling compare registers. 1867 1868 void fcmpe(const VRegister& vn, const VRegister& vm) 1869 1870 1871### FCSEL ### 1872 1873FP conditional select. 1874 1875 void fcsel(const VRegister& vd, 1876 const VRegister& vn, 1877 const VRegister& vm, 1878 Condition cond) 1879 1880 1881### FCVT ### 1882 1883FP convert between precisions. 1884 1885 void fcvt(const VRegister& vd, const VRegister& vn) 1886 1887 1888### FCVTAS ### 1889 1890FP convert to signed integer, nearest with ties to away. 1891 1892 void fcvtas(const Register& rd, const VRegister& vn) 1893 1894 1895### FCVTAS ### 1896 1897FP convert to signed integer, nearest with ties to away. 1898 1899 void fcvtas(const VRegister& vd, const VRegister& vn) 1900 1901 1902### FCVTAU ### 1903 1904FP convert to unsigned integer, nearest with ties to away. 1905 1906 void fcvtau(const Register& rd, const VRegister& vn) 1907 1908 1909### FCVTAU ### 1910 1911FP convert to unsigned integer, nearest with ties to away. 1912 1913 void fcvtau(const VRegister& vd, const VRegister& vn) 1914 1915 1916### FCVTL ### 1917 1918FP convert to higher precision. 1919 1920 void fcvtl(const VRegister& vd, const VRegister& vn) 1921 1922 1923### FCVTL2 ### 1924 1925FP convert to higher precision (second part). 1926 1927 void fcvtl2(const VRegister& vd, const VRegister& vn) 1928 1929 1930### FCVTMS ### 1931 1932FP convert to signed integer, round towards -infinity. 1933 1934 void fcvtms(const Register& rd, const VRegister& vn) 1935 1936 1937### FCVTMS ### 1938 1939FP convert to signed integer, round towards -infinity. 1940 1941 void fcvtms(const VRegister& vd, const VRegister& vn) 1942 1943 1944### FCVTMU ### 1945 1946FP convert to unsigned integer, round towards -infinity. 1947 1948 void fcvtmu(const Register& rd, const VRegister& vn) 1949 1950 1951### FCVTMU ### 1952 1953FP convert to unsigned integer, round towards -infinity. 1954 1955 void fcvtmu(const VRegister& vd, const VRegister& vn) 1956 1957 1958### FCVTN ### 1959 1960FP convert to lower precision. 1961 1962 void fcvtn(const VRegister& vd, const VRegister& vn) 1963 1964 1965### FCVTN2 ### 1966 1967FP convert to lower prevision (second part). 1968 1969 void fcvtn2(const VRegister& vd, const VRegister& vn) 1970 1971 1972### FCVTNS ### 1973 1974FP convert to signed integer, nearest with ties to even. 1975 1976 void fcvtns(const Register& rd, const VRegister& vn) 1977 1978 1979### FCVTNS ### 1980 1981FP convert to signed integer, nearest with ties to even. 1982 1983 void fcvtns(const VRegister& rd, const VRegister& vn) 1984 1985 1986### FCVTNU ### 1987 1988FP convert to unsigned integer, nearest with ties to even. 1989 1990 void fcvtnu(const Register& rd, const VRegister& vn) 1991 1992 1993### FCVTNU ### 1994 1995FP convert to unsigned integer, nearest with ties to even. 1996 1997 void fcvtnu(const VRegister& rd, const VRegister& vn) 1998 1999 2000### FCVTPS ### 2001 2002FP convert to signed integer, round towards +infinity. 2003 2004 void fcvtps(const Register& rd, const VRegister& vn) 2005 2006 2007### FCVTPS ### 2008 2009FP convert to signed integer, round towards +infinity. 2010 2011 void fcvtps(const VRegister& vd, const VRegister& vn) 2012 2013 2014### FCVTPU ### 2015 2016FP convert to unsigned integer, round towards +infinity. 2017 2018 void fcvtpu(const Register& rd, const VRegister& vn) 2019 2020 2021### FCVTPU ### 2022 2023FP convert to unsigned integer, round towards +infinity. 2024 2025 void fcvtpu(const VRegister& vd, const VRegister& vn) 2026 2027 2028### FCVTXN ### 2029 2030FP convert to lower precision, rounding to odd. 2031 2032 void fcvtxn(const VRegister& vd, const VRegister& vn) 2033 2034 2035### FCVTXN2 ### 2036 2037FP convert to lower precision, rounding to odd (second part). 2038 2039 void fcvtxn2(const VRegister& vd, const VRegister& vn) 2040 2041 2042### FCVTZS ### 2043 2044FP convert to signed integer or fixed-point, round towards zero. 2045 2046 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0) 2047 2048 2049### FCVTZS ### 2050 2051FP convert to signed integer or fixed-point, round towards zero. 2052 2053 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) 2054 2055 2056### FCVTZU ### 2057 2058FP convert to unsigned integer or fixed-point, round towards zero. 2059 2060 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0) 2061 2062 2063### FCVTZU ### 2064 2065FP convert to unsigned integer or fixed-point, round towards zero. 2066 2067 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) 2068 2069 2070### FDIV ### 2071 2072FP divide. 2073 2074 void fdiv(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2075 2076 2077### FMADD ### 2078 2079FP fused multiply-add. 2080 2081 void fmadd(const VRegister& vd, 2082 const VRegister& vn, 2083 const VRegister& vm, 2084 const VRegister& va) 2085 2086 2087### FMAX ### 2088 2089FP maximum. 2090 2091 void fmax(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2092 2093 2094### FMAXNM ### 2095 2096FP maximum number. 2097 2098 void fmaxnm(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2099 2100 2101### FMAXNMP ### 2102 2103FP pairwise maximum number scalar. 2104 2105 void fmaxnmp(const VRegister& vd, 2106 const VRegister& vn) 2107 2108 2109### FMAXNMP ### 2110 2111FP pairwise maximum number vector. 2112 2113 void fmaxnmp(const VRegister& vd, 2114 const VRegister& vn, 2115 const VRegister& vm) 2116 2117 2118### FMAXNMV ### 2119 2120FP maximum number across vector. 2121 2122 void fmaxnmv(const VRegister& vd, 2123 const VRegister& vn) 2124 2125 2126### FMAXP ### 2127 2128FP pairwise maximum scalar. 2129 2130 void fmaxp(const VRegister& vd, 2131 const VRegister& vn) 2132 2133 2134### FMAXP ### 2135 2136FP pairwise maximum vector. 2137 2138 void fmaxp(const VRegister& vd, 2139 const VRegister& vn, 2140 const VRegister& vm) 2141 2142 2143### FMAXV ### 2144 2145FP maximum across vector. 2146 2147 void fmaxv(const VRegister& vd, 2148 const VRegister& vn) 2149 2150 2151### FMIN ### 2152 2153FP minimum. 2154 2155 void fmin(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2156 2157 2158### FMINNM ### 2159 2160FP minimum number. 2161 2162 void fminnm(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2163 2164 2165### FMINNMP ### 2166 2167FP pairwise minimum number scalar. 2168 2169 void fminnmp(const VRegister& vd, 2170 const VRegister& vn) 2171 2172 2173### FMINNMP ### 2174 2175FP pairwise minimum number vector. 2176 2177 void fminnmp(const VRegister& vd, 2178 const VRegister& vn, 2179 const VRegister& vm) 2180 2181 2182### FMINNMV ### 2183 2184FP minimum number across vector. 2185 2186 void fminnmv(const VRegister& vd, 2187 const VRegister& vn) 2188 2189 2190### FMINP ### 2191 2192FP pairwise minimum scalar. 2193 2194 void fminp(const VRegister& vd, 2195 const VRegister& vn) 2196 2197 2198### FMINP ### 2199 2200FP pairwise minimum vector. 2201 2202 void fminp(const VRegister& vd, 2203 const VRegister& vn, 2204 const VRegister& vm) 2205 2206 2207### FMINV ### 2208 2209FP minimum across vector. 2210 2211 void fminv(const VRegister& vd, 2212 const VRegister& vn) 2213 2214 2215### FMLA ### 2216 2217FP fused multiply-add to accumulator by element. 2218 2219 void fmla(const VRegister& vd, 2220 const VRegister& vn, 2221 const VRegister& vm, 2222 int vm_index) 2223 2224 2225### FMLA ### 2226 2227FP vector multiply accumulate. 2228 2229 void fmla(const VRegister& vd, 2230 const VRegister& vn, 2231 const VRegister& vm) 2232 2233 2234### FMLS ### 2235 2236FP fused multiply-sub from accumulator by element. 2237 2238 void fmls(const VRegister& vd, 2239 const VRegister& vn, 2240 const VRegister& vm, 2241 int vm_index) 2242 2243 2244### FMLS ### 2245 2246FP vector multiply subtract. 2247 2248 void fmls(const VRegister& vd, 2249 const VRegister& vn, 2250 const VRegister& vm) 2251 2252 2253### FMOV ### 2254 2255Move 64-bit register to top half of 128-bit FP register. 2256 2257 void fmov(const VRegister& vd, int index, const Register& rn) 2258 2259 2260### FMOV ### 2261 2262Move FP register to FP register. 2263 2264 void fmov(const VRegister& vd, const VRegister& fn) 2265 2266 2267### FMOV ### 2268 2269Move FP register to register. 2270 2271 void fmov(const Register& rd, const VRegister& fn) 2272 2273 2274### FMOV ### 2275 2276Move double precision immediate to FP register. 2277 2278 void fmov(const VRegister& vd, double imm) 2279 2280 2281### FMOV ### 2282 2283Move register to FP register. 2284 2285 void fmov(const VRegister& vd, const Register& rn) 2286 2287 2288### FMOV ### 2289 2290Move single precision immediate to FP register. 2291 2292 void fmov(const VRegister& vd, float imm) 2293 2294 2295### FMOV ### 2296 2297Move top half of 128-bit FP register to 64-bit register. 2298 2299 void fmov(const Register& rd, const VRegister& vn, int index) 2300 2301 2302### FMSUB ### 2303 2304FP fused multiply-subtract. 2305 2306 void fmsub(const VRegister& vd, 2307 const VRegister& vn, 2308 const VRegister& vm, 2309 const VRegister& va) 2310 2311 2312### FMUL ### 2313 2314FP multiply by element. 2315 2316 void fmul(const VRegister& vd, 2317 const VRegister& vn, 2318 const VRegister& vm, 2319 int vm_index) 2320 2321 2322### FMUL ### 2323 2324FP multiply. 2325 2326 void fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2327 2328 2329### FMULX ### 2330 2331FP multiply extended by element. 2332 2333 void fmulx(const VRegister& vd, 2334 const VRegister& vn, 2335 const VRegister& vm, 2336 int vm_index) 2337 2338 2339### FMULX ### 2340 2341FP vector multiply extended. 2342 2343 void fmulx(const VRegister& vd, 2344 const VRegister& vn, 2345 const VRegister& vm) 2346 2347 2348### FNEG ### 2349 2350FP negate. 2351 2352 void fneg(const VRegister& vd, const VRegister& vn) 2353 2354 2355### FNMADD ### 2356 2357FP fused multiply-add and negate. 2358 2359 void fnmadd(const VRegister& vd, 2360 const VRegister& vn, 2361 const VRegister& vm, 2362 const VRegister& va) 2363 2364 2365### FNMSUB ### 2366 2367FP fused multiply-subtract and negate. 2368 2369 void fnmsub(const VRegister& vd, 2370 const VRegister& vn, 2371 const VRegister& vm, 2372 const VRegister& va) 2373 2374 2375### FNMUL ### 2376 2377FP multiply-negate scalar. 2378 2379 void fnmul(const VRegister& vd, 2380 const VRegister& vn, 2381 const VRegister& vm) 2382 2383 2384### FRECPE ### 2385 2386FP reciprocal estimate. 2387 2388 void frecpe(const VRegister& vd, 2389 const VRegister& vn) 2390 2391 2392### FRECPS ### 2393 2394FP reciprocal step. 2395 2396 void frecps(const VRegister& vd, 2397 const VRegister& vn, 2398 const VRegister& vm) 2399 2400 2401### FRECPX ### 2402 2403FP reciprocal exponent scalar. 2404 2405 void frecpx(const VRegister& vd, 2406 const VRegister& vn) 2407 2408 2409### FRINTA ### 2410 2411FP round to integer, nearest with ties to away. 2412 2413 void frinta(const VRegister& vd, const VRegister& vn) 2414 2415 2416### FRINTI ### 2417 2418FP round to integer, implicit rounding. 2419 2420 void frinti(const VRegister& vd, const VRegister& vn) 2421 2422 2423### FRINTM ### 2424 2425FP round to integer, toward minus infinity. 2426 2427 void frintm(const VRegister& vd, const VRegister& vn) 2428 2429 2430### FRINTN ### 2431 2432FP round to integer, nearest with ties to even. 2433 2434 void frintn(const VRegister& vd, const VRegister& vn) 2435 2436 2437### FRINTP ### 2438 2439FP round to integer, toward plus infinity. 2440 2441 void frintp(const VRegister& vd, const VRegister& vn) 2442 2443 2444### FRINTX ### 2445 2446FP round to integer, exact, implicit rounding. 2447 2448 void frintx(const VRegister& vd, const VRegister& vn) 2449 2450 2451### FRINTZ ### 2452 2453FP round to integer, towards zero. 2454 2455 void frintz(const VRegister& vd, const VRegister& vn) 2456 2457 2458### FRSQRTE ### 2459 2460FP reciprocal square root estimate. 2461 2462 void frsqrte(const VRegister& vd, 2463 const VRegister& vn) 2464 2465 2466### FRSQRTS ### 2467 2468FP reciprocal square root step. 2469 2470 void frsqrts(const VRegister& vd, 2471 const VRegister& vn, 2472 const VRegister& vm) 2473 2474 2475### FSQRT ### 2476 2477FP square root. 2478 2479 void fsqrt(const VRegister& vd, const VRegister& vn) 2480 2481 2482### FSUB ### 2483 2484FP subtract. 2485 2486 void fsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2487 2488 2489### INS ### 2490 2491Insert vector element from another vector element. 2492 2493 void ins(const VRegister& vd, 2494 int vd_index, 2495 const VRegister& vn, 2496 int vn_index) 2497 2498 2499### INS ### 2500 2501Insert vector element from general-purpose register. 2502 2503 void ins(const VRegister& vd, 2504 int vd_index, 2505 const Register& rn) 2506 2507 2508### LD1 ### 2509 2510One-element single structure load to one lane. 2511 2512 void ld1(const VRegister& vt, 2513 int lane, 2514 const MemOperand& src) 2515 2516 2517### LD1 ### 2518 2519One-element structure load to four registers. 2520 2521 void ld1(const VRegister& vt, 2522 const VRegister& vt2, 2523 const VRegister& vt3, 2524 const VRegister& vt4, 2525 const MemOperand& src) 2526 2527 2528### LD1 ### 2529 2530One-element structure load to one register. 2531 2532 void ld1(const VRegister& vt, 2533 const MemOperand& src) 2534 2535 2536### LD1 ### 2537 2538One-element structure load to three registers. 2539 2540 void ld1(const VRegister& vt, 2541 const VRegister& vt2, 2542 const VRegister& vt3, 2543 const MemOperand& src) 2544 2545 2546### LD1 ### 2547 2548One-element structure load to two registers. 2549 2550 void ld1(const VRegister& vt, 2551 const VRegister& vt2, 2552 const MemOperand& src) 2553 2554 2555### LD1R ### 2556 2557One-element single structure load to all lanes. 2558 2559 void ld1r(const VRegister& vt, 2560 const MemOperand& src) 2561 2562 2563### LD2 ### 2564 2565Two-element single structure load to one lane. 2566 2567 void ld2(const VRegister& vt, 2568 const VRegister& vt2, 2569 int lane, 2570 const MemOperand& src) 2571 2572 2573### LD2 ### 2574 2575Two-element structure load. 2576 2577 void ld2(const VRegister& vt, 2578 const VRegister& vt2, 2579 const MemOperand& src) 2580 2581 2582### LD2R ### 2583 2584Two-element single structure load to all lanes. 2585 2586 void ld2r(const VRegister& vt, 2587 const VRegister& vt2, 2588 const MemOperand& src) 2589 2590 2591### LD3 ### 2592 2593Three-element single structure load to one lane. 2594 2595 void ld3(const VRegister& vt, 2596 const VRegister& vt2, 2597 const VRegister& vt3, 2598 int lane, 2599 const MemOperand& src) 2600 2601 2602### LD3 ### 2603 2604Three-element structure load. 2605 2606 void ld3(const VRegister& vt, 2607 const VRegister& vt2, 2608 const VRegister& vt3, 2609 const MemOperand& src) 2610 2611 2612### LD3R ### 2613 2614Three-element single structure load to all lanes. 2615 2616 void ld3r(const VRegister& vt, 2617 const VRegister& vt2, 2618 const VRegister& vt3, 2619 const MemOperand& src) 2620 2621 2622### LD4 ### 2623 2624Four-element single structure load to one lane. 2625 2626 void ld4(const VRegister& vt, 2627 const VRegister& vt2, 2628 const VRegister& vt3, 2629 const VRegister& vt4, 2630 int lane, 2631 const MemOperand& src) 2632 2633 2634### LD4 ### 2635 2636Four-element structure load. 2637 2638 void ld4(const VRegister& vt, 2639 const VRegister& vt2, 2640 const VRegister& vt3, 2641 const VRegister& vt4, 2642 const MemOperand& src) 2643 2644 2645### LD4R ### 2646 2647Four-element single structure load to all lanes. 2648 2649 void ld4r(const VRegister& vt, 2650 const VRegister& vt2, 2651 const VRegister& vt3, 2652 const VRegister& vt4, 2653 const MemOperand& src) 2654 2655 2656### MLA ### 2657 2658Multiply-add by scalar element. 2659 2660 void mla(const VRegister& vd, 2661 const VRegister& vn, 2662 const VRegister& vm, 2663 int vm_index) 2664 2665 2666### MLA ### 2667 2668Multiply-add to accumulator. 2669 2670 void mla(const VRegister& vd, 2671 const VRegister& vn, 2672 const VRegister& vm) 2673 2674 2675### MLS ### 2676 2677Multiply-subtract by scalar element. 2678 2679 void mls(const VRegister& vd, 2680 const VRegister& vn, 2681 const VRegister& vm, 2682 int vm_index) 2683 2684 2685### MLS ### 2686 2687Multiply-subtract to accumulator. 2688 2689 void mls(const VRegister& vd, 2690 const VRegister& vn, 2691 const VRegister& vm) 2692 2693 2694### MOV ### 2695 2696Move general-purpose register to a vector element. 2697 2698 void mov(const VRegister& vd, 2699 int vd_index, 2700 const Register& rn) 2701 2702 2703### MOV ### 2704 2705Move register to register. 2706 2707 void mov(const VRegister& vd, 2708 const VRegister& vn) 2709 2710 2711### MOV ### 2712 2713Move vector element to another vector element. 2714 2715 void mov(const VRegister& vd, 2716 int vd_index, 2717 const VRegister& vn, 2718 int vn_index) 2719 2720 2721### MOV ### 2722 2723Move vector element to general-purpose register. 2724 2725 void mov(const Register& rd, 2726 const VRegister& vn, 2727 int vn_index) 2728 2729 2730### MOV ### 2731 2732Move vector element to scalar. 2733 2734 void mov(const VRegister& vd, 2735 const VRegister& vn, 2736 int vn_index) 2737 2738 2739### MOVI ### 2740 2741Vector move immediate. 2742 2743 void movi(const VRegister& vd, 2744 const uint64_t imm, 2745 Shift shift = LSL, 2746 const int shift_amount = 0) 2747 2748 2749### MUL ### 2750 2751Multiply by scalar element. 2752 2753 void mul(const VRegister& vd, 2754 const VRegister& vn, 2755 const VRegister& vm, 2756 int vm_index) 2757 2758 2759### MUL ### 2760 2761Multiply. 2762 2763 void mul(const VRegister& vd, 2764 const VRegister& vn, 2765 const VRegister& vm) 2766 2767 2768### MVN ### 2769 2770Bitwise not. 2771 2772 void mvn(const VRegister& vd, 2773 const VRegister& vn) 2774 2775 2776### MVNI ### 2777 2778Vector move inverted immediate. 2779 2780 void mvni(const VRegister& vd, 2781 const int imm8, 2782 Shift shift = LSL, 2783 const int shift_amount = 0) 2784 2785 2786### NEG ### 2787 2788Negate. 2789 2790 void neg(const VRegister& vd, 2791 const VRegister& vn) 2792 2793 2794### NOT ### 2795 2796Bitwise not. 2797 2798 void not_(const VRegister& vd, 2799 const VRegister& vn) 2800 2801 2802### ORN ### 2803 2804Bitwise orn. 2805 2806 void orn(const VRegister& vd, 2807 const VRegister& vn, 2808 const VRegister& vm) 2809 2810 2811### ORR ### 2812 2813Bitwise or immediate. 2814 2815 void orr(const VRegister& vd, 2816 const int imm8, 2817 const int left_shift = 0) 2818 2819 2820### ORR ### 2821 2822Bitwise or. 2823 2824 void orr(const VRegister& vd, 2825 const VRegister& vn, 2826 const VRegister& vm) 2827 2828 2829### PMUL ### 2830 2831Polynomial multiply. 2832 2833 void pmul(const VRegister& vd, 2834 const VRegister& vn, 2835 const VRegister& vm) 2836 2837 2838### PMULL ### 2839 2840Polynomial multiply long. 2841 2842 void pmull(const VRegister& vd, 2843 const VRegister& vn, 2844 const VRegister& vm) 2845 2846 2847### PMULL2 ### 2848 2849Polynomial multiply long (second part). 2850 2851 void pmull2(const VRegister& vd, 2852 const VRegister& vn, 2853 const VRegister& vm) 2854 2855 2856### RADDHN ### 2857 2858Rounding add narrow returning high half. 2859 2860 void raddhn(const VRegister& vd, 2861 const VRegister& vn, 2862 const VRegister& vm) 2863 2864 2865### RADDHN2 ### 2866 2867Rounding add narrow returning high half (second part). 2868 2869 void raddhn2(const VRegister& vd, 2870 const VRegister& vn, 2871 const VRegister& vm) 2872 2873 2874### RBIT ### 2875 2876Reverse bit order. 2877 2878 void rbit(const VRegister& vd, 2879 const VRegister& vn) 2880 2881 2882### REV16 ### 2883 2884Reverse elements in 16-bit halfwords. 2885 2886 void rev16(const VRegister& vd, 2887 const VRegister& vn) 2888 2889 2890### REV32 ### 2891 2892Reverse elements in 32-bit words. 2893 2894 void rev32(const VRegister& vd, 2895 const VRegister& vn) 2896 2897 2898### REV64 ### 2899 2900Reverse elements in 64-bit doublewords. 2901 2902 void rev64(const VRegister& vd, 2903 const VRegister& vn) 2904 2905 2906### RSHRN ### 2907 2908Rounding shift right narrow by immediate. 2909 2910 void rshrn(const VRegister& vd, 2911 const VRegister& vn, 2912 int shift) 2913 2914 2915### RSHRN2 ### 2916 2917Rounding shift right narrow by immediate (second part). 2918 2919 void rshrn2(const VRegister& vd, 2920 const VRegister& vn, 2921 int shift) 2922 2923 2924### RSUBHN ### 2925 2926Rounding subtract narrow returning high half. 2927 2928 void rsubhn(const VRegister& vd, 2929 const VRegister& vn, 2930 const VRegister& vm) 2931 2932 2933### RSUBHN2 ### 2934 2935Rounding subtract narrow returning high half (second part). 2936 2937 void rsubhn2(const VRegister& vd, 2938 const VRegister& vn, 2939 const VRegister& vm) 2940 2941 2942### SABA ### 2943 2944Signed absolute difference and accumulate. 2945 2946 void saba(const VRegister& vd, 2947 const VRegister& vn, 2948 const VRegister& vm) 2949 2950 2951### SABAL ### 2952 2953Signed absolute difference and accumulate long. 2954 2955 void sabal(const VRegister& vd, 2956 const VRegister& vn, 2957 const VRegister& vm) 2958 2959 2960### SABAL2 ### 2961 2962Signed absolute difference and accumulate long (second part). 2963 2964 void sabal2(const VRegister& vd, 2965 const VRegister& vn, 2966 const VRegister& vm) 2967 2968 2969### SABD ### 2970 2971Signed absolute difference. 2972 2973 void sabd(const VRegister& vd, 2974 const VRegister& vn, 2975 const VRegister& vm) 2976 2977 2978### SABDL ### 2979 2980Signed absolute difference long. 2981 2982 void sabdl(const VRegister& vd, 2983 const VRegister& vn, 2984 const VRegister& vm) 2985 2986 2987### SABDL2 ### 2988 2989Signed absolute difference long (second part). 2990 2991 void sabdl2(const VRegister& vd, 2992 const VRegister& vn, 2993 const VRegister& vm) 2994 2995 2996### SADALP ### 2997 2998Signed pairwise long add and accumulate. 2999 3000 void sadalp(const VRegister& vd, 3001 const VRegister& vn) 3002 3003 3004### SADDL ### 3005 3006Signed add long. 3007 3008 void saddl(const VRegister& vd, 3009 const VRegister& vn, 3010 const VRegister& vm) 3011 3012 3013### SADDL2 ### 3014 3015Signed add long (second part). 3016 3017 void saddl2(const VRegister& vd, 3018 const VRegister& vn, 3019 const VRegister& vm) 3020 3021 3022### SADDLP ### 3023 3024Signed pairwise long add. 3025 3026 void saddlp(const VRegister& vd, 3027 const VRegister& vn) 3028 3029 3030### SADDLV ### 3031 3032Signed add long across vector. 3033 3034 void saddlv(const VRegister& vd, 3035 const VRegister& vn) 3036 3037 3038### SADDW ### 3039 3040Signed add wide. 3041 3042 void saddw(const VRegister& vd, 3043 const VRegister& vn, 3044 const VRegister& vm) 3045 3046 3047### SADDW2 ### 3048 3049Signed add wide (second part). 3050 3051 void saddw2(const VRegister& vd, 3052 const VRegister& vn, 3053 const VRegister& vm) 3054 3055 3056### SCVTF ### 3057 3058Convert signed integer or fixed point to FP. 3059 3060 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0) 3061 3062 3063### SCVTF ### 3064 3065Convert signed integer or fixed-point to FP. 3066 3067 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0) 3068 3069 3070### SHADD ### 3071 3072Signed halving add. 3073 3074 void shadd(const VRegister& vd, 3075 const VRegister& vn, 3076 const VRegister& vm) 3077 3078 3079### SHL ### 3080 3081Shift left by immediate. 3082 3083 void shl(const VRegister& vd, 3084 const VRegister& vn, 3085 int shift) 3086 3087 3088### SHLL ### 3089 3090Shift left long by element size. 3091 3092 void shll(const VRegister& vd, 3093 const VRegister& vn, 3094 int shift) 3095 3096 3097### SHLL2 ### 3098 3099Shift left long by element size (second part). 3100 3101 void shll2(const VRegister& vd, 3102 const VRegister& vn, 3103 int shift) 3104 3105 3106### SHRN ### 3107 3108Shift right narrow by immediate. 3109 3110 void shrn(const VRegister& vd, 3111 const VRegister& vn, 3112 int shift) 3113 3114 3115### SHRN2 ### 3116 3117Shift right narrow by immediate (second part). 3118 3119 void shrn2(const VRegister& vd, 3120 const VRegister& vn, 3121 int shift) 3122 3123 3124### SHSUB ### 3125 3126Signed halving sub. 3127 3128 void shsub(const VRegister& vd, 3129 const VRegister& vn, 3130 const VRegister& vm) 3131 3132 3133### SLI ### 3134 3135Shift left by immediate and insert. 3136 3137 void sli(const VRegister& vd, 3138 const VRegister& vn, 3139 int shift) 3140 3141 3142### SMAX ### 3143 3144Signed maximum. 3145 3146 void smax(const VRegister& vd, 3147 const VRegister& vn, 3148 const VRegister& vm) 3149 3150 3151### SMAXP ### 3152 3153Signed pairwise maximum. 3154 3155 void smaxp(const VRegister& vd, 3156 const VRegister& vn, 3157 const VRegister& vm) 3158 3159 3160### SMAXV ### 3161 3162Signed maximum across vector. 3163 3164 void smaxv(const VRegister& vd, 3165 const VRegister& vn) 3166 3167 3168### SMIN ### 3169 3170Signed minimum. 3171 3172 void smin(const VRegister& vd, 3173 const VRegister& vn, 3174 const VRegister& vm) 3175 3176 3177### SMINP ### 3178 3179Signed minimum pairwise. 3180 3181 void sminp(const VRegister& vd, 3182 const VRegister& vn, 3183 const VRegister& vm) 3184 3185 3186### SMINV ### 3187 3188Signed minimum across vector. 3189 3190 void sminv(const VRegister& vd, 3191 const VRegister& vn) 3192 3193 3194### SMLAL ### 3195 3196Signed long multiply-add by scalar element. 3197 3198 void smlal(const VRegister& vd, 3199 const VRegister& vn, 3200 const VRegister& vm, 3201 int vm_index) 3202 3203 3204### SMLAL ### 3205 3206Signed long multiply-add. 3207 3208 void smlal(const VRegister& vd, 3209 const VRegister& vn, 3210 const VRegister& vm) 3211 3212 3213### SMLAL2 ### 3214 3215Signed long multiply-add (second part). 3216 3217 void smlal2(const VRegister& vd, 3218 const VRegister& vn, 3219 const VRegister& vm) 3220 3221 3222### SMLAL2 ### 3223 3224Signed long multiply-add by scalar element (second part). 3225 3226 void smlal2(const VRegister& vd, 3227 const VRegister& vn, 3228 const VRegister& vm, 3229 int vm_index) 3230 3231 3232### SMLSL ### 3233 3234Signed long multiply-sub by scalar element. 3235 3236 void smlsl(const VRegister& vd, 3237 const VRegister& vn, 3238 const VRegister& vm, 3239 int vm_index) 3240 3241 3242### SMLSL ### 3243 3244Signed long multiply-sub. 3245 3246 void smlsl(const VRegister& vd, 3247 const VRegister& vn, 3248 const VRegister& vm) 3249 3250 3251### SMLSL2 ### 3252 3253Signed long multiply-sub (second part). 3254 3255 void smlsl2(const VRegister& vd, 3256 const VRegister& vn, 3257 const VRegister& vm) 3258 3259 3260### SMLSL2 ### 3261 3262Signed long multiply-sub by scalar element (second part). 3263 3264 void smlsl2(const VRegister& vd, 3265 const VRegister& vn, 3266 const VRegister& vm, 3267 int vm_index) 3268 3269 3270### SMOV ### 3271 3272Signed move vector element to general-purpose register. 3273 3274 void smov(const Register& rd, 3275 const VRegister& vn, 3276 int vn_index) 3277 3278 3279### SMULL ### 3280 3281Signed long multiply by scalar element. 3282 3283 void smull(const VRegister& vd, 3284 const VRegister& vn, 3285 const VRegister& vm, 3286 int vm_index) 3287 3288 3289### SMULL ### 3290 3291Signed long multiply. 3292 3293 void smull(const VRegister& vd, 3294 const VRegister& vn, 3295 const VRegister& vm) 3296 3297 3298### SMULL2 ### 3299 3300Signed long multiply (second part). 3301 3302 void smull2(const VRegister& vd, 3303 const VRegister& vn, 3304 const VRegister& vm) 3305 3306 3307### SMULL2 ### 3308 3309Signed long multiply by scalar element (second part). 3310 3311 void smull2(const VRegister& vd, 3312 const VRegister& vn, 3313 const VRegister& vm, 3314 int vm_index) 3315 3316 3317### SQABS ### 3318 3319Signed saturating absolute value. 3320 3321 void sqabs(const VRegister& vd, 3322 const VRegister& vn) 3323 3324 3325### SQADD ### 3326 3327Signed saturating add. 3328 3329 void sqadd(const VRegister& vd, 3330 const VRegister& vn, 3331 const VRegister& vm) 3332 3333 3334### SQDMLAL ### 3335 3336Signed saturating doubling long multiply-add by element. 3337 3338 void sqdmlal(const VRegister& vd, 3339 const VRegister& vn, 3340 const VRegister& vm, 3341 int vm_index) 3342 3343 3344### SQDMLAL ### 3345 3346Signed saturating doubling long multiply-add. 3347 3348 void sqdmlal(const VRegister& vd, 3349 const VRegister& vn, 3350 const VRegister& vm) 3351 3352 3353### SQDMLAL2 ### 3354 3355Signed saturating doubling long multiply-add (second part). 3356 3357 void sqdmlal2(const VRegister& vd, 3358 const VRegister& vn, 3359 const VRegister& vm) 3360 3361 3362### SQDMLAL2 ### 3363 3364Signed saturating doubling long multiply-add by element (second part). 3365 3366 void sqdmlal2(const VRegister& vd, 3367 const VRegister& vn, 3368 const VRegister& vm, 3369 int vm_index) 3370 3371 3372### SQDMLSL ### 3373 3374Signed saturating doubling long multiply-sub by element. 3375 3376 void sqdmlsl(const VRegister& vd, 3377 const VRegister& vn, 3378 const VRegister& vm, 3379 int vm_index) 3380 3381 3382### SQDMLSL ### 3383 3384Signed saturating doubling long multiply-subtract. 3385 3386 void sqdmlsl(const VRegister& vd, 3387 const VRegister& vn, 3388 const VRegister& vm) 3389 3390 3391### SQDMLSL2 ### 3392 3393Signed saturating doubling long multiply-sub by element (second part). 3394 3395 void sqdmlsl2(const VRegister& vd, 3396 const VRegister& vn, 3397 const VRegister& vm, 3398 int vm_index) 3399 3400 3401### SQDMLSL2 ### 3402 3403Signed saturating doubling long multiply-subtract (second part). 3404 3405 void sqdmlsl2(const VRegister& vd, 3406 const VRegister& vn, 3407 const VRegister& vm) 3408 3409 3410### SQDMULH ### 3411 3412Signed saturating doubling multiply element returning high half. 3413 3414 void sqdmulh(const VRegister& vd, 3415 const VRegister& vn, 3416 const VRegister& vm, 3417 int vm_index) 3418 3419 3420### SQDMULH ### 3421 3422Signed saturating doubling multiply returning high half. 3423 3424 void sqdmulh(const VRegister& vd, 3425 const VRegister& vn, 3426 const VRegister& vm) 3427 3428 3429### SQDMULL ### 3430 3431Signed saturating double long multiply by element. 3432 3433 void sqdmull(const VRegister& vd, 3434 const VRegister& vn, 3435 const VRegister& vm, 3436 int vm_index) 3437 3438 3439### SQDMULL ### 3440 3441Signed saturating doubling long multiply. 3442 3443 void sqdmull(const VRegister& vd, 3444 const VRegister& vn, 3445 const VRegister& vm) 3446 3447 3448### SQDMULL2 ### 3449 3450Signed saturating double long multiply by element (second part). 3451 3452 void sqdmull2(const VRegister& vd, 3453 const VRegister& vn, 3454 const VRegister& vm, 3455 int vm_index) 3456 3457 3458### SQDMULL2 ### 3459 3460Signed saturating doubling long multiply (second part). 3461 3462 void sqdmull2(const VRegister& vd, 3463 const VRegister& vn, 3464 const VRegister& vm) 3465 3466 3467### SQNEG ### 3468 3469Signed saturating negate. 3470 3471 void sqneg(const VRegister& vd, 3472 const VRegister& vn) 3473 3474 3475### SQRDMULH ### 3476 3477Signed saturating rounding doubling multiply element returning high half. 3478 3479 void sqrdmulh(const VRegister& vd, 3480 const VRegister& vn, 3481 const VRegister& vm, 3482 int vm_index) 3483 3484 3485### SQRDMULH ### 3486 3487Signed saturating rounding doubling multiply returning high half. 3488 3489 void sqrdmulh(const VRegister& vd, 3490 const VRegister& vn, 3491 const VRegister& vm) 3492 3493 3494### SQRSHL ### 3495 3496Signed saturating rounding shift left by register. 3497 3498 void sqrshl(const VRegister& vd, 3499 const VRegister& vn, 3500 const VRegister& vm) 3501 3502 3503### SQRSHRN ### 3504 3505Signed saturating rounded shift right narrow by immediate. 3506 3507 void sqrshrn(const VRegister& vd, 3508 const VRegister& vn, 3509 int shift) 3510 3511 3512### SQRSHRN2 ### 3513 3514Signed saturating rounded shift right narrow by immediate (second part). 3515 3516 void sqrshrn2(const VRegister& vd, 3517 const VRegister& vn, 3518 int shift) 3519 3520 3521### SQRSHRUN ### 3522 3523Signed sat rounded shift right unsigned narrow by immediate. 3524 3525 void sqrshrun(const VRegister& vd, 3526 const VRegister& vn, 3527 int shift) 3528 3529 3530### SQRSHRUN2 ### 3531 3532Signed sat rounded shift right unsigned narrow by immediate (second part). 3533 3534 void sqrshrun2(const VRegister& vd, 3535 const VRegister& vn, 3536 int shift) 3537 3538 3539### SQSHL ### 3540 3541Signed saturating shift left by immediate. 3542 3543 void sqshl(const VRegister& vd, 3544 const VRegister& vn, 3545 int shift) 3546 3547 3548### SQSHL ### 3549 3550Signed saturating shift left by register. 3551 3552 void sqshl(const VRegister& vd, 3553 const VRegister& vn, 3554 const VRegister& vm) 3555 3556 3557### SQSHLU ### 3558 3559Signed saturating shift left unsigned by immediate. 3560 3561 void sqshlu(const VRegister& vd, 3562 const VRegister& vn, 3563 int shift) 3564 3565 3566### SQSHRN ### 3567 3568Signed saturating shift right narrow by immediate. 3569 3570 void sqshrn(const VRegister& vd, 3571 const VRegister& vn, 3572 int shift) 3573 3574 3575### SQSHRN2 ### 3576 3577Signed saturating shift right narrow by immediate (second part). 3578 3579 void sqshrn2(const VRegister& vd, 3580 const VRegister& vn, 3581 int shift) 3582 3583 3584### SQSHRUN ### 3585 3586Signed saturating shift right unsigned narrow by immediate. 3587 3588 void sqshrun(const VRegister& vd, 3589 const VRegister& vn, 3590 int shift) 3591 3592 3593### SQSHRUN2 ### 3594 3595Signed saturating shift right unsigned narrow by immediate (second part). 3596 3597 void sqshrun2(const VRegister& vd, 3598 const VRegister& vn, 3599 int shift) 3600 3601 3602### SQSUB ### 3603 3604Signed saturating subtract. 3605 3606 void sqsub(const VRegister& vd, 3607 const VRegister& vn, 3608 const VRegister& vm) 3609 3610 3611### SQXTN ### 3612 3613Signed saturating extract narrow. 3614 3615 void sqxtn(const VRegister& vd, 3616 const VRegister& vn) 3617 3618 3619### SQXTN2 ### 3620 3621Signed saturating extract narrow (second part). 3622 3623 void sqxtn2(const VRegister& vd, 3624 const VRegister& vn) 3625 3626 3627### SQXTUN ### 3628 3629Signed saturating extract unsigned narrow. 3630 3631 void sqxtun(const VRegister& vd, 3632 const VRegister& vn) 3633 3634 3635### SQXTUN2 ### 3636 3637Signed saturating extract unsigned narrow (second part). 3638 3639 void sqxtun2(const VRegister& vd, 3640 const VRegister& vn) 3641 3642 3643### SRHADD ### 3644 3645Signed rounding halving add. 3646 3647 void srhadd(const VRegister& vd, 3648 const VRegister& vn, 3649 const VRegister& vm) 3650 3651 3652### SRI ### 3653 3654Shift right by immediate and insert. 3655 3656 void sri(const VRegister& vd, 3657 const VRegister& vn, 3658 int shift) 3659 3660 3661### SRSHL ### 3662 3663Signed rounding shift left by register. 3664 3665 void srshl(const VRegister& vd, 3666 const VRegister& vn, 3667 const VRegister& vm) 3668 3669 3670### SRSHR ### 3671 3672Signed rounding shift right by immediate. 3673 3674 void srshr(const VRegister& vd, 3675 const VRegister& vn, 3676 int shift) 3677 3678 3679### SRSRA ### 3680 3681Signed rounding shift right by immediate and accumulate. 3682 3683 void srsra(const VRegister& vd, 3684 const VRegister& vn, 3685 int shift) 3686 3687 3688### SSHL ### 3689 3690Signed shift left by register. 3691 3692 void sshl(const VRegister& vd, 3693 const VRegister& vn, 3694 const VRegister& vm) 3695 3696 3697### SSHLL ### 3698 3699Signed shift left long by immediate. 3700 3701 void sshll(const VRegister& vd, 3702 const VRegister& vn, 3703 int shift) 3704 3705 3706### SSHLL2 ### 3707 3708Signed shift left long by immediate (second part). 3709 3710 void sshll2(const VRegister& vd, 3711 const VRegister& vn, 3712 int shift) 3713 3714 3715### SSHR ### 3716 3717Signed shift right by immediate. 3718 3719 void sshr(const VRegister& vd, 3720 const VRegister& vn, 3721 int shift) 3722 3723 3724### SSRA ### 3725 3726Signed shift right by immediate and accumulate. 3727 3728 void ssra(const VRegister& vd, 3729 const VRegister& vn, 3730 int shift) 3731 3732 3733### SSUBL ### 3734 3735Signed subtract long. 3736 3737 void ssubl(const VRegister& vd, 3738 const VRegister& vn, 3739 const VRegister& vm) 3740 3741 3742### SSUBL2 ### 3743 3744Signed subtract long (second part). 3745 3746 void ssubl2(const VRegister& vd, 3747 const VRegister& vn, 3748 const VRegister& vm) 3749 3750 3751### SSUBW ### 3752 3753Signed integer subtract wide. 3754 3755 void ssubw(const VRegister& vd, 3756 const VRegister& vn, 3757 const VRegister& vm) 3758 3759 3760### SSUBW2 ### 3761 3762Signed integer subtract wide (second part). 3763 3764 void ssubw2(const VRegister& vd, 3765 const VRegister& vn, 3766 const VRegister& vm) 3767 3768 3769### ST1 ### 3770 3771One-element single structure store from one lane. 3772 3773 void st1(const VRegister& vt, 3774 int lane, 3775 const MemOperand& src) 3776 3777 3778### ST1 ### 3779 3780One-element structure store from four registers. 3781 3782 void st1(const VRegister& vt, 3783 const VRegister& vt2, 3784 const VRegister& vt3, 3785 const VRegister& vt4, 3786 const MemOperand& src) 3787 3788 3789### ST1 ### 3790 3791One-element structure store from one register. 3792 3793 void st1(const VRegister& vt, 3794 const MemOperand& src) 3795 3796 3797### ST1 ### 3798 3799One-element structure store from three registers. 3800 3801 void st1(const VRegister& vt, 3802 const VRegister& vt2, 3803 const VRegister& vt3, 3804 const MemOperand& src) 3805 3806 3807### ST1 ### 3808 3809One-element structure store from two registers. 3810 3811 void st1(const VRegister& vt, 3812 const VRegister& vt2, 3813 const MemOperand& src) 3814 3815 3816### ST2 ### 3817 3818Two-element single structure store from two lanes. 3819 3820 void st2(const VRegister& vt, 3821 const VRegister& vt2, 3822 int lane, 3823 const MemOperand& src) 3824 3825 3826### ST2 ### 3827 3828Two-element structure store from two registers. 3829 3830 void st2(const VRegister& vt, 3831 const VRegister& vt2, 3832 const MemOperand& src) 3833 3834 3835### ST3 ### 3836 3837Three-element single structure store from three lanes. 3838 3839 void st3(const VRegister& vt, 3840 const VRegister& vt2, 3841 const VRegister& vt3, 3842 int lane, 3843 const MemOperand& src) 3844 3845 3846### ST3 ### 3847 3848Three-element structure store from three registers. 3849 3850 void st3(const VRegister& vt, 3851 const VRegister& vt2, 3852 const VRegister& vt3, 3853 const MemOperand& src) 3854 3855 3856### ST4 ### 3857 3858Four-element single structure store from four lanes. 3859 3860 void st4(const VRegister& vt, 3861 const VRegister& vt2, 3862 const VRegister& vt3, 3863 const VRegister& vt4, 3864 int lane, 3865 const MemOperand& src) 3866 3867 3868### ST4 ### 3869 3870Four-element structure store from four registers. 3871 3872 void st4(const VRegister& vt, 3873 const VRegister& vt2, 3874 const VRegister& vt3, 3875 const VRegister& vt4, 3876 const MemOperand& src) 3877 3878 3879### SUB ### 3880 3881Subtract. 3882 3883 void sub(const VRegister& vd, 3884 const VRegister& vn, 3885 const VRegister& vm) 3886 3887 3888### SUBHN ### 3889 3890Subtract narrow returning high half. 3891 3892 void subhn(const VRegister& vd, 3893 const VRegister& vn, 3894 const VRegister& vm) 3895 3896 3897### SUBHN2 ### 3898 3899Subtract narrow returning high half (second part). 3900 3901 void subhn2(const VRegister& vd, 3902 const VRegister& vn, 3903 const VRegister& vm) 3904 3905 3906### SUQADD ### 3907 3908Signed saturating accumulate of unsigned value. 3909 3910 void suqadd(const VRegister& vd, 3911 const VRegister& vn) 3912 3913 3914### SXTL ### 3915 3916Signed extend long. 3917 3918 void sxtl(const VRegister& vd, 3919 const VRegister& vn) 3920 3921 3922### SXTL2 ### 3923 3924Signed extend long (second part). 3925 3926 void sxtl2(const VRegister& vd, 3927 const VRegister& vn) 3928 3929 3930### TBL ### 3931 3932Table lookup from four registers. 3933 3934 void tbl(const VRegister& vd, 3935 const VRegister& vn, 3936 const VRegister& vn2, 3937 const VRegister& vn3, 3938 const VRegister& vn4, 3939 const VRegister& vm) 3940 3941 3942### TBL ### 3943 3944Table lookup from one register. 3945 3946 void tbl(const VRegister& vd, 3947 const VRegister& vn, 3948 const VRegister& vm) 3949 3950 3951### TBL ### 3952 3953Table lookup from three registers. 3954 3955 void tbl(const VRegister& vd, 3956 const VRegister& vn, 3957 const VRegister& vn2, 3958 const VRegister& vn3, 3959 const VRegister& vm) 3960 3961 3962### TBL ### 3963 3964Table lookup from two registers. 3965 3966 void tbl(const VRegister& vd, 3967 const VRegister& vn, 3968 const VRegister& vn2, 3969 const VRegister& vm) 3970 3971 3972### TBX ### 3973 3974Table lookup extension from four registers. 3975 3976 void tbx(const VRegister& vd, 3977 const VRegister& vn, 3978 const VRegister& vn2, 3979 const VRegister& vn3, 3980 const VRegister& vn4, 3981 const VRegister& vm) 3982 3983 3984### TBX ### 3985 3986Table lookup extension from one register. 3987 3988 void tbx(const VRegister& vd, 3989 const VRegister& vn, 3990 const VRegister& vm) 3991 3992 3993### TBX ### 3994 3995Table lookup extension from three registers. 3996 3997 void tbx(const VRegister& vd, 3998 const VRegister& vn, 3999 const VRegister& vn2, 4000 const VRegister& vn3, 4001 const VRegister& vm) 4002 4003 4004### TBX ### 4005 4006Table lookup extension from two registers. 4007 4008 void tbx(const VRegister& vd, 4009 const VRegister& vn, 4010 const VRegister& vn2, 4011 const VRegister& vm) 4012 4013 4014### TRN1 ### 4015 4016Transpose vectors (primary). 4017 4018 void trn1(const VRegister& vd, 4019 const VRegister& vn, 4020 const VRegister& vm) 4021 4022 4023### TRN2 ### 4024 4025Transpose vectors (secondary). 4026 4027 void trn2(const VRegister& vd, 4028 const VRegister& vn, 4029 const VRegister& vm) 4030 4031 4032### UABA ### 4033 4034Unsigned absolute difference and accumulate. 4035 4036 void uaba(const VRegister& vd, 4037 const VRegister& vn, 4038 const VRegister& vm) 4039 4040 4041### UABAL ### 4042 4043Unsigned absolute difference and accumulate long. 4044 4045 void uabal(const VRegister& vd, 4046 const VRegister& vn, 4047 const VRegister& vm) 4048 4049 4050### UABAL2 ### 4051 4052Unsigned absolute difference and accumulate long (second part). 4053 4054 void uabal2(const VRegister& vd, 4055 const VRegister& vn, 4056 const VRegister& vm) 4057 4058 4059### UABD ### 4060 4061Unsigned absolute difference. 4062 4063 void uabd(const VRegister& vd, 4064 const VRegister& vn, 4065 const VRegister& vm) 4066 4067 4068### UABDL ### 4069 4070Unsigned absolute difference long. 4071 4072 void uabdl(const VRegister& vd, 4073 const VRegister& vn, 4074 const VRegister& vm) 4075 4076 4077### UABDL2 ### 4078 4079Unsigned absolute difference long (second part). 4080 4081 void uabdl2(const VRegister& vd, 4082 const VRegister& vn, 4083 const VRegister& vm) 4084 4085 4086### UADALP ### 4087 4088Unsigned pairwise long add and accumulate. 4089 4090 void uadalp(const VRegister& vd, 4091 const VRegister& vn) 4092 4093 4094### UADDL ### 4095 4096Unsigned add long. 4097 4098 void uaddl(const VRegister& vd, 4099 const VRegister& vn, 4100 const VRegister& vm) 4101 4102 4103### UADDL2 ### 4104 4105Unsigned add long (second part). 4106 4107 void uaddl2(const VRegister& vd, 4108 const VRegister& vn, 4109 const VRegister& vm) 4110 4111 4112### UADDLP ### 4113 4114Unsigned pairwise long add. 4115 4116 void uaddlp(const VRegister& vd, 4117 const VRegister& vn) 4118 4119 4120### UADDLV ### 4121 4122Unsigned add long across vector. 4123 4124 void uaddlv(const VRegister& vd, 4125 const VRegister& vn) 4126 4127 4128### UADDW ### 4129 4130Unsigned add wide. 4131 4132 void uaddw(const VRegister& vd, 4133 const VRegister& vn, 4134 const VRegister& vm) 4135 4136 4137### UADDW2 ### 4138 4139Unsigned add wide (second part). 4140 4141 void uaddw2(const VRegister& vd, 4142 const VRegister& vn, 4143 const VRegister& vm) 4144 4145 4146### UCVTF ### 4147 4148Convert unsigned integer or fixed point to FP. 4149 4150 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0) 4151 4152 4153### UCVTF ### 4154 4155Convert unsigned integer or fixed-point to FP. 4156 4157 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0) 4158 4159 4160### UHADD ### 4161 4162Unsigned halving add. 4163 4164 void uhadd(const VRegister& vd, 4165 const VRegister& vn, 4166 const VRegister& vm) 4167 4168 4169### UHSUB ### 4170 4171Unsigned halving sub. 4172 4173 void uhsub(const VRegister& vd, 4174 const VRegister& vn, 4175 const VRegister& vm) 4176 4177 4178### UMAX ### 4179 4180Unsigned maximum. 4181 4182 void umax(const VRegister& vd, 4183 const VRegister& vn, 4184 const VRegister& vm) 4185 4186 4187### UMAXP ### 4188 4189Unsigned pairwise maximum. 4190 4191 void umaxp(const VRegister& vd, 4192 const VRegister& vn, 4193 const VRegister& vm) 4194 4195 4196### UMAXV ### 4197 4198Unsigned maximum across vector. 4199 4200 void umaxv(const VRegister& vd, 4201 const VRegister& vn) 4202 4203 4204### UMIN ### 4205 4206Unsigned minimum. 4207 4208 void umin(const VRegister& vd, 4209 const VRegister& vn, 4210 const VRegister& vm) 4211 4212 4213### UMINP ### 4214 4215Unsigned pairwise minimum. 4216 4217 void uminp(const VRegister& vd, 4218 const VRegister& vn, 4219 const VRegister& vm) 4220 4221 4222### UMINV ### 4223 4224Unsigned minimum across vector. 4225 4226 void uminv(const VRegister& vd, 4227 const VRegister& vn) 4228 4229 4230### UMLAL ### 4231 4232Unsigned long multiply-add by scalar element. 4233 4234 void umlal(const VRegister& vd, 4235 const VRegister& vn, 4236 const VRegister& vm, 4237 int vm_index) 4238 4239 4240### UMLAL ### 4241 4242Unsigned long multiply-add. 4243 4244 void umlal(const VRegister& vd, 4245 const VRegister& vn, 4246 const VRegister& vm) 4247 4248 4249### UMLAL2 ### 4250 4251Unsigned long multiply-add (second part). 4252 4253 void umlal2(const VRegister& vd, 4254 const VRegister& vn, 4255 const VRegister& vm) 4256 4257 4258### UMLAL2 ### 4259 4260Unsigned long multiply-add by scalar element (second part). 4261 4262 void umlal2(const VRegister& vd, 4263 const VRegister& vn, 4264 const VRegister& vm, 4265 int vm_index) 4266 4267 4268### UMLSL ### 4269 4270Unsigned long multiply-sub by scalar element. 4271 4272 void umlsl(const VRegister& vd, 4273 const VRegister& vn, 4274 const VRegister& vm, 4275 int vm_index) 4276 4277 4278### UMLSL ### 4279 4280Unsigned long multiply-sub. 4281 4282 void umlsl(const VRegister& vd, 4283 const VRegister& vn, 4284 const VRegister& vm) 4285 4286 4287### UMLSL2 ### 4288 4289Unsigned long multiply-sub (second part). 4290 4291 void umlsl2(const VRegister& vd, 4292 const VRegister& vn, 4293 const VRegister& vm) 4294 4295 4296### UMLSL2 ### 4297 4298Unsigned long multiply-sub by scalar element (second part). 4299 4300 void umlsl2(const VRegister& vd, 4301 const VRegister& vn, 4302 const VRegister& vm, 4303 int vm_index) 4304 4305 4306### UMOV ### 4307 4308Unsigned move vector element to general-purpose register. 4309 4310 void umov(const Register& rd, 4311 const VRegister& vn, 4312 int vn_index) 4313 4314 4315### UMULL ### 4316 4317Unsigned long multiply by scalar element. 4318 4319 void umull(const VRegister& vd, 4320 const VRegister& vn, 4321 const VRegister& vm, 4322 int vm_index) 4323 4324 4325### UMULL ### 4326 4327Unsigned long multiply long. 4328 4329 void umull(const VRegister& vd, 4330 const VRegister& vn, 4331 const VRegister& vm) 4332 4333 4334### UMULL2 ### 4335 4336Unsigned long multiply (second part). 4337 4338 void umull2(const VRegister& vd, 4339 const VRegister& vn, 4340 const VRegister& vm) 4341 4342 4343### UMULL2 ### 4344 4345Unsigned long multiply by scalar element (second part). 4346 4347 void umull2(const VRegister& vd, 4348 const VRegister& vn, 4349 const VRegister& vm, 4350 int vm_index) 4351 4352 4353### UQADD ### 4354 4355Unsigned saturating add. 4356 4357 void uqadd(const VRegister& vd, 4358 const VRegister& vn, 4359 const VRegister& vm) 4360 4361 4362### UQRSHL ### 4363 4364Unsigned saturating rounding shift left by register. 4365 4366 void uqrshl(const VRegister& vd, 4367 const VRegister& vn, 4368 const VRegister& vm) 4369 4370 4371### UQRSHRN ### 4372 4373Unsigned saturating rounding shift right narrow by immediate. 4374 4375 void uqrshrn(const VRegister& vd, 4376 const VRegister& vn, 4377 int shift) 4378 4379 4380### UQRSHRN2 ### 4381 4382Unsigned saturating rounding shift right narrow by immediate (second part). 4383 4384 void uqrshrn2(const VRegister& vd, 4385 const VRegister& vn, 4386 int shift) 4387 4388 4389### UQSHL ### 4390 4391Unsigned saturating shift left by immediate. 4392 4393 void uqshl(const VRegister& vd, 4394 const VRegister& vn, 4395 int shift) 4396 4397 4398### UQSHL ### 4399 4400Unsigned saturating shift left by register. 4401 4402 void uqshl(const VRegister& vd, 4403 const VRegister& vn, 4404 const VRegister& vm) 4405 4406 4407### UQSHRN ### 4408 4409Unsigned saturating shift right narrow by immediate. 4410 4411 void uqshrn(const VRegister& vd, 4412 const VRegister& vn, 4413 int shift) 4414 4415 4416### UQSHRN2 ### 4417 4418Unsigned saturating shift right narrow by immediate (second part). 4419 4420 void uqshrn2(const VRegister& vd, 4421 const VRegister& vn, 4422 int shift) 4423 4424 4425### UQSUB ### 4426 4427Unsigned saturating subtract. 4428 4429 void uqsub(const VRegister& vd, 4430 const VRegister& vn, 4431 const VRegister& vm) 4432 4433 4434### UQXTN ### 4435 4436Unsigned saturating extract narrow. 4437 4438 void uqxtn(const VRegister& vd, 4439 const VRegister& vn) 4440 4441 4442### UQXTN2 ### 4443 4444Unsigned saturating extract narrow (second part). 4445 4446 void uqxtn2(const VRegister& vd, 4447 const VRegister& vn) 4448 4449 4450### URECPE ### 4451 4452Unsigned reciprocal estimate. 4453 4454 void urecpe(const VRegister& vd, 4455 const VRegister& vn) 4456 4457 4458### URHADD ### 4459 4460Unsigned rounding halving add. 4461 4462 void urhadd(const VRegister& vd, 4463 const VRegister& vn, 4464 const VRegister& vm) 4465 4466 4467### URSHL ### 4468 4469Unsigned rounding shift left by register. 4470 4471 void urshl(const VRegister& vd, 4472 const VRegister& vn, 4473 const VRegister& vm) 4474 4475 4476### URSHR ### 4477 4478Unsigned rounding shift right by immediate. 4479 4480 void urshr(const VRegister& vd, 4481 const VRegister& vn, 4482 int shift) 4483 4484 4485### URSQRTE ### 4486 4487Unsigned reciprocal square root estimate. 4488 4489 void ursqrte(const VRegister& vd, 4490 const VRegister& vn) 4491 4492 4493### URSRA ### 4494 4495Unsigned rounding shift right by immediate and accumulate. 4496 4497 void ursra(const VRegister& vd, 4498 const VRegister& vn, 4499 int shift) 4500 4501 4502### USHL ### 4503 4504Unsigned shift left by register. 4505 4506 void ushl(const VRegister& vd, 4507 const VRegister& vn, 4508 const VRegister& vm) 4509 4510 4511### USHLL ### 4512 4513Unsigned shift left long by immediate. 4514 4515 void ushll(const VRegister& vd, 4516 const VRegister& vn, 4517 int shift) 4518 4519 4520### USHLL2 ### 4521 4522Unsigned shift left long by immediate (second part). 4523 4524 void ushll2(const VRegister& vd, 4525 const VRegister& vn, 4526 int shift) 4527 4528 4529### USHR ### 4530 4531Unsigned shift right by immediate. 4532 4533 void ushr(const VRegister& vd, 4534 const VRegister& vn, 4535 int shift) 4536 4537 4538### USQADD ### 4539 4540Unsigned saturating accumulate of signed value. 4541 4542 void usqadd(const VRegister& vd, 4543 const VRegister& vn) 4544 4545 4546### USRA ### 4547 4548Unsigned shift right by immediate and accumulate. 4549 4550 void usra(const VRegister& vd, 4551 const VRegister& vn, 4552 int shift) 4553 4554 4555### USUBL ### 4556 4557Unsigned subtract long. 4558 4559 void usubl(const VRegister& vd, 4560 const VRegister& vn, 4561 const VRegister& vm) 4562 4563 4564### USUBL2 ### 4565 4566Unsigned subtract long (second part). 4567 4568 void usubl2(const VRegister& vd, 4569 const VRegister& vn, 4570 const VRegister& vm) 4571 4572 4573### USUBW ### 4574 4575Unsigned subtract wide. 4576 4577 void usubw(const VRegister& vd, 4578 const VRegister& vn, 4579 const VRegister& vm) 4580 4581 4582### USUBW2 ### 4583 4584Unsigned subtract wide (second part). 4585 4586 void usubw2(const VRegister& vd, 4587 const VRegister& vn, 4588 const VRegister& vm) 4589 4590 4591### UXTL ### 4592 4593Unsigned extend long. 4594 4595 void uxtl(const VRegister& vd, 4596 const VRegister& vn) 4597 4598 4599### UXTL2 ### 4600 4601Unsigned extend long (second part). 4602 4603 void uxtl2(const VRegister& vd, 4604 const VRegister& vn) 4605 4606 4607### UZP1 ### 4608 4609Unzip vectors (primary). 4610 4611 void uzp1(const VRegister& vd, 4612 const VRegister& vn, 4613 const VRegister& vm) 4614 4615 4616### UZP2 ### 4617 4618Unzip vectors (secondary). 4619 4620 void uzp2(const VRegister& vd, 4621 const VRegister& vn, 4622 const VRegister& vm) 4623 4624 4625### XTN ### 4626 4627Extract narrow. 4628 4629 void xtn(const VRegister& vd, 4630 const VRegister& vn) 4631 4632 4633### XTN2 ### 4634 4635Extract narrow (second part). 4636 4637 void xtn2(const VRegister& vd, 4638 const VRegister& vn) 4639 4640 4641### ZIP1 ### 4642 4643Zip vectors (primary). 4644 4645 void zip1(const VRegister& vd, 4646 const VRegister& vn, 4647 const VRegister& vm) 4648 4649 4650### ZIP2 ### 4651 4652Zip vectors (secondary). 4653 4654 void zip2(const VRegister& vd, 4655 const VRegister& vn, 4656 const VRegister& vm) 4657 4658 4659 4660Additional or pseudo instructions 4661--------------------------------- 4662 4663### BIND ### 4664 4665Bind a label to the current PC. 4666 4667 void bind(Label* label) 4668 4669 4670### DC32 ### 4671 4672Emit 32 bits of data into the instruction stream. 4673 4674 void dc32(uint32_t data) 4675 4676 4677### DC64 ### 4678 4679Emit 64 bits of data into the instruction stream. 4680 4681 void dc64(uint64_t data) 4682 4683 4684### DCI ### 4685 4686Emit raw instructions into the instruction stream. 4687 4688 void dci(Instr raw_inst) 4689 4690 4691### PLACE ### 4692 4693Place a literal at the current PC. 4694 4695 void place(RawLiteral* literal) 4696 4697 4698 4699