Searched refs:BLR (Results 1 – 25 of 27) sorted by relevance
12
| /external/llvm/test/CodeGen/PowerPC/ |
| D | quadint-return.ll | 19 ; CHECK-NEXT: BLR
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCEarlyReturn.cpp | 66 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
|
| D | PPCInstrInfo.cpp | 1304 if (OpC == PPC::BLR || OpC == PPC::BLR8) { in PredicateInstruction()
1466 case PPC::BLR: in isPredicable()
|
| D | PPCFrameLowering.cpp | 1176 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) && in emitEpilogue()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 421 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg)); in LowerPATCHPOINT()
531 Blr.setOpcode(AArch64::BLR); in EmitInstruction()
|
| D | AArch64SchedA57.td | 132 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
|
| D | AArch64FastISel.cpp | 3099 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL); in fastLowerCall()
3132 const MCInstrDesc &II = TII.get(AArch64::BLR); in fastLowerCall()
|
| D | AArch64InstrInfo.td | 1151 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1169 // (which in the usual case is a BLR).
|
| /external/v8/src/arm64/ |
| D | instructions-arm64.h | 335 return Mask(UnconditionalBranchToRegisterMask) == BLR; in IsBranchAndLinkToRegister()
|
| D | constants-arm64.h | 612 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, enumerator
|
| D | assembler-arm64-inl.h | 577 Emit(BLR | Rn(xzr));
|
| D | disasm-arm64.cc | 543 case BLR: mnemonic = "blr"; break; in VisitUnconditionalBranchToRegister()
|
| D | assembler-arm64.cc | 942 Emit(BLR | Rn(xzr)); in EmitPoolGuard()
973 Emit(BLR | Rn(xn)); in blr()
|
| D | simulator-arm64.cc | 1340 case BLR: { in VisitUnconditionalBranchToRegister()
|
| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_64.c | 74 #define BLR 0xd63f0000 macro
1901 PTR_FAIL_IF(push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(TMP_REG1))); in sljit_emit_jump()
1954 return push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(src)); in sljit_emit_ijump()
1964 return push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(TMP_REG1)); in sljit_emit_ijump()
|
| D | sljitNativePPC_common.c | 145 #define BLR (HI(19) | LO(16) | (0x14 << 21)) macro
691 FAIL_IF(push_inst(compiler, BLR)); in sljit_emit_return()
2045 return push_inst(compiler, BLR); in sljit_emit_fast_return()
|
| /external/selinux/policycoreutils/mcstrans/share/examples/nato/setrans.d/ |
| D | eyes-only.conf | 97 ~c228=BLR # Belarus
|
| D | rel.conf | 103 ~c200,~c228=BLR # Belarus
|
| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 639 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, enumerator
|
| D | disasm-a64.cc | 556 case BLR: mnemonic = "blr"; break; in VisitUnconditionalBranchToRegister()
|
| D | simulator-a64.cc | 846 case BLR: in VisitUnconditionalBranchToRegister()
|
| D | assembler-a64.cc | 654 Emit(BLR | Rn(xn)); in blr()
|
| /external/icu/icu4c/source/data/misc/ |
| D | metadata.txt | 2802 BLR{
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 198 ### BLR ### subsection
|
| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/de-DE/ |
| D | de-DE_gl0_kpdf_mgc.pkb | 722 ����D �`�N3-aDP3G=6Oaf,S=L01C9<BLR d3CIM?[UbI;)1A3?;C><AFKU@FMEOW_h51*:04>4:882988@����c���…
|
12