Searched refs:CSEL (Results 1 – 10 of 10) sorted by relevance
| /external/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 569 CSEL W16, W7, W27, EQ
570 CSEL W15, W6, W26, NE
571 CSEL W14, W5, W25, CS
572 CSEL W13, W4, W24, HS
578 CSEL X7, X7, X3, VC
579 CSEL X6, X7, X4, HI
580 CSEL X5, X6, X5, LS
581 CSEL X4, X5, X6, GE
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 741 case AArch64ISD::CSEL: { in computeKnownBitsForTargetNode()
843 case AArch64ISD::CSEL: return "AArch64ISD::CSEL"; in getTargetNodeName()
1717 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal, in LowerXOR()
1779 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal, in LowerXALUO()
3853 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp); in LowerSETCC()
3872 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp); in LowerSETCC()
3882 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp); in LowerSETCC()
3885 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); in LowerSETCC()
3917 unsigned Opcode = AArch64ISD::CSEL; in LowerSELECT_CC()
3992 if (Opcode != AArch64ISD::CSEL) { in LowerSELECT_CC()
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| D | AArch64ISelLowering.h | 43 CSEL, enumerator
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| D | AArch64SchedCyclone.td | 144 // CSEL,CSINC,CSINV,CSNEG
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| D | AArch64InstrInfo.td | 169 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
1064 defm CSEL : CondSelect<0, 0b00, "csel">;
2610 // CSEL instructions providing f128 types need to be handled by a
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 896 CSEL = CSEL_w, enumerator
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| D | assembler-arm64.cc | 1331 ConditionalSelect(rd, rn, rm, cond, CSEL); in csel()
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 1000 CSEL = CSEL_w, enumerator
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| D | assembler-a64.cc | 1135 ConditionalSelect(rd, rn, rm, cond, CSEL); in csel()
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| /external/vixl/doc/ |
| D | supported-instructions.md | 395 ### CSEL ### subsection
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