| /external/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 45 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
120 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, in MoveCopyOutOfITBlock()
168 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg); in MoveCopyOutOfITBlock()
185 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in InsertITInstructions()
208 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); in InsertITInstructions()
225 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg); in InsertITInstructions()
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| D | ARMBaseInstrInfo.h | 140 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { in getPredicate()
142 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() in getPredicate()
450 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
471 ARMCC::CondCodes Pred, unsigned PredReg,
477 ARMCC::CondCodes Pred, unsigned PredReg,
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| D | ARMLoadStoreOptimizer.cpp | 136 ARMCC::CondCodes Pred, unsigned PredReg);
139 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg,
143 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg,
444 ARMCC::CondCodes Pred, unsigned PredReg) { in UpdateBaseRegUses()
579 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, in CreateLoadStoreMulti()
775 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, in CreateLoadStoreDouble()
843 ARMCC::CondCodes Pred = getInstrPredicate(First, PredReg); in MergeOpsUpdate()
1087 ARMCC::CondCodes Pred, unsigned PredReg) { in isIncrementOrDecrement()
1117 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecBefore()
1137 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecAfter()
[all …]
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| D | ThumbRegisterInfo.h | 43 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
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| D | Thumb2InstrInfo.h | 73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| D | ARMBaseInstrInfo.cpp | 168 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); in convertToThreeAddress()
436 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); in ReverseBranchCondition()
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); in SubsumesPredicate()
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); in SubsumesPredicate()
1721 ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg); in isProfitableToIfCvt()
1776 ARMCC::CondCodes
1785 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); in getInstrPredicate()
1809 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstructionImpl()
1918 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); in optimizeSelect()
1999 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate()
[all …]
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| D | MLxExpansionPass.cpp | 284 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); in ExpandFPMLxInstruction()
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| D | ThumbRegisterInfo.cpp | 66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
105 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, in emitLoadConstPool()
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| D | ARMBaseRegisterInfo.h | 163 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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| D | Thumb2SizeReduction.cpp | 157 bool is2Addr, ARMCC::CondCodes Pred,
299 bool is2Addr, ARMCC::CondCodes Pred, in VerifyPredAndCC()
705 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
801 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
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| D | ARMBaseRegisterInfo.cpp | 385 ARMCC::CondCodes Pred, in emitLoadConstPool()
734 ARMCC::CondCodes Pred = (PIdx == -1) in eliminateFrameIndex()
735 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); in eliminateFrameIndex()
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| D | Thumb2InstrInfo.cpp | 61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
219 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
630 ARMCC::CondCodes
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| D | ARMConstantIslandPass.cpp | 1487 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in createNewWater()
1723 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm(); in fixupConditionalBr()
1943 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); in optimizeThumb2Branches()
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| /external/mesa3d/src/mesa/program/ |
| D | prog_execute.c | 460 if (test_cc(machine->CondCodes[GET_SWZ(swizzle, 0)], condMask) || in eval_condition()
461 test_cc(machine->CondCodes[GET_SWZ(swizzle, 1)], condMask) || in eval_condition()
462 test_cc(machine->CondCodes[GET_SWZ(swizzle, 2)], condMask) || in eval_condition()
463 test_cc(machine->CondCodes[GET_SWZ(swizzle, 3)], condMask)) { in eval_condition()
506 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 0)], in store_vector4()
511 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 1)], in store_vector4()
516 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 2)], in store_vector4()
521 if (!test_cc(machine->CondCodes[GET_SWZ(dstReg->CondSwizzle, 3)], in store_vector4()
545 machine->CondCodes[0] = generate_cc(value[0]); in store_vector4()
547 machine->CondCodes[1] = generate_cc(value[1]); in store_vector4()
[all …]
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| D | prog_execute.h | 66 GLuint CondCodes[4]; /**< COND_* value for x/y/z/w */ member
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 131 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in ReverseBranchCondition()
226 MSP430CC::CondCodes BranchCode = in AnalyzeBranch()
227 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); in AnalyzeBranch()
249 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in AnalyzeBranch()
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| D | MSP430.h | 23 enum CondCodes { enum
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 29 enum CondCodes { // Meaning (integer) Meaning (floating-point) enum
47 inline static CondCodes getOppositeCondition(CondCodes CC) { in getOppositeCondition()
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { in ARMCondCodeToString()
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| /external/mesa3d/src/mesa/swrast/ |
| D | s_fragprog.c | 198 machine->CondCodes[0] = COND_EQ; in init_machine()
199 machine->CondCodes[1] = COND_EQ; in init_machine()
200 machine->CondCodes[2] = COND_EQ; in init_machine()
201 machine->CondCodes[3] = COND_EQ; in init_machine()
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| /external/llvm/lib/Target/Sparc/ |
| D | Sparc.h | 42 enum CondCodes { enum
79 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { in SPARCCondCodeToString()
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| D | SparcInstrInfo.cpp | 87 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) in GetOppositeBranchCondition()
181 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); in AnalyzeBranch()
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| /external/mesa3d/src/mesa/tnl/ |
| D | t_vb_program.c | 252 machine->CondCodes[0] = COND_EQ; in init_machine()
253 machine->CondCodes[1] = COND_EQ; in init_machine()
254 machine->CondCodes[2] = COND_EQ; in init_machine()
255 machine->CondCodes[3] = COND_EQ; in init_machine()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTX.h | 34 enum CondCodes { enum
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| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| D | SparcInstPrinter.cpp | 170 O << SPARCCondCodeToString((SPCC::CondCodes)CC); in printCCOperand()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 998 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printPredicateOperand()
1010 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); in printMandatoryPredicateOperand()
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