| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.td | 51 def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
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| D | AMDGPUISelLowering.h | 120 FMIN, enumerator
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| D | AMDGPUISelLowering.cpp | 133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
348 NODE_NAME_CASE(FMIN) in getTargetNodeName()
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| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 794 X86_INTRINSIC_DATA(avx512_mask_min_pd_128, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
795 X86_INTRINSIC_DATA(avx512_mask_min_pd_256, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
796 X86_INTRINSIC_DATA(avx512_mask_min_pd_512, INTR_TYPE_2OP_MASK, X86ISD::FMIN,
798 X86_INTRINSIC_DATA(avx512_mask_min_ps_128, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
799 X86_INTRINSIC_DATA(avx512_mask_min_ps_256, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
800 X86_INTRINSIC_DATA(avx512_mask_min_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FMIN,
803 X86ISD::FMIN, X86ISD::FMIN_RND),
805 X86ISD::FMIN, X86ISD::FMIN_RND),
1647 X86_INTRINSIC_DATA(avx_min_pd_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
1648 X86_INTRINSIC_DATA(avx_min_ps_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
[all …]
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| D | X86ISelLowering.h | 250 FMAX, FMIN, enumerator
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| D | X86InstrFragmentsSIMD.td | 44 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
47 // Commutative and Associative FMIN and FMAX.
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| D | README-SSE.txt | 332 specified. We should turn int_x86_sse_max_ss and X86ISD::FMIN etc. into other
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| D | X86ISelLowering.cpp | 20199 case X86ISD::FMIN: in ReplaceNodeResults()
20474 case X86ISD::FMIN: return "X86ISD::FMIN"; in getTargetNodeName()
23999 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
24007 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
24016 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
24064 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
24071 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
24080 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
26788 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX); in PerformFMinFMaxCombine()
26799 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break; in PerformFMinFMaxCombine()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 459 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
461 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
463 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
465 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
467 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
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| D | AArch64InstrInfo.td | 2537 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;
2876 defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminnan>;
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1094 FMIN = FPDataProcessing2SourceFixed | 0x00005000, enumerator
1095 FMIN_s = FMIN,
1096 FMIN_d = FMIN | FP64,
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| D | disasm-arm64.cc | 1003 FORMAT(FMIN, "fmin"); in VisitFPDataProcessing2Source()
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| D | assembler-arm64.cc | 1856 FPDataProcessing2Source(fd, fn, fm, FMIN); in fmin()
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 1204 FMIN = FPDataProcessing2SourceFixed | 0x00005000, enumerator
1205 FMIN_s = FMIN,
1206 FMIN_d = FMIN | FP64,
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| D | disasm-a64.cc | 1143 FORMAT(FMIN, "fmin"); in VisitFPDataProcessing2Source()
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| D | assembler-a64.cc | 3275 V(fmin, NEON_FMIN, FMIN) \
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| /external/vixl/doc/ |
| D | supported-instructions.md | 2151 ### FMIN ### subsection
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