| /external/llvm/test/CodeGen/Mips/ |
| D | fcopysign.ll | 19 ; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
20 ; 32R2: mthc1 $[[INS]], $f0
31 ; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1
32 ; 64R2: dmtc1 $[[INS]], $f0
52 ; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1
53 ; 32R2: mtc1 $[[INS]], $f0
|
| D | fcopysign-f32-f64.ll | 22 ; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
23 ; 64R2: mtc1 $[[INS]], $f0
46 ; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
47 ; 64R2: dmtc1 $[[INS]], $f0
|
| /external/valgrind/ |
| D | README.aarch64 | 177 MOVs to vector registers instead of INS Vd.D[0], Xreg, to avoid false
179 the semantics of INS Vd.D[0] to see if it zeroes out the top.)
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 635 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
643 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
652 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1) in emitInterruptPrologueStub()
|
| D | MipsSchedule.td | 82 def II_INS : InstrItinClass; // Any INS instruction
|
| D | MipsInstrInfo.td | 1694 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
|
| /external/v8/src/mips/ |
| D | constants-mips.h | 464 INS = ((0U << 3) + 4), enumerator
1169 case INS: in InstructionType()
|
| D | disasm-mips.cc | 1237 case INS: { in DecodeTypeRegisterSPECIAL3()
|
| D | assembler-mips.cc | 2043 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS); in ins_()
|
| D | simulator-mips.cc | 3776 case INS: { // Mips32r2 instruction. in DecodeTypeRegisterSPECIAL3()
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 492 INS = ((0U << 3) + 4), enumerator
1228 case INS: in InstructionType()
|
| D | disasm-mips64.cc | 1451 case INS: { in DecodeTypeRegisterSPECIAL3()
|
| D | assembler-mips64.cc | 2402 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS); in ins_()
|
| D | simulator-mips64.cc | 3851 case INS: { // Mips64r2 instruction. in DecodeTypeRegisterSPECIAL3()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 342 // INS V[x],V[y] is a WriteV.
352 // INS V[x],R
|
| D | AArch64InstrInfo.td | 3688 // AdvSIMD INS/DUP instructions
3827 defm INS : SIMDIns;
3907 // index type and INS extension
3934 ValueType VTScal, Instruction INS> {
3938 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3943 (INS V128:$src, imm:$Immd,
3949 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3957 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3986 // INS.
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 27198 INS v7.u64[0],x19 55555555555555555555555555555555 2320578235e5a500 55555555555555552320578235e5…
27199 INS v7.d[1],x19 55555555555555555555555555555555 5b37ef6695b03794 5b37ef6695b0379455555555555555…
27200 INS v7.s[0],x19 55555555555555555555555555555555 6ddcc967b6252c0d 555555555555555555555555b6252c…
27201 INS v7.s[1],x19 55555555555555555555555555555555 2714f0bbddf85dc4 5555555555555555ddf85dc4555555…
27202 INS v7.s[2],x19 55555555555555555555555555555555 b6ebff0d8e3d14e7 555555558e3d14e755555555555555…
27203 INS v7.s[3],x19 55555555555555555555555555555555 6332dd3f4b31c83a 4b31c83a5555555555555555555555…
27204 INS v7.h[0],x19 55555555555555555555555555555555 5742812852f8ded8 5555555555555555555555555555de…
27205 INS v7.h[1],x19 55555555555555555555555555555555 59b8ae54615a68f0 55555555555555555555555568f055…
27206 INS v7.h[2],x19 55555555555555555555555555555555 8d37b7c77386e88a 55555555555555555555e88a555555…
27207 INS v7.h[3],x19 55555555555555555555555555555555 35293bba83d00c40 55555555555555550c405555555555…
[all …]
|
| /external/ImageMagick/ |
| D | Install-unix.txt | 176 ImageMagick built with delegates (see MAGICK PLUG-INS below) can pose
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 2489 ### INS ### subsection
2499 ### INS ### subsection
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 84 # INS/DUP
172 # INS/DUP (non-standard)
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-advsimd.s | 86 ; INS/DUP
253 ; MOV aliases for the above INS instructions.
|
| /external/valgrind/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-mips32r2-LE | 304 INS
|
| D | MIPS32int.stdout.exp-mips32r2-BE | 304 INS
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 1893 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
|
| /external/valgrind/none/tests/mips64/ |
| D | extract_insert_bit_field.stdout.exp-mips64r2 | 1 --- INS ---
|