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Searched refs:ItinData (Results 1 – 19 of 19) sorted by relevance

/external/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp36 ScheduleHazardRecognizer(), ItinData(II), DAG(SchedDAG), IssueWidth(0), in ScoreboardHazardRecognizer()
47 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer()
49 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer()
52 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
53 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
81 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
120 if (!ItinData || ItinData->isEmpty()) in getHazardType()
135 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
136 *E = ItinData->endStage(idx); IS != E; ++IS) { in getHazardType()
180 if (!ItinData || ItinData->isEmpty()) in EmitInstruction()
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DTargetInstrInfo.cpp982 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
985 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
993 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
995 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
998 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1000 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1006 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1014 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
1016 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1020 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
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/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h281 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
284 int getOperandLatency(const InstrItineraryData *ItinData,
288 int getOperandLatency(const InstrItineraryData *ItinData,
308 int getVLDMDefCycle(const InstrItineraryData *ItinData,
312 int getLDMDefCycle(const InstrItineraryData *ItinData,
316 int getVSTMUseCycle(const InstrItineraryData *ItinData,
320 int getSTMUseCycle(const InstrItineraryData *ItinData,
324 int getOperandLatency(const InstrItineraryData *ItinData,
332 unsigned getInstrLatency(const InstrItineraryData *ItinData,
336 int getInstrLatency(const InstrItineraryData *ItinData,
DARMHazardRecognizer.h35 ARMHazardRecognizer(const InstrItineraryData *ItinData, in ARMHazardRecognizer() argument
37 : ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), in ARMHazardRecognizer()
DARMBaseInstrInfo.cpp2752 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, in getNumMicroOpsSwiftLdSt() argument
2757 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
3007 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
3009 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
3014 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps()
3017 return getNumMicroOpsSwiftLdSt(ItinData, MI); in getNumMicroOps()
3151 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, in getVLDMDefCycle() argument
3158 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3192 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, in getLDMDefCycle() argument
3199 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h115 unsigned getInstrLatency(const InstrItineraryData *ItinData,
119 int getOperandLatency(const InstrItineraryData *ItinData,
123 int getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
126 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
DPPCHazardRecognizers.h35 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, in PPCDispatchGroupSBHazardRecognizer() argument
37 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), in PPCDispatchGroupSBHazardRecognizer()
DPPCInstrInfo.cpp110 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
113 if (!ItinData || UseOldLatencyCalc) in getInstrLatency()
114 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); in getInstrLatency()
130 int Cycle = ItinData->getOperandCycle(DefClass, i); in getInstrLatency()
140 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
144 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, in getOperandLatency()
166 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp71 Record *ItinData, std::string &ItinString,
73 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
76 Record *ItinData,
275 Record *ItinData, in FormItineraryStageString() argument
280 ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
319 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, in FormItineraryOperandCycleString() argument
323 ItinData->getValueAsListOfInts("OperandCycles"); in FormItineraryOperandCycleString()
337 Record *ItinData, in FormItineraryBypassString() argument
341 ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
444 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData() local
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DDFAPacketizerEmitter.cpp136 Record *ItinData,
745 Record *ItinData, in collectOneInsnClass() argument
748 ItinData->getValueAsListOfDefs("Stages"); in collectOneInsnClass()
753 DEBUG(dbgs() << " " << ItinData->getValueAsDef("TheClass")->getName() in collectOneInsnClass()
824 Record *ItinData = ItinDataList[j]; in collectAllInsnClasses() local
826 FUNameToBitsMap, ItinData, OS); in collectAllInsnClasses()
DCodeGenSchedule.cpp784 Record *ItinData = ItinRecords[i]; in collectProcItins() local
785 Record *ItinDef = ItinData->getValueAsDef("TheClass"); in collectProcItins()
791 ProcModel.ItinDefList[SCI->Index] = ItinData; in collectProcItins()
/external/llvm/include/llvm/CodeGen/
DScoreboardHazardRecognizer.h93 const InstrItineraryData *ItinData; variable
107 ScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h1141 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1152 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1164 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1171 unsigned computeOperandLatency(const InstrItineraryData *ItinData,
1179 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1185 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1192 int computeDefOperandLatency(const InstrItineraryData *ItinData,
/external/mesa3d/src/gallium/drivers/radeon/
DR600InstrInfo.h106 int getInstrLatency(const InstrItineraryData *ItinData,
110 virtual int getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
DR600InstrInfo.cpp470 int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.h204 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
208 int getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
DR600InstrInfo.cpp1042 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h237 unsigned getInstrLatency(const InstrItineraryData *ItinData,
367 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
DHexagonInstrInfo.cpp1374 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1376 return getInstrTimingClassLatency(ItinData, MI); in getInstrLatency()
3531 const InstrItineraryData *ItinData, const MachineInstr *MI) const { in getInstrTimingClassLatency() argument
3534 if (!ItinData) in getInstrTimingClassLatency()
3535 return getInstrLatency(ItinData, MI); in getInstrTimingClassLatency()
3542 unsigned Latency = ItinData->getStageLatency(MI->getDesc().getSchedClass()); in getInstrTimingClassLatency()