| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ControlFlowFinalizer.cpp | 336 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), in MakeFetchClause() local
340 return ClauseFile(MIb, std::move(ClauseContent)); in MakeFetchClause()
536 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
541 Pair.second.insert(MIb); in runOnMachineFunction()
561 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
565 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
566 DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
575 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
579 DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
580 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 1181 MachineInstr *MIb) const { in checkInstOffsetsDoNotOverlap()
1186 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
1187 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() && in checkInstOffsetsDoNotOverlap()
1190 unsigned Width1 = (*MIb->memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap()
1201 MachineInstr *MIb, in areMemAccessesTriviallyDisjoint() argument
1205 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) && in areMemAccessesTriviallyDisjoint()
1208 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
1212 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1221 if (isDS(*MIb)) in areMemAccessesTriviallyDisjoint()
1222 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
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| D | SIInstrInfo.h | 66 MachineInstr *MIb) const;
137 MachineInstr *MIa, MachineInstr *MIb,
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 576 MCInst const &MIb, bool ExtendedB, in isOrderedDuplexPair() argument
583 unsigned Opcode = MIb.getOpcode(); in isOrderedDuplexPair()
588 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); in isOrderedDuplexPair()
594 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); in isOrderedDuplexPair()
608 if (MIb.getOpcode() == Hexagon::S2_allocframe) in isOrderedDuplexPair()
620 if (subInstWouldBeExtended(MIb) && !ExtendedB) in isOrderedDuplexPair()
626 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && in isOrderedDuplexPair()
627 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
629 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && in isOrderedDuplexPair()
630 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
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| D | HexagonMCCompound.cpp | 346 MCInst const &MIb, bool IsExtendedB) { in isOrderedCompoundPair() argument
348 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); in isOrderedCompoundPair()
356 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
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| D | HexagonMCInstrInfo.h | 198 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
235 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1352 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
1356 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 569 MachineInstr *MIb) { in MIsNeedChainEdge() argument
574 if (MIa == MIb) in MIsNeedChainEdge()
579 (MIb->mayLoad() || MIb->mayStore())) in MIsNeedChainEdge()
580 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA)) in MIsNeedChainEdge()
584 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand()) in MIsNeedChainEdge()
587 if (isUnsafeMemoryObject(MIa, MFI, DL) || isUnsafeMemoryObject(MIb, MFI, DL)) in MIsNeedChainEdge()
592 if (!MIa->mayStore() && !MIb->mayStore()) in MIsNeedChainEdge()
600 MachineMemOperand *MMOb = *MIb->memoperands_begin(); in MIsNeedChainEdge()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 249 bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
276 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
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| D | HexagonInstrInfo.cpp | 1392 MachineInstr *MIb, AliasAnalysis *AA) const { in areMemAccessesTriviallyDisjoint() argument
1396 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1402 if (MIa->mayLoad() && !isMemOp(MIa) && MIb->mayLoad() && !isMemOp(MIb)) in areMemAccessesTriviallyDisjoint()
1411 unsigned BaseRegB = getBaseAndOffset(MIb, OffsetB, SizeB); in areMemAccessesTriviallyDisjoint()
1776 const MachineInstr *MIb) const { in isDuplexPair()
1778 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb); in isDuplexPair()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 843 static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb, in mayAlias() argument
846 if (!MIa->mayStore() && !MIb->mayStore()) in mayAlias()
850 if (!MIa->mayLoadOrStore() && !MIb->mayLoadOrStore()) in mayAlias()
853 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb); in mayAlias()
859 for (auto &MIb : MemInsns) in mayAlias() local
860 if (mayAlias(MIa, MIb, TII)) in mayAlias()
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| D | AArch64InstrInfo.h | 56 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
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| D | AArch64InstrInfo.cpp | 616 MachineInstr *MIb, in areMemAccessesTriviallyDisjoint() argument
624 assert(MIb && MIb->mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
626 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
627 MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
636 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
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