| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 300 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 enumerator
692 case X86II::MRM0m: case X86II::MRM1m: in getMemoryOperandNo()
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| D | X86MCCodeEmitter.cpp | 799 case X86II::MRM0m: case X86II::MRM1m: in EmitVEXOpcodePrefix()
1047 case X86II::MRM0m: case X86II::MRM1m: in DetermineREXPrefix()
1418 case X86II::MRM0m: case X86II::MRM1m: in encodeInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 630 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
634 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
638 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
642 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
647 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src),
651 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, u8imm:$src),
655 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, u8imm:$src),
659 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src),
665 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
669 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
[all …]
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| D | X86Instr3DNow.td | 94 def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
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| D | X86InstrFPStack.td | 249 defm MUL : FPBinary<fmul, MRM1m, "mul">;
529 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst",
531 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst",
533 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst),
672 def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
674 def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
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| D | X86InstrSystem.td | 251 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
394 def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
396 def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
398 def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
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| D | X86InstrArithmetic.td | 532 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
535 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
538 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
541 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
1193 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
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| D | X86InstrCompiler.td | 665 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
691 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
729 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
736 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
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| D | X86InstrInfo.td | 1870 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1874 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
2188 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2189 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2404 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2407 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
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| D | X86InstrFormats.td | 33 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
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| D | X86InstrAVX512.td | 4095 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
6524 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6527 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6530 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6533 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
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| D | X86InstrSSE.td | 3707 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
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| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 110 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, enumerator
742 case X86Local::MRM1m: in emitInstructionSpecifier()
859 case X86Local::MRM0m: case X86Local::MRM1m: in emitDecodePath()
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 55 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1826 case X86II::MRM0m: case X86II::MRM1m: // for instructions that operate on
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