1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
22
23 using namespace llvm;
24
25 #define MRM_MAPPING \
26 MAP(C0, 32) \
27 MAP(C1, 33) \
28 MAP(C2, 34) \
29 MAP(C3, 35) \
30 MAP(C4, 36) \
31 MAP(C5, 37) \
32 MAP(C6, 38) \
33 MAP(C7, 39) \
34 MAP(C8, 40) \
35 MAP(C9, 41) \
36 MAP(CA, 42) \
37 MAP(CB, 43) \
38 MAP(CC, 44) \
39 MAP(CD, 45) \
40 MAP(CE, 46) \
41 MAP(CF, 47) \
42 MAP(D0, 48) \
43 MAP(D1, 49) \
44 MAP(D2, 50) \
45 MAP(D3, 51) \
46 MAP(D4, 52) \
47 MAP(D5, 53) \
48 MAP(D6, 54) \
49 MAP(D7, 55) \
50 MAP(D8, 56) \
51 MAP(D9, 57) \
52 MAP(DA, 58) \
53 MAP(DB, 59) \
54 MAP(DC, 60) \
55 MAP(DD, 61) \
56 MAP(DE, 62) \
57 MAP(DF, 63) \
58 MAP(E0, 64) \
59 MAP(E1, 65) \
60 MAP(E2, 66) \
61 MAP(E3, 67) \
62 MAP(E4, 68) \
63 MAP(E5, 69) \
64 MAP(E6, 70) \
65 MAP(E7, 71) \
66 MAP(E8, 72) \
67 MAP(E9, 73) \
68 MAP(EA, 74) \
69 MAP(EB, 75) \
70 MAP(EC, 76) \
71 MAP(ED, 77) \
72 MAP(EE, 78) \
73 MAP(EF, 79) \
74 MAP(F0, 80) \
75 MAP(F1, 81) \
76 MAP(F2, 82) \
77 MAP(F3, 83) \
78 MAP(F4, 84) \
79 MAP(F5, 85) \
80 MAP(F6, 86) \
81 MAP(F7, 87) \
82 MAP(F8, 88) \
83 MAP(F9, 89) \
84 MAP(FA, 90) \
85 MAP(FB, 91) \
86 MAP(FC, 92) \
87 MAP(FD, 93) \
88 MAP(FE, 94) \
89 MAP(FF, 95)
90
91 // A clone of X86 since we can't depend on something that is generated.
92 namespace X86Local {
93 enum {
94 Pseudo = 0,
95 RawFrm = 1,
96 AddRegFrm = 2,
97 MRMDestReg = 3,
98 MRMDestMem = 4,
99 MRMSrcReg = 5,
100 MRMSrcMem = 6,
101 RawFrmMemOffs = 7,
102 RawFrmSrc = 8,
103 RawFrmDst = 9,
104 RawFrmDstSrc = 10,
105 RawFrmImm8 = 11,
106 RawFrmImm16 = 12,
107 MRMXr = 14, MRMXm = 15,
108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
110 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
111 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
112 #define MAP(from, to) MRM_##from = to,
113 MRM_MAPPING
114 #undef MAP
115 lastMRM
116 };
117
118 enum {
119 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6
120 };
121
122 enum {
123 PS = 1, PD = 2, XS = 3, XD = 4
124 };
125
126 enum {
127 VEX = 1, XOP = 2, EVEX = 3
128 };
129
130 enum {
131 OpSize16 = 1, OpSize32 = 2
132 };
133
134 enum {
135 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
136 };
137 }
138
139 using namespace X86Disassembler;
140
141 /// isRegFormat - Indicates whether a particular form requires the Mod field of
142 /// the ModR/M byte to be 0b11.
143 ///
144 /// @param form - The form of the instruction.
145 /// @return - true if the form implies that Mod must be 0b11, false
146 /// otherwise.
isRegFormat(uint8_t form)147 static bool isRegFormat(uint8_t form) {
148 return (form == X86Local::MRMDestReg ||
149 form == X86Local::MRMSrcReg ||
150 form == X86Local::MRMXr ||
151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
152 }
153
154 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
155 /// Useful for switch statements and the like.
156 ///
157 /// @param init - A reference to the BitsInit to be decoded.
158 /// @return - The field, with the first bit in the BitsInit as the lowest
159 /// order bit.
byteFromBitsInit(BitsInit & init)160 static uint8_t byteFromBitsInit(BitsInit &init) {
161 int width = init.getNumBits();
162
163 assert(width <= 8 && "Field is too large for uint8_t!");
164
165 int index;
166 uint8_t mask = 0x01;
167
168 uint8_t ret = 0;
169
170 for (index = 0; index < width; index++) {
171 if (static_cast<BitInit*>(init.getBit(index))->getValue())
172 ret |= mask;
173
174 mask <<= 1;
175 }
176
177 return ret;
178 }
179
180 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
181 /// name of the field.
182 ///
183 /// @param rec - The record from which to extract the value.
184 /// @param name - The name of the field in the record.
185 /// @return - The field, as translated by byteFromBitsInit().
byteFromRec(const Record * rec,const std::string & name)186 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
187 BitsInit* bits = rec->getValueAsBitsInit(name);
188 return byteFromBitsInit(*bits);
189 }
190
RecognizableInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)191 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
192 const CodeGenInstruction &insn,
193 InstrUID uid) {
194 UID = uid;
195
196 Rec = insn.TheDef;
197 Name = Rec->getName();
198 Spec = &tables.specForUID(UID);
199
200 if (!Rec->isSubClassOf("X86Inst")) {
201 ShouldBeEmitted = false;
202 return;
203 }
204
205 OpPrefix = byteFromRec(Rec, "OpPrefixBits");
206 OpMap = byteFromRec(Rec, "OpMapBits");
207 Opcode = byteFromRec(Rec, "Opcode");
208 Form = byteFromRec(Rec, "FormBits");
209 Encoding = byteFromRec(Rec, "OpEncBits");
210
211 OpSize = byteFromRec(Rec, "OpSizeBits");
212 AdSize = byteFromRec(Rec, "AdSizeBits");
213 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
214 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
215 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
216 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
217 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
218 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
219 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
220 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
221 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
222 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
223 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
224 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
225 CD8_Scale = byteFromRec(Rec, "CD8_Scale");
226
227 Name = Rec->getName();
228 AsmString = Rec->getValueAsString("AsmString");
229
230 Operands = &insn.Operands.OperandList;
231
232 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
233
234 // Check for 64-bit inst which does not require REX
235 Is32Bit = false;
236 Is64Bit = false;
237 // FIXME: Is there some better way to check for In64BitMode?
238 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
239 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
240 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
241 Predicates[i]->getName().find("In32Bit") != Name.npos) {
242 Is32Bit = true;
243 break;
244 }
245 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
246 Is64Bit = true;
247 break;
248 }
249 }
250
251 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
252 ShouldBeEmitted = false;
253 return;
254 }
255
256 // Special case since there is no attribute class for 64-bit and VEX
257 if (Name == "VMASKMOVDQU64") {
258 ShouldBeEmitted = false;
259 return;
260 }
261
262 ShouldBeEmitted = true;
263 }
264
processInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)265 void RecognizableInstr::processInstr(DisassemblerTables &tables,
266 const CodeGenInstruction &insn,
267 InstrUID uid)
268 {
269 // Ignore "asm parser only" instructions.
270 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
271 return;
272
273 RecognizableInstr recogInstr(tables, insn, uid);
274
275 if (recogInstr.shouldBeEmitted()) {
276 recogInstr.emitInstructionSpecifier();
277 recogInstr.emitDecodePath(tables);
278 }
279 }
280
281 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
282 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
283 (HasEVEX_KZ ? n##_KZ : \
284 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
285
insnContext() const286 InstructionContext RecognizableInstr::insnContext() const {
287 InstructionContext insnContext;
288
289 if (Encoding == X86Local::EVEX) {
290 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
291 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
292 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
293 }
294 // VEX_L & VEX_W
295 if (HasVEX_LPrefix && HasVEX_WPrefix) {
296 if (OpPrefix == X86Local::PD)
297 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
298 else if (OpPrefix == X86Local::XS)
299 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
300 else if (OpPrefix == X86Local::XD)
301 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
302 else if (OpPrefix == X86Local::PS)
303 insnContext = EVEX_KB(IC_EVEX_L_W);
304 else {
305 errs() << "Instruction does not use a prefix: " << Name << "\n";
306 llvm_unreachable("Invalid prefix");
307 }
308 } else if (HasVEX_LPrefix) {
309 // VEX_L
310 if (OpPrefix == X86Local::PD)
311 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
312 else if (OpPrefix == X86Local::XS)
313 insnContext = EVEX_KB(IC_EVEX_L_XS);
314 else if (OpPrefix == X86Local::XD)
315 insnContext = EVEX_KB(IC_EVEX_L_XD);
316 else if (OpPrefix == X86Local::PS)
317 insnContext = EVEX_KB(IC_EVEX_L);
318 else {
319 errs() << "Instruction does not use a prefix: " << Name << "\n";
320 llvm_unreachable("Invalid prefix");
321 }
322 }
323 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
324 // EVEX_L2 & VEX_W
325 if (OpPrefix == X86Local::PD)
326 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
327 else if (OpPrefix == X86Local::XS)
328 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
329 else if (OpPrefix == X86Local::XD)
330 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
331 else if (OpPrefix == X86Local::PS)
332 insnContext = EVEX_KB(IC_EVEX_L2_W);
333 else {
334 errs() << "Instruction does not use a prefix: " << Name << "\n";
335 llvm_unreachable("Invalid prefix");
336 }
337 } else if (HasEVEX_L2Prefix) {
338 // EVEX_L2
339 if (OpPrefix == X86Local::PD)
340 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
341 else if (OpPrefix == X86Local::XD)
342 insnContext = EVEX_KB(IC_EVEX_L2_XD);
343 else if (OpPrefix == X86Local::XS)
344 insnContext = EVEX_KB(IC_EVEX_L2_XS);
345 else if (OpPrefix == X86Local::PS)
346 insnContext = EVEX_KB(IC_EVEX_L2);
347 else {
348 errs() << "Instruction does not use a prefix: " << Name << "\n";
349 llvm_unreachable("Invalid prefix");
350 }
351 }
352 else if (HasVEX_WPrefix) {
353 // VEX_W
354 if (OpPrefix == X86Local::PD)
355 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
356 else if (OpPrefix == X86Local::XS)
357 insnContext = EVEX_KB(IC_EVEX_W_XS);
358 else if (OpPrefix == X86Local::XD)
359 insnContext = EVEX_KB(IC_EVEX_W_XD);
360 else if (OpPrefix == X86Local::PS)
361 insnContext = EVEX_KB(IC_EVEX_W);
362 else {
363 errs() << "Instruction does not use a prefix: " << Name << "\n";
364 llvm_unreachable("Invalid prefix");
365 }
366 }
367 // No L, no W
368 else if (OpPrefix == X86Local::PD)
369 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
370 else if (OpPrefix == X86Local::XD)
371 insnContext = EVEX_KB(IC_EVEX_XD);
372 else if (OpPrefix == X86Local::XS)
373 insnContext = EVEX_KB(IC_EVEX_XS);
374 else
375 insnContext = EVEX_KB(IC_EVEX);
376 /// eof EVEX
377 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
378 if (HasVEX_LPrefix && HasVEX_WPrefix) {
379 if (OpPrefix == X86Local::PD)
380 insnContext = IC_VEX_L_W_OPSIZE;
381 else if (OpPrefix == X86Local::XS)
382 insnContext = IC_VEX_L_W_XS;
383 else if (OpPrefix == X86Local::XD)
384 insnContext = IC_VEX_L_W_XD;
385 else if (OpPrefix == X86Local::PS)
386 insnContext = IC_VEX_L_W;
387 else {
388 errs() << "Instruction does not use a prefix: " << Name << "\n";
389 llvm_unreachable("Invalid prefix");
390 }
391 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
392 insnContext = IC_VEX_L_OPSIZE;
393 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
394 insnContext = IC_VEX_W_OPSIZE;
395 else if (OpPrefix == X86Local::PD)
396 insnContext = IC_VEX_OPSIZE;
397 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
398 insnContext = IC_VEX_L_XS;
399 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
400 insnContext = IC_VEX_L_XD;
401 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
402 insnContext = IC_VEX_W_XS;
403 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
404 insnContext = IC_VEX_W_XD;
405 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS)
406 insnContext = IC_VEX_W;
407 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
408 insnContext = IC_VEX_L;
409 else if (OpPrefix == X86Local::XD)
410 insnContext = IC_VEX_XD;
411 else if (OpPrefix == X86Local::XS)
412 insnContext = IC_VEX_XS;
413 else if (OpPrefix == X86Local::PS)
414 insnContext = IC_VEX;
415 else {
416 errs() << "Instruction does not use a prefix: " << Name << "\n";
417 llvm_unreachable("Invalid prefix");
418 }
419 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
420 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
421 insnContext = IC_64BIT_REXW_OPSIZE;
422 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
423 insnContext = IC_64BIT_REXW_ADSIZE;
424 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
425 insnContext = IC_64BIT_XD_OPSIZE;
426 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
427 insnContext = IC_64BIT_XS_OPSIZE;
428 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
429 insnContext = IC_64BIT_OPSIZE_ADSIZE;
430 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
431 insnContext = IC_64BIT_OPSIZE;
432 else if (AdSize == X86Local::AdSize32)
433 insnContext = IC_64BIT_ADSIZE;
434 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
435 insnContext = IC_64BIT_REXW_XS;
436 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
437 insnContext = IC_64BIT_REXW_XD;
438 else if (OpPrefix == X86Local::XD)
439 insnContext = IC_64BIT_XD;
440 else if (OpPrefix == X86Local::XS)
441 insnContext = IC_64BIT_XS;
442 else if (HasREX_WPrefix)
443 insnContext = IC_64BIT_REXW;
444 else
445 insnContext = IC_64BIT;
446 } else {
447 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
448 insnContext = IC_XD_OPSIZE;
449 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
450 insnContext = IC_XS_OPSIZE;
451 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
452 insnContext = IC_OPSIZE_ADSIZE;
453 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
454 insnContext = IC_OPSIZE;
455 else if (AdSize == X86Local::AdSize16)
456 insnContext = IC_ADSIZE;
457 else if (OpPrefix == X86Local::XD)
458 insnContext = IC_XD;
459 else if (OpPrefix == X86Local::XS)
460 insnContext = IC_XS;
461 else
462 insnContext = IC;
463 }
464
465 return insnContext;
466 }
467
adjustOperandEncoding(OperandEncoding & encoding)468 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
469 // The scaling factor for AVX512 compressed displacement encoding is an
470 // instruction attribute. Adjust the ModRM encoding type to include the
471 // scale for compressed displacement.
472 if (encoding != ENCODING_RM || CD8_Scale == 0)
473 return;
474 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
475 assert(encoding <= ENCODING_RM_CD64 && "Invalid CDisp scaling");
476 }
477
handleOperand(bool optional,unsigned & operandIndex,unsigned & physicalOperandIndex,unsigned & numPhysicalOperands,const unsigned * operandMapping,OperandEncoding (* encodingFromString)(const std::string &,uint8_t OpSize))478 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
479 unsigned &physicalOperandIndex,
480 unsigned &numPhysicalOperands,
481 const unsigned *operandMapping,
482 OperandEncoding (*encodingFromString)
483 (const std::string&,
484 uint8_t OpSize)) {
485 if (optional) {
486 if (physicalOperandIndex >= numPhysicalOperands)
487 return;
488 } else {
489 assert(physicalOperandIndex < numPhysicalOperands);
490 }
491
492 while (operandMapping[operandIndex] != operandIndex) {
493 Spec->operands[operandIndex].encoding = ENCODING_DUP;
494 Spec->operands[operandIndex].type =
495 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
496 ++operandIndex;
497 }
498
499 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
500
501 OperandEncoding encoding = encodingFromString(typeName, OpSize);
502 // Adjust the encoding type for an operand based on the instruction.
503 adjustOperandEncoding(encoding);
504 Spec->operands[operandIndex].encoding = encoding;
505 Spec->operands[operandIndex].type = typeFromString(typeName,
506 HasREX_WPrefix, OpSize);
507
508 ++operandIndex;
509 ++physicalOperandIndex;
510 }
511
emitInstructionSpecifier()512 void RecognizableInstr::emitInstructionSpecifier() {
513 Spec->name = Name;
514
515 Spec->insnContext = insnContext();
516
517 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
518
519 unsigned numOperands = OperandList.size();
520 unsigned numPhysicalOperands = 0;
521
522 // operandMapping maps from operands in OperandList to their originals.
523 // If operandMapping[i] != i, then the entry is a duplicate.
524 unsigned operandMapping[X86_MAX_OPERANDS];
525 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
526
527 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
528 if (!OperandList[operandIndex].Constraints.empty()) {
529 const CGIOperandList::ConstraintInfo &Constraint =
530 OperandList[operandIndex].Constraints[0];
531 if (Constraint.isTied()) {
532 operandMapping[operandIndex] = operandIndex;
533 operandMapping[Constraint.getTiedOperand()] = operandIndex;
534 } else {
535 ++numPhysicalOperands;
536 operandMapping[operandIndex] = operandIndex;
537 }
538 } else {
539 ++numPhysicalOperands;
540 operandMapping[operandIndex] = operandIndex;
541 }
542 }
543
544 #define HANDLE_OPERAND(class) \
545 handleOperand(false, \
546 operandIndex, \
547 physicalOperandIndex, \
548 numPhysicalOperands, \
549 operandMapping, \
550 class##EncodingFromString);
551
552 #define HANDLE_OPTIONAL(class) \
553 handleOperand(true, \
554 operandIndex, \
555 physicalOperandIndex, \
556 numPhysicalOperands, \
557 operandMapping, \
558 class##EncodingFromString);
559
560 // operandIndex should always be < numOperands
561 unsigned operandIndex = 0;
562 // physicalOperandIndex should always be < numPhysicalOperands
563 unsigned physicalOperandIndex = 0;
564
565 // Given the set of prefix bits, how many additional operands does the
566 // instruction have?
567 unsigned additionalOperands = 0;
568 if (HasVEX_4V || HasVEX_4VOp3)
569 ++additionalOperands;
570 if (HasEVEX_K)
571 ++additionalOperands;
572
573 switch (Form) {
574 default: llvm_unreachable("Unhandled form");
575 case X86Local::RawFrmSrc:
576 HANDLE_OPERAND(relocation);
577 return;
578 case X86Local::RawFrmDst:
579 HANDLE_OPERAND(relocation);
580 return;
581 case X86Local::RawFrmDstSrc:
582 HANDLE_OPERAND(relocation);
583 HANDLE_OPERAND(relocation);
584 return;
585 case X86Local::RawFrm:
586 // Operand 1 (optional) is an address or immediate.
587 // Operand 2 (optional) is an immediate.
588 assert(numPhysicalOperands <= 2 &&
589 "Unexpected number of operands for RawFrm");
590 HANDLE_OPTIONAL(relocation)
591 HANDLE_OPTIONAL(immediate)
592 break;
593 case X86Local::RawFrmMemOffs:
594 // Operand 1 is an address.
595 HANDLE_OPERAND(relocation);
596 break;
597 case X86Local::AddRegFrm:
598 // Operand 1 is added to the opcode.
599 // Operand 2 (optional) is an address.
600 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
601 "Unexpected number of operands for AddRegFrm");
602 HANDLE_OPERAND(opcodeModifier)
603 HANDLE_OPTIONAL(relocation)
604 break;
605 case X86Local::MRMDestReg:
606 // Operand 1 is a register operand in the R/M field.
607 // - In AVX512 there may be a mask operand here -
608 // Operand 2 is a register operand in the Reg/Opcode field.
609 // - In AVX, there is a register operand in the VEX.vvvv field here -
610 // Operand 3 (optional) is an immediate.
611 assert(numPhysicalOperands >= 2 + additionalOperands &&
612 numPhysicalOperands <= 3 + additionalOperands &&
613 "Unexpected number of operands for MRMDestRegFrm");
614
615 HANDLE_OPERAND(rmRegister)
616 if (HasEVEX_K)
617 HANDLE_OPERAND(writemaskRegister)
618
619 if (HasVEX_4V)
620 // FIXME: In AVX, the register below becomes the one encoded
621 // in ModRMVEX and the one above the one in the VEX.VVVV field
622 HANDLE_OPERAND(vvvvRegister)
623
624 HANDLE_OPERAND(roRegister)
625 HANDLE_OPTIONAL(immediate)
626 break;
627 case X86Local::MRMDestMem:
628 // Operand 1 is a memory operand (possibly SIB-extended)
629 // Operand 2 is a register operand in the Reg/Opcode field.
630 // - In AVX, there is a register operand in the VEX.vvvv field here -
631 // Operand 3 (optional) is an immediate.
632 assert(numPhysicalOperands >= 2 + additionalOperands &&
633 numPhysicalOperands <= 3 + additionalOperands &&
634 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
635
636 HANDLE_OPERAND(memory)
637
638 if (HasEVEX_K)
639 HANDLE_OPERAND(writemaskRegister)
640
641 if (HasVEX_4V)
642 // FIXME: In AVX, the register below becomes the one encoded
643 // in ModRMVEX and the one above the one in the VEX.VVVV field
644 HANDLE_OPERAND(vvvvRegister)
645
646 HANDLE_OPERAND(roRegister)
647 HANDLE_OPTIONAL(immediate)
648 break;
649 case X86Local::MRMSrcReg:
650 // Operand 1 is a register operand in the Reg/Opcode field.
651 // Operand 2 is a register operand in the R/M field.
652 // - In AVX, there is a register operand in the VEX.vvvv field here -
653 // Operand 3 (optional) is an immediate.
654 // Operand 4 (optional) is an immediate.
655
656 assert(numPhysicalOperands >= 2 + additionalOperands &&
657 numPhysicalOperands <= 4 + additionalOperands &&
658 "Unexpected number of operands for MRMSrcRegFrm");
659
660 HANDLE_OPERAND(roRegister)
661
662 if (HasEVEX_K)
663 HANDLE_OPERAND(writemaskRegister)
664
665 if (HasVEX_4V)
666 // FIXME: In AVX, the register below becomes the one encoded
667 // in ModRMVEX and the one above the one in the VEX.VVVV field
668 HANDLE_OPERAND(vvvvRegister)
669
670 if (HasMemOp4Prefix)
671 HANDLE_OPERAND(immediate)
672
673 HANDLE_OPERAND(rmRegister)
674
675 if (HasVEX_4VOp3)
676 HANDLE_OPERAND(vvvvRegister)
677
678 if (!HasMemOp4Prefix)
679 HANDLE_OPTIONAL(immediate)
680 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
681 HANDLE_OPTIONAL(immediate)
682 break;
683 case X86Local::MRMSrcMem:
684 // Operand 1 is a register operand in the Reg/Opcode field.
685 // Operand 2 is a memory operand (possibly SIB-extended)
686 // - In AVX, there is a register operand in the VEX.vvvv field here -
687 // Operand 3 (optional) is an immediate.
688
689 assert(numPhysicalOperands >= 2 + additionalOperands &&
690 numPhysicalOperands <= 4 + additionalOperands &&
691 "Unexpected number of operands for MRMSrcMemFrm");
692
693 HANDLE_OPERAND(roRegister)
694
695 if (HasEVEX_K)
696 HANDLE_OPERAND(writemaskRegister)
697
698 if (HasVEX_4V)
699 // FIXME: In AVX, the register below becomes the one encoded
700 // in ModRMVEX and the one above the one in the VEX.VVVV field
701 HANDLE_OPERAND(vvvvRegister)
702
703 if (HasMemOp4Prefix)
704 HANDLE_OPERAND(immediate)
705
706 HANDLE_OPERAND(memory)
707
708 if (HasVEX_4VOp3)
709 HANDLE_OPERAND(vvvvRegister)
710
711 if (!HasMemOp4Prefix)
712 HANDLE_OPTIONAL(immediate)
713 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
714 break;
715 case X86Local::MRMXr:
716 case X86Local::MRM0r:
717 case X86Local::MRM1r:
718 case X86Local::MRM2r:
719 case X86Local::MRM3r:
720 case X86Local::MRM4r:
721 case X86Local::MRM5r:
722 case X86Local::MRM6r:
723 case X86Local::MRM7r:
724 // Operand 1 is a register operand in the R/M field.
725 // Operand 2 (optional) is an immediate or relocation.
726 // Operand 3 (optional) is an immediate.
727 assert(numPhysicalOperands >= 0 + additionalOperands &&
728 numPhysicalOperands <= 3 + additionalOperands &&
729 "Unexpected number of operands for MRMnr");
730
731 if (HasVEX_4V)
732 HANDLE_OPERAND(vvvvRegister)
733
734 if (HasEVEX_K)
735 HANDLE_OPERAND(writemaskRegister)
736 HANDLE_OPTIONAL(rmRegister)
737 HANDLE_OPTIONAL(relocation)
738 HANDLE_OPTIONAL(immediate)
739 break;
740 case X86Local::MRMXm:
741 case X86Local::MRM0m:
742 case X86Local::MRM1m:
743 case X86Local::MRM2m:
744 case X86Local::MRM3m:
745 case X86Local::MRM4m:
746 case X86Local::MRM5m:
747 case X86Local::MRM6m:
748 case X86Local::MRM7m:
749 // Operand 1 is a memory operand (possibly SIB-extended)
750 // Operand 2 (optional) is an immediate or relocation.
751 assert(numPhysicalOperands >= 1 + additionalOperands &&
752 numPhysicalOperands <= 2 + additionalOperands &&
753 "Unexpected number of operands for MRMnm");
754
755 if (HasVEX_4V)
756 HANDLE_OPERAND(vvvvRegister)
757 if (HasEVEX_K)
758 HANDLE_OPERAND(writemaskRegister)
759 HANDLE_OPERAND(memory)
760 HANDLE_OPTIONAL(relocation)
761 break;
762 case X86Local::RawFrmImm8:
763 // operand 1 is a 16-bit immediate
764 // operand 2 is an 8-bit immediate
765 assert(numPhysicalOperands == 2 &&
766 "Unexpected number of operands for X86Local::RawFrmImm8");
767 HANDLE_OPERAND(immediate)
768 HANDLE_OPERAND(immediate)
769 break;
770 case X86Local::RawFrmImm16:
771 // operand 1 is a 16-bit immediate
772 // operand 2 is a 16-bit immediate
773 HANDLE_OPERAND(immediate)
774 HANDLE_OPERAND(immediate)
775 break;
776 case X86Local::MRM_F8:
777 if (Opcode == 0xc6) {
778 assert(numPhysicalOperands == 1 &&
779 "Unexpected number of operands for X86Local::MRM_F8");
780 HANDLE_OPERAND(immediate)
781 } else if (Opcode == 0xc7) {
782 assert(numPhysicalOperands == 1 &&
783 "Unexpected number of operands for X86Local::MRM_F8");
784 HANDLE_OPERAND(relocation)
785 }
786 break;
787 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2:
788 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8:
789 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB:
790 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1:
791 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6:
792 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9:
793 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC:
794 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF:
795 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2:
796 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5:
797 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA:
798 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED:
799 case X86Local::MRM_EE: case X86Local::MRM_F0: case X86Local::MRM_F1:
800 case X86Local::MRM_F2: case X86Local::MRM_F3: case X86Local::MRM_F4:
801 case X86Local::MRM_F5: case X86Local::MRM_F6: case X86Local::MRM_F7:
802 case X86Local::MRM_F9: case X86Local::MRM_FA: case X86Local::MRM_FB:
803 case X86Local::MRM_FC: case X86Local::MRM_FD: case X86Local::MRM_FE:
804 case X86Local::MRM_FF:
805 // Ignored.
806 break;
807 }
808
809 #undef HANDLE_OPERAND
810 #undef HANDLE_OPTIONAL
811 }
812
emitDecodePath(DisassemblerTables & tables) const813 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
814 // Special cases where the LLVM tables are not complete
815
816 #define MAP(from, to) \
817 case X86Local::MRM_##from:
818
819 OpcodeType opcodeType = (OpcodeType)-1;
820
821 ModRMFilter* filter = nullptr;
822 uint8_t opcodeToSet = 0;
823
824 switch (OpMap) {
825 default: llvm_unreachable("Invalid map!");
826 case X86Local::OB:
827 case X86Local::TB:
828 case X86Local::T8:
829 case X86Local::TA:
830 case X86Local::XOP8:
831 case X86Local::XOP9:
832 case X86Local::XOPA:
833 switch (OpMap) {
834 default: llvm_unreachable("Unexpected map!");
835 case X86Local::OB: opcodeType = ONEBYTE; break;
836 case X86Local::TB: opcodeType = TWOBYTE; break;
837 case X86Local::T8: opcodeType = THREEBYTE_38; break;
838 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
839 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
840 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
841 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
842 }
843
844 switch (Form) {
845 default:
846 filter = new DumbFilter();
847 break;
848 case X86Local::MRMDestReg: case X86Local::MRMDestMem:
849 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
850 case X86Local::MRMXr: case X86Local::MRMXm:
851 filter = new ModFilter(isRegFormat(Form));
852 break;
853 case X86Local::MRM0r: case X86Local::MRM1r:
854 case X86Local::MRM2r: case X86Local::MRM3r:
855 case X86Local::MRM4r: case X86Local::MRM5r:
856 case X86Local::MRM6r: case X86Local::MRM7r:
857 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
858 break;
859 case X86Local::MRM0m: case X86Local::MRM1m:
860 case X86Local::MRM2m: case X86Local::MRM3m:
861 case X86Local::MRM4m: case X86Local::MRM5m:
862 case X86Local::MRM6m: case X86Local::MRM7m:
863 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
864 break;
865 MRM_MAPPING
866 filter = new ExactFilter(0xC0 + Form - X86Local::MRM_C0); \
867 break;
868 } // switch (Form)
869
870 opcodeToSet = Opcode;
871 break;
872 } // switch (OpMap)
873
874 unsigned AddressSize = 0;
875 switch (AdSize) {
876 case X86Local::AdSize16: AddressSize = 16; break;
877 case X86Local::AdSize32: AddressSize = 32; break;
878 case X86Local::AdSize64: AddressSize = 64; break;
879 }
880
881 assert(opcodeType != (OpcodeType)-1 &&
882 "Opcode type not set");
883 assert(filter && "Filter not set");
884
885 if (Form == X86Local::AddRegFrm) {
886 assert(((opcodeToSet & 7) == 0) &&
887 "ADDREG_FRM opcode not aligned");
888
889 uint8_t currentOpcode;
890
891 for (currentOpcode = opcodeToSet;
892 currentOpcode < opcodeToSet + 8;
893 ++currentOpcode)
894 tables.setTableFields(opcodeType,
895 insnContext(),
896 currentOpcode,
897 *filter,
898 UID, Is32Bit, IgnoresVEX_L, AddressSize);
899 } else {
900 tables.setTableFields(opcodeType,
901 insnContext(),
902 opcodeToSet,
903 *filter,
904 UID, Is32Bit, IgnoresVEX_L, AddressSize);
905 }
906
907 delete filter;
908
909 #undef MAP
910 }
911
912 #define TYPE(str, type) if (s == str) return type;
typeFromString(const std::string & s,bool hasREX_WPrefix,uint8_t OpSize)913 OperandType RecognizableInstr::typeFromString(const std::string &s,
914 bool hasREX_WPrefix,
915 uint8_t OpSize) {
916 if(hasREX_WPrefix) {
917 // For instructions with a REX_W prefix, a declared 32-bit register encoding
918 // is special.
919 TYPE("GR32", TYPE_R32)
920 }
921 if(OpSize == X86Local::OpSize16) {
922 // For OpSize16 instructions, a declared 16-bit register or
923 // immediate encoding is special.
924 TYPE("GR16", TYPE_Rv)
925 TYPE("i16imm", TYPE_IMMv)
926 } else if(OpSize == X86Local::OpSize32) {
927 // For OpSize32 instructions, a declared 32-bit register or
928 // immediate encoding is special.
929 TYPE("GR32", TYPE_Rv)
930 }
931 TYPE("i16mem", TYPE_Mv)
932 TYPE("i16imm", TYPE_IMM16)
933 TYPE("i16i8imm", TYPE_IMMv)
934 TYPE("GR16", TYPE_R16)
935 TYPE("i32mem", TYPE_Mv)
936 TYPE("i32imm", TYPE_IMMv)
937 TYPE("i32i8imm", TYPE_IMM32)
938 TYPE("GR32", TYPE_R32)
939 TYPE("GR32orGR64", TYPE_R32)
940 TYPE("i64mem", TYPE_Mv)
941 TYPE("i64i32imm", TYPE_IMM64)
942 TYPE("i64i8imm", TYPE_IMM64)
943 TYPE("GR64", TYPE_R64)
944 TYPE("i8mem", TYPE_M8)
945 TYPE("i8imm", TYPE_IMM8)
946 TYPE("u8imm", TYPE_UIMM8)
947 TYPE("i32u8imm", TYPE_UIMM8)
948 TYPE("GR8", TYPE_R8)
949 TYPE("VR128", TYPE_XMM128)
950 TYPE("VR128X", TYPE_XMM128)
951 TYPE("f128mem", TYPE_M128)
952 TYPE("f256mem", TYPE_M256)
953 TYPE("f512mem", TYPE_M512)
954 TYPE("FR128", TYPE_XMM128)
955 TYPE("FR64", TYPE_XMM64)
956 TYPE("FR64X", TYPE_XMM64)
957 TYPE("f64mem", TYPE_M64FP)
958 TYPE("sdmem", TYPE_M64FP)
959 TYPE("FR32", TYPE_XMM32)
960 TYPE("FR32X", TYPE_XMM32)
961 TYPE("f32mem", TYPE_M32FP)
962 TYPE("ssmem", TYPE_M32FP)
963 TYPE("RST", TYPE_ST)
964 TYPE("i128mem", TYPE_M128)
965 TYPE("i256mem", TYPE_M256)
966 TYPE("i512mem", TYPE_M512)
967 TYPE("i64i32imm_pcrel", TYPE_REL64)
968 TYPE("i16imm_pcrel", TYPE_REL16)
969 TYPE("i32imm_pcrel", TYPE_REL32)
970 TYPE("SSECC", TYPE_IMM3)
971 TYPE("XOPCC", TYPE_IMM3)
972 TYPE("AVXCC", TYPE_IMM5)
973 TYPE("AVX512ICC", TYPE_AVX512ICC)
974 TYPE("AVX512RC", TYPE_IMM32)
975 TYPE("brtarget32", TYPE_RELv)
976 TYPE("brtarget16", TYPE_RELv)
977 TYPE("brtarget8", TYPE_REL8)
978 TYPE("f80mem", TYPE_M80FP)
979 TYPE("lea64_32mem", TYPE_LEA)
980 TYPE("lea64mem", TYPE_LEA)
981 TYPE("VR64", TYPE_MM64)
982 TYPE("i64imm", TYPE_IMMv)
983 TYPE("anymem", TYPE_M)
984 TYPE("opaque32mem", TYPE_M1616)
985 TYPE("opaque48mem", TYPE_M1632)
986 TYPE("opaque80mem", TYPE_M1664)
987 TYPE("opaque512mem", TYPE_M512)
988 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
989 TYPE("DEBUG_REG", TYPE_DEBUGREG)
990 TYPE("CONTROL_REG", TYPE_CONTROLREG)
991 TYPE("srcidx8", TYPE_SRCIDX8)
992 TYPE("srcidx16", TYPE_SRCIDX16)
993 TYPE("srcidx32", TYPE_SRCIDX32)
994 TYPE("srcidx64", TYPE_SRCIDX64)
995 TYPE("dstidx8", TYPE_DSTIDX8)
996 TYPE("dstidx16", TYPE_DSTIDX16)
997 TYPE("dstidx32", TYPE_DSTIDX32)
998 TYPE("dstidx64", TYPE_DSTIDX64)
999 TYPE("offset16_8", TYPE_MOFFS8)
1000 TYPE("offset16_16", TYPE_MOFFS16)
1001 TYPE("offset16_32", TYPE_MOFFS32)
1002 TYPE("offset32_8", TYPE_MOFFS8)
1003 TYPE("offset32_16", TYPE_MOFFS16)
1004 TYPE("offset32_32", TYPE_MOFFS32)
1005 TYPE("offset32_64", TYPE_MOFFS64)
1006 TYPE("offset64_8", TYPE_MOFFS8)
1007 TYPE("offset64_16", TYPE_MOFFS16)
1008 TYPE("offset64_32", TYPE_MOFFS32)
1009 TYPE("offset64_64", TYPE_MOFFS64)
1010 TYPE("VR256", TYPE_XMM256)
1011 TYPE("VR256X", TYPE_XMM256)
1012 TYPE("VR512", TYPE_XMM512)
1013 TYPE("VK1", TYPE_VK1)
1014 TYPE("VK1WM", TYPE_VK1)
1015 TYPE("VK2", TYPE_VK2)
1016 TYPE("VK2WM", TYPE_VK2)
1017 TYPE("VK4", TYPE_VK4)
1018 TYPE("VK4WM", TYPE_VK4)
1019 TYPE("VK8", TYPE_VK8)
1020 TYPE("VK8WM", TYPE_VK8)
1021 TYPE("VK16", TYPE_VK16)
1022 TYPE("VK16WM", TYPE_VK16)
1023 TYPE("VK32", TYPE_VK32)
1024 TYPE("VK32WM", TYPE_VK32)
1025 TYPE("VK64", TYPE_VK64)
1026 TYPE("VK64WM", TYPE_VK64)
1027 TYPE("GR16_NOAX", TYPE_Rv)
1028 TYPE("GR32_NOAX", TYPE_Rv)
1029 TYPE("GR64_NOAX", TYPE_R64)
1030 TYPE("vx32mem", TYPE_M32)
1031 TYPE("vx32xmem", TYPE_M32)
1032 TYPE("vy32mem", TYPE_M32)
1033 TYPE("vy32xmem", TYPE_M32)
1034 TYPE("vz32mem", TYPE_M32)
1035 TYPE("vx64mem", TYPE_M64)
1036 TYPE("vx64xmem", TYPE_M64)
1037 TYPE("vy64mem", TYPE_M64)
1038 TYPE("vy64xmem", TYPE_M64)
1039 TYPE("vz64mem", TYPE_M64)
1040 TYPE("BNDR", TYPE_BNDR)
1041 errs() << "Unhandled type string " << s << "\n";
1042 llvm_unreachable("Unhandled type string");
1043 }
1044 #undef TYPE
1045
1046 #define ENCODING(str, encoding) if (s == str) return encoding;
1047 OperandEncoding
immediateEncodingFromString(const std::string & s,uint8_t OpSize)1048 RecognizableInstr::immediateEncodingFromString(const std::string &s,
1049 uint8_t OpSize) {
1050 if(OpSize != X86Local::OpSize16) {
1051 // For instructions without an OpSize prefix, a declared 16-bit register or
1052 // immediate encoding is special.
1053 ENCODING("i16imm", ENCODING_IW)
1054 }
1055 ENCODING("i32i8imm", ENCODING_IB)
1056 ENCODING("SSECC", ENCODING_IB)
1057 ENCODING("XOPCC", ENCODING_IB)
1058 ENCODING("AVXCC", ENCODING_IB)
1059 ENCODING("AVX512ICC", ENCODING_IB)
1060 ENCODING("AVX512RC", ENCODING_IB)
1061 ENCODING("i16imm", ENCODING_Iv)
1062 ENCODING("i16i8imm", ENCODING_IB)
1063 ENCODING("i32imm", ENCODING_Iv)
1064 ENCODING("i64i32imm", ENCODING_ID)
1065 ENCODING("i64i8imm", ENCODING_IB)
1066 ENCODING("i8imm", ENCODING_IB)
1067 ENCODING("u8imm", ENCODING_IB)
1068 ENCODING("i32u8imm", ENCODING_IB)
1069 // This is not a typo. Instructions like BLENDVPD put
1070 // register IDs in 8-bit immediates nowadays.
1071 ENCODING("FR32", ENCODING_IB)
1072 ENCODING("FR64", ENCODING_IB)
1073 ENCODING("FR128", ENCODING_IB)
1074 ENCODING("VR128", ENCODING_IB)
1075 ENCODING("VR256", ENCODING_IB)
1076 ENCODING("FR32X", ENCODING_IB)
1077 ENCODING("FR64X", ENCODING_IB)
1078 ENCODING("VR128X", ENCODING_IB)
1079 ENCODING("VR256X", ENCODING_IB)
1080 ENCODING("VR512", ENCODING_IB)
1081 errs() << "Unhandled immediate encoding " << s << "\n";
1082 llvm_unreachable("Unhandled immediate encoding");
1083 }
1084
1085 OperandEncoding
rmRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1086 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1087 uint8_t OpSize) {
1088 ENCODING("RST", ENCODING_FP)
1089 ENCODING("GR16", ENCODING_RM)
1090 ENCODING("GR32", ENCODING_RM)
1091 ENCODING("GR32orGR64", ENCODING_RM)
1092 ENCODING("GR64", ENCODING_RM)
1093 ENCODING("GR8", ENCODING_RM)
1094 ENCODING("VR128", ENCODING_RM)
1095 ENCODING("VR128X", ENCODING_RM)
1096 ENCODING("FR128", ENCODING_RM)
1097 ENCODING("FR64", ENCODING_RM)
1098 ENCODING("FR32", ENCODING_RM)
1099 ENCODING("FR64X", ENCODING_RM)
1100 ENCODING("FR32X", ENCODING_RM)
1101 ENCODING("VR64", ENCODING_RM)
1102 ENCODING("VR256", ENCODING_RM)
1103 ENCODING("VR256X", ENCODING_RM)
1104 ENCODING("VR512", ENCODING_RM)
1105 ENCODING("VK1", ENCODING_RM)
1106 ENCODING("VK2", ENCODING_RM)
1107 ENCODING("VK4", ENCODING_RM)
1108 ENCODING("VK8", ENCODING_RM)
1109 ENCODING("VK16", ENCODING_RM)
1110 ENCODING("VK32", ENCODING_RM)
1111 ENCODING("VK64", ENCODING_RM)
1112 ENCODING("BNDR", ENCODING_RM)
1113 errs() << "Unhandled R/M register encoding " << s << "\n";
1114 llvm_unreachable("Unhandled R/M register encoding");
1115 }
1116
1117 OperandEncoding
roRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1118 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1119 uint8_t OpSize) {
1120 ENCODING("GR16", ENCODING_REG)
1121 ENCODING("GR32", ENCODING_REG)
1122 ENCODING("GR32orGR64", ENCODING_REG)
1123 ENCODING("GR64", ENCODING_REG)
1124 ENCODING("GR8", ENCODING_REG)
1125 ENCODING("VR128", ENCODING_REG)
1126 ENCODING("FR128", ENCODING_REG)
1127 ENCODING("FR64", ENCODING_REG)
1128 ENCODING("FR32", ENCODING_REG)
1129 ENCODING("VR64", ENCODING_REG)
1130 ENCODING("SEGMENT_REG", ENCODING_REG)
1131 ENCODING("DEBUG_REG", ENCODING_REG)
1132 ENCODING("CONTROL_REG", ENCODING_REG)
1133 ENCODING("VR256", ENCODING_REG)
1134 ENCODING("VR256X", ENCODING_REG)
1135 ENCODING("VR128X", ENCODING_REG)
1136 ENCODING("FR64X", ENCODING_REG)
1137 ENCODING("FR32X", ENCODING_REG)
1138 ENCODING("VR512", ENCODING_REG)
1139 ENCODING("VK1", ENCODING_REG)
1140 ENCODING("VK2", ENCODING_REG)
1141 ENCODING("VK4", ENCODING_REG)
1142 ENCODING("VK8", ENCODING_REG)
1143 ENCODING("VK16", ENCODING_REG)
1144 ENCODING("VK32", ENCODING_REG)
1145 ENCODING("VK64", ENCODING_REG)
1146 ENCODING("VK1WM", ENCODING_REG)
1147 ENCODING("VK2WM", ENCODING_REG)
1148 ENCODING("VK4WM", ENCODING_REG)
1149 ENCODING("VK8WM", ENCODING_REG)
1150 ENCODING("VK16WM", ENCODING_REG)
1151 ENCODING("VK32WM", ENCODING_REG)
1152 ENCODING("VK64WM", ENCODING_REG)
1153 ENCODING("BNDR", ENCODING_REG)
1154 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1155 llvm_unreachable("Unhandled reg/opcode register encoding");
1156 }
1157
1158 OperandEncoding
vvvvRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1159 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1160 uint8_t OpSize) {
1161 ENCODING("GR32", ENCODING_VVVV)
1162 ENCODING("GR64", ENCODING_VVVV)
1163 ENCODING("FR32", ENCODING_VVVV)
1164 ENCODING("FR128", ENCODING_VVVV)
1165 ENCODING("FR64", ENCODING_VVVV)
1166 ENCODING("VR128", ENCODING_VVVV)
1167 ENCODING("VR256", ENCODING_VVVV)
1168 ENCODING("FR32X", ENCODING_VVVV)
1169 ENCODING("FR64X", ENCODING_VVVV)
1170 ENCODING("VR128X", ENCODING_VVVV)
1171 ENCODING("VR256X", ENCODING_VVVV)
1172 ENCODING("VR512", ENCODING_VVVV)
1173 ENCODING("VK1", ENCODING_VVVV)
1174 ENCODING("VK2", ENCODING_VVVV)
1175 ENCODING("VK4", ENCODING_VVVV)
1176 ENCODING("VK8", ENCODING_VVVV)
1177 ENCODING("VK16", ENCODING_VVVV)
1178 ENCODING("VK32", ENCODING_VVVV)
1179 ENCODING("VK64", ENCODING_VVVV)
1180 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1181 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1182 }
1183
1184 OperandEncoding
writemaskRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1185 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1186 uint8_t OpSize) {
1187 ENCODING("VK1WM", ENCODING_WRITEMASK)
1188 ENCODING("VK2WM", ENCODING_WRITEMASK)
1189 ENCODING("VK4WM", ENCODING_WRITEMASK)
1190 ENCODING("VK8WM", ENCODING_WRITEMASK)
1191 ENCODING("VK16WM", ENCODING_WRITEMASK)
1192 ENCODING("VK32WM", ENCODING_WRITEMASK)
1193 ENCODING("VK64WM", ENCODING_WRITEMASK)
1194 errs() << "Unhandled mask register encoding " << s << "\n";
1195 llvm_unreachable("Unhandled mask register encoding");
1196 }
1197
1198 OperandEncoding
memoryEncodingFromString(const std::string & s,uint8_t OpSize)1199 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1200 uint8_t OpSize) {
1201 ENCODING("i16mem", ENCODING_RM)
1202 ENCODING("i32mem", ENCODING_RM)
1203 ENCODING("i64mem", ENCODING_RM)
1204 ENCODING("i8mem", ENCODING_RM)
1205 ENCODING("ssmem", ENCODING_RM)
1206 ENCODING("sdmem", ENCODING_RM)
1207 ENCODING("f128mem", ENCODING_RM)
1208 ENCODING("f256mem", ENCODING_RM)
1209 ENCODING("f512mem", ENCODING_RM)
1210 ENCODING("f64mem", ENCODING_RM)
1211 ENCODING("f32mem", ENCODING_RM)
1212 ENCODING("i128mem", ENCODING_RM)
1213 ENCODING("i256mem", ENCODING_RM)
1214 ENCODING("i512mem", ENCODING_RM)
1215 ENCODING("f80mem", ENCODING_RM)
1216 ENCODING("lea64_32mem", ENCODING_RM)
1217 ENCODING("lea64mem", ENCODING_RM)
1218 ENCODING("anymem", ENCODING_RM)
1219 ENCODING("opaque32mem", ENCODING_RM)
1220 ENCODING("opaque48mem", ENCODING_RM)
1221 ENCODING("opaque80mem", ENCODING_RM)
1222 ENCODING("opaque512mem", ENCODING_RM)
1223 ENCODING("vx32mem", ENCODING_RM)
1224 ENCODING("vx32xmem", ENCODING_RM)
1225 ENCODING("vy32mem", ENCODING_RM)
1226 ENCODING("vy32xmem", ENCODING_RM)
1227 ENCODING("vz32mem", ENCODING_RM)
1228 ENCODING("vx64mem", ENCODING_RM)
1229 ENCODING("vx64xmem", ENCODING_RM)
1230 ENCODING("vy64mem", ENCODING_RM)
1231 ENCODING("vy64xmem", ENCODING_RM)
1232 ENCODING("vz64mem", ENCODING_RM)
1233 errs() << "Unhandled memory encoding " << s << "\n";
1234 llvm_unreachable("Unhandled memory encoding");
1235 }
1236
1237 OperandEncoding
relocationEncodingFromString(const std::string & s,uint8_t OpSize)1238 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1239 uint8_t OpSize) {
1240 if(OpSize != X86Local::OpSize16) {
1241 // For instructions without an OpSize prefix, a declared 16-bit register or
1242 // immediate encoding is special.
1243 ENCODING("i16imm", ENCODING_IW)
1244 }
1245 ENCODING("i16imm", ENCODING_Iv)
1246 ENCODING("i16i8imm", ENCODING_IB)
1247 ENCODING("i32imm", ENCODING_Iv)
1248 ENCODING("i32i8imm", ENCODING_IB)
1249 ENCODING("i64i32imm", ENCODING_ID)
1250 ENCODING("i64i8imm", ENCODING_IB)
1251 ENCODING("i8imm", ENCODING_IB)
1252 ENCODING("u8imm", ENCODING_IB)
1253 ENCODING("i32u8imm", ENCODING_IB)
1254 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1255 ENCODING("i16imm_pcrel", ENCODING_IW)
1256 ENCODING("i32imm_pcrel", ENCODING_ID)
1257 ENCODING("brtarget32", ENCODING_Iv)
1258 ENCODING("brtarget16", ENCODING_Iv)
1259 ENCODING("brtarget8", ENCODING_IB)
1260 ENCODING("i64imm", ENCODING_IO)
1261 ENCODING("offset16_8", ENCODING_Ia)
1262 ENCODING("offset16_16", ENCODING_Ia)
1263 ENCODING("offset16_32", ENCODING_Ia)
1264 ENCODING("offset32_8", ENCODING_Ia)
1265 ENCODING("offset32_16", ENCODING_Ia)
1266 ENCODING("offset32_32", ENCODING_Ia)
1267 ENCODING("offset32_64", ENCODING_Ia)
1268 ENCODING("offset64_8", ENCODING_Ia)
1269 ENCODING("offset64_16", ENCODING_Ia)
1270 ENCODING("offset64_32", ENCODING_Ia)
1271 ENCODING("offset64_64", ENCODING_Ia)
1272 ENCODING("srcidx8", ENCODING_SI)
1273 ENCODING("srcidx16", ENCODING_SI)
1274 ENCODING("srcidx32", ENCODING_SI)
1275 ENCODING("srcidx64", ENCODING_SI)
1276 ENCODING("dstidx8", ENCODING_DI)
1277 ENCODING("dstidx16", ENCODING_DI)
1278 ENCODING("dstidx32", ENCODING_DI)
1279 ENCODING("dstidx64", ENCODING_DI)
1280 errs() << "Unhandled relocation encoding " << s << "\n";
1281 llvm_unreachable("Unhandled relocation encoding");
1282 }
1283
1284 OperandEncoding
opcodeModifierEncodingFromString(const std::string & s,uint8_t OpSize)1285 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1286 uint8_t OpSize) {
1287 ENCODING("GR32", ENCODING_Rv)
1288 ENCODING("GR64", ENCODING_RO)
1289 ENCODING("GR16", ENCODING_Rv)
1290 ENCODING("GR8", ENCODING_RB)
1291 ENCODING("GR16_NOAX", ENCODING_Rv)
1292 ENCODING("GR32_NOAX", ENCODING_Rv)
1293 ENCODING("GR64_NOAX", ENCODING_RO)
1294 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1295 llvm_unreachable("Unhandled opcode modifier encoding");
1296 }
1297 #undef ENCODING
1298